root / hw / qxl.c @ 4b3582b0
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/*
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* Copyright (C) 2010 Red Hat, Inc.
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*
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* written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
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* maintained by Gerd Hoffmann <kraxel@redhat.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu-common.h" |
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#include "qemu-timer.h" |
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#include "qemu-queue.h" |
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#include "monitor.h" |
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#include "sysemu.h" |
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#include "trace.h" |
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#include "qxl.h" |
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/*
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* NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
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* such can be changed by the guest, so to avoid a guest trigerrable
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* abort we just set qxl_guest_bug and set the return to NULL. Still
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* it may happen as a result of emulator bug as well.
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*/
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#undef SPICE_RING_PROD_ITEM
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#define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
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typeof(r) start = r; \ |
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typeof(r) end = r + 1; \
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uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \ |
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typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \ |
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if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \ |
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qxl_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
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"! %p <= %p < %p", (uint8_t *)start, \
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(uint8_t *)m_item, (uint8_t *)end); \ |
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ret = NULL; \
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} else { \
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ret = &m_item->el; \ |
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} \ |
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} |
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#undef SPICE_RING_CONS_ITEM
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#define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
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typeof(r) start = r; \ |
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typeof(r) end = r + 1; \
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uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ |
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typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \ |
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if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \ |
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qxl_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
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"! %p <= %p < %p", (uint8_t *)start, \
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(uint8_t *)m_item, (uint8_t *)end); \ |
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ret = NULL; \
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} else { \
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ret = &m_item->el; \ |
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} \ |
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} |
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#undef ALIGN
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#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) |
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#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" |
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#define QXL_MODE(_x, _y, _b, _o) \
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{ .x_res = _x, \ |
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.y_res = _y, \ |
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.bits = _b, \ |
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.stride = (_x) * (_b) / 8, \
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.x_mili = PIXEL_SIZE * (_x), \ |
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.y_mili = PIXEL_SIZE * (_y), \ |
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.orientation = _o, \ |
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} |
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#define QXL_MODE_16_32(x_res, y_res, orientation) \
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QXL_MODE(x_res, y_res, 16, orientation), \
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QXL_MODE(x_res, y_res, 32, orientation)
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#define QXL_MODE_EX(x_res, y_res) \
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QXL_MODE_16_32(x_res, y_res, 0), \
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QXL_MODE_16_32(y_res, x_res, 1), \
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QXL_MODE_16_32(x_res, y_res, 2), \
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QXL_MODE_16_32(y_res, x_res, 3)
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static QXLMode qxl_modes[] = {
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QXL_MODE_EX(640, 480), |
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QXL_MODE_EX(800, 480), |
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QXL_MODE_EX(800, 600), |
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QXL_MODE_EX(832, 624), |
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QXL_MODE_EX(960, 640), |
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QXL_MODE_EX(1024, 600), |
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QXL_MODE_EX(1024, 768), |
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QXL_MODE_EX(1152, 864), |
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QXL_MODE_EX(1152, 870), |
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QXL_MODE_EX(1280, 720), |
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QXL_MODE_EX(1280, 760), |
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QXL_MODE_EX(1280, 768), |
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QXL_MODE_EX(1280, 800), |
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QXL_MODE_EX(1280, 960), |
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QXL_MODE_EX(1280, 1024), |
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QXL_MODE_EX(1360, 768), |
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QXL_MODE_EX(1366, 768), |
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QXL_MODE_EX(1400, 1050), |
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QXL_MODE_EX(1440, 900), |
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QXL_MODE_EX(1600, 900), |
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QXL_MODE_EX(1600, 1200), |
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QXL_MODE_EX(1680, 1050), |
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QXL_MODE_EX(1920, 1080), |
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#if VGA_RAM_SIZE >= (16 * 1024 * 1024) |
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/* these modes need more than 8 MB video memory */
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QXL_MODE_EX(1920, 1200), |
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QXL_MODE_EX(1920, 1440), |
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QXL_MODE_EX(2048, 1536), |
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QXL_MODE_EX(2560, 1440), |
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QXL_MODE_EX(2560, 1600), |
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#endif
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#if VGA_RAM_SIZE >= (32 * 1024 * 1024) |
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/* these modes need more than 16 MB video memory */
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QXL_MODE_EX(2560, 2048), |
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QXL_MODE_EX(2800, 2100), |
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QXL_MODE_EX(3200, 2400), |
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#endif
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}; |
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static PCIQXLDevice *qxl0;
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static void qxl_send_events(PCIQXLDevice *d, uint32_t events); |
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static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async); |
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static void qxl_reset_memslots(PCIQXLDevice *d); |
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static void qxl_reset_surfaces(PCIQXLDevice *d); |
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static void qxl_ring_set_dirty(PCIQXLDevice *qxl); |
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void qxl_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) |
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{ |
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qxl_send_events(qxl, QXL_INTERRUPT_ERROR); |
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if (qxl->guestdebug) {
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va_list ap; |
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va_start(ap, msg); |
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fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
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vfprintf(stderr, msg, ap); |
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fprintf(stderr, "\n");
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va_end(ap); |
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} |
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} |
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void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
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struct QXLRect *area, struct QXLRect *dirty_rects, |
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uint32_t num_dirty_rects, |
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uint32_t clear_dirty_region, |
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qxl_async_io async, struct QXLCookie *cookie)
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{ |
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trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right, |
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area->top, area->bottom); |
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trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects, |
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clear_dirty_region); |
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if (async == QXL_SYNC) {
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qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area, |
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dirty_rects, num_dirty_rects, clear_dirty_region); |
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} else {
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assert(cookie != NULL);
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spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, |
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clear_dirty_region, (uintptr_t)cookie); |
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} |
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} |
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static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl, |
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uint32_t id) |
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{ |
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trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id); |
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qemu_mutex_lock(&qxl->track_lock); |
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qxl->guest_surfaces.cmds[id] = 0;
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qxl->guest_surfaces.count--; |
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qemu_mutex_unlock(&qxl->track_lock); |
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} |
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static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id, |
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qxl_async_io async) |
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{ |
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QXLCookie *cookie; |
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trace_qxl_spice_destroy_surface_wait(qxl->id, id, async); |
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if (async) {
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cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
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QXL_IO_DESTROY_SURFACE_ASYNC); |
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cookie->u.surface_id = id; |
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spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie); |
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} else {
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qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id); |
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} |
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} |
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static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl) |
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{ |
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trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count, |
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qxl->num_free_res); |
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spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, |
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(uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
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QXL_IO_FLUSH_SURFACES_ASYNC)); |
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} |
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void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, |
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uint32_t count) |
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{ |
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trace_qxl_spice_loadvm_commands(qxl->id, ext, count); |
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qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count); |
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} |
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void qxl_spice_oom(PCIQXLDevice *qxl)
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{ |
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trace_qxl_spice_oom(qxl->id); |
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qxl->ssd.worker->oom(qxl->ssd.worker); |
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} |
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void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
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{ |
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trace_qxl_spice_reset_memslots(qxl->id); |
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qxl->ssd.worker->reset_memslots(qxl->ssd.worker); |
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} |
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static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl) |
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{ |
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trace_qxl_spice_destroy_surfaces_complete(qxl->id); |
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qemu_mutex_lock(&qxl->track_lock); |
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memset(&qxl->guest_surfaces.cmds, 0, sizeof(qxl->guest_surfaces.cmds)); |
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qxl->guest_surfaces.count = 0;
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qemu_mutex_unlock(&qxl->track_lock); |
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} |
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static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async) |
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{ |
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trace_qxl_spice_destroy_surfaces(qxl->id, async); |
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if (async) {
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spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, |
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(uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
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QXL_IO_DESTROY_ALL_SURFACES_ASYNC)); |
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} else {
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qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker); |
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qxl_spice_destroy_surfaces_complete(qxl); |
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} |
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} |
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void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
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{ |
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trace_qxl_spice_reset_image_cache(qxl->id); |
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qxl->ssd.worker->reset_image_cache(qxl->ssd.worker); |
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} |
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void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
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{ |
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trace_qxl_spice_reset_cursor(qxl->id); |
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qxl->ssd.worker->reset_cursor(qxl->ssd.worker); |
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qemu_mutex_lock(&qxl->track_lock); |
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qxl->guest_cursor = 0;
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qemu_mutex_unlock(&qxl->track_lock); |
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} |
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static inline uint32_t msb_mask(uint32_t val) |
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{ |
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uint32_t mask; |
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do {
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mask = ~(val - 1) & val;
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val &= ~mask; |
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} while (mask < val);
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return mask;
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} |
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static ram_addr_t qxl_rom_size(void) |
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{ |
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uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes); |
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rom_size = MAX(rom_size, TARGET_PAGE_SIZE); |
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rom_size = msb_mask(rom_size * 2 - 1); |
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return rom_size;
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} |
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static void init_qxl_rom(PCIQXLDevice *d) |
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{ |
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QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); |
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QXLModes *modes = (QXLModes *)(rom + 1);
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uint32_t ram_header_size; |
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uint32_t surface0_area_size; |
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uint32_t num_pages; |
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uint32_t fb, maxfb = 0;
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int i;
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memset(rom, 0, d->rom_size);
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rom->magic = cpu_to_le32(QXL_ROM_MAGIC); |
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rom->id = cpu_to_le32(d->id); |
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rom->log_level = cpu_to_le32(d->guestdebug); |
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rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
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rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; |
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rom->slot_id_bits = MEMSLOT_SLOT_BITS; |
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rom->slots_start = 1;
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rom->slots_end = NUM_MEMSLOTS - 1;
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rom->n_surfaces = cpu_to_le32(NUM_SURFACES); |
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modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes)); |
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for (i = 0; i < modes->n_modes; i++) { |
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fb = qxl_modes[i].y_res * qxl_modes[i].stride; |
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if (maxfb < fb) {
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maxfb = fb; |
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} |
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modes->modes[i].id = cpu_to_le32(i); |
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modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res); |
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modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res); |
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modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits); |
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modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride); |
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modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili); |
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modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili); |
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modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation); |
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} |
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if (maxfb < VGA_RAM_SIZE && d->id == 0) |
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maxfb = VGA_RAM_SIZE; |
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ram_header_size = ALIGN(sizeof(QXLRam), 4096); |
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surface0_area_size = ALIGN(maxfb, 4096);
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num_pages = d->vga.vram_size; |
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num_pages -= ram_header_size; |
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num_pages -= surface0_area_size; |
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num_pages = num_pages / TARGET_PAGE_SIZE; |
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|
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rom->draw_area_offset = cpu_to_le32(0);
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rom->surface0_area_size = cpu_to_le32(surface0_area_size); |
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rom->pages_offset = cpu_to_le32(surface0_area_size); |
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rom->num_pages = cpu_to_le32(num_pages); |
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rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); |
340 |
|
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d->shadow_rom = *rom; |
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d->rom = rom; |
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d->modes = modes; |
344 |
} |
345 |
|
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static void init_qxl_ram(PCIQXLDevice *d) |
347 |
{ |
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uint8_t *buf; |
349 |
uint64_t *item; |
350 |
|
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buf = d->vga.vram_ptr; |
352 |
d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); |
353 |
d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); |
354 |
d->ram->int_pending = cpu_to_le32(0);
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d->ram->int_mask = cpu_to_le32(0);
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d->ram->update_surface = 0;
|
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SPICE_RING_INIT(&d->ram->cmd_ring); |
358 |
SPICE_RING_INIT(&d->ram->cursor_ring); |
359 |
SPICE_RING_INIT(&d->ram->release_ring); |
360 |
SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item); |
361 |
assert(item); |
362 |
*item = 0;
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qxl_ring_set_dirty(d); |
364 |
} |
365 |
|
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/* can be called from spice server thread context */
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static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end) |
368 |
{ |
369 |
memory_region_set_dirty(mr, addr, end - addr); |
370 |
} |
371 |
|
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static void qxl_rom_set_dirty(PCIQXLDevice *qxl) |
373 |
{ |
374 |
qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
|
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} |
376 |
|
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/* called from spice server thread context only */
|
378 |
static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) |
379 |
{ |
380 |
void *base = qxl->vga.vram_ptr;
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intptr_t offset; |
382 |
|
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offset = ptr - base; |
384 |
offset &= ~(TARGET_PAGE_SIZE-1);
|
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assert(offset < qxl->vga.vram_size); |
386 |
qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE); |
387 |
} |
388 |
|
389 |
/* can be called from spice server thread context */
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static void qxl_ring_set_dirty(PCIQXLDevice *qxl) |
391 |
{ |
392 |
ram_addr_t addr = qxl->shadow_rom.ram_header_offset; |
393 |
ram_addr_t end = qxl->vga.vram_size; |
394 |
qxl_set_dirty(&qxl->vga.vram, addr, end); |
395 |
} |
396 |
|
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/*
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* keep track of some command state, for savevm/loadvm.
|
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* called from spice server thread context only
|
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*/
|
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static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) |
402 |
{ |
403 |
switch (le32_to_cpu(ext->cmd.type)) {
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404 |
case QXL_CMD_SURFACE:
|
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{ |
406 |
QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); |
407 |
|
408 |
if (!cmd) {
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return 1; |
410 |
} |
411 |
uint32_t id = le32_to_cpu(cmd->surface_id); |
412 |
|
413 |
if (id >= NUM_SURFACES) {
|
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qxl_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id, NUM_SURFACES);
|
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return 1; |
416 |
} |
417 |
qemu_mutex_lock(&qxl->track_lock); |
418 |
if (cmd->type == QXL_SURFACE_CMD_CREATE) {
|
419 |
qxl->guest_surfaces.cmds[id] = ext->cmd.data; |
420 |
qxl->guest_surfaces.count++; |
421 |
if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
|
422 |
qxl->guest_surfaces.max = qxl->guest_surfaces.count; |
423 |
} |
424 |
if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
|
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qxl->guest_surfaces.cmds[id] = 0;
|
426 |
qxl->guest_surfaces.count--; |
427 |
} |
428 |
qemu_mutex_unlock(&qxl->track_lock); |
429 |
break;
|
430 |
} |
431 |
case QXL_CMD_CURSOR:
|
432 |
{ |
433 |
QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); |
434 |
|
435 |
if (!cmd) {
|
436 |
return 1; |
437 |
} |
438 |
if (cmd->type == QXL_CURSOR_SET) {
|
439 |
qemu_mutex_lock(&qxl->track_lock); |
440 |
qxl->guest_cursor = ext->cmd.data; |
441 |
qemu_mutex_unlock(&qxl->track_lock); |
442 |
} |
443 |
break;
|
444 |
} |
445 |
} |
446 |
return 0; |
447 |
} |
448 |
|
449 |
/* spice display interface callbacks */
|
450 |
|
451 |
static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) |
452 |
{ |
453 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
454 |
|
455 |
trace_qxl_interface_attach_worker(qxl->id); |
456 |
qxl->ssd.worker = qxl_worker; |
457 |
} |
458 |
|
459 |
static void interface_set_compression_level(QXLInstance *sin, int level) |
460 |
{ |
461 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
462 |
|
463 |
trace_qxl_interface_set_compression_level(qxl->id, level); |
464 |
qxl->shadow_rom.compression_level = cpu_to_le32(level); |
465 |
qxl->rom->compression_level = cpu_to_le32(level); |
466 |
qxl_rom_set_dirty(qxl); |
467 |
} |
468 |
|
469 |
static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) |
470 |
{ |
471 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
472 |
|
473 |
trace_qxl_interface_set_mm_time(qxl->id, mm_time); |
474 |
qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); |
475 |
qxl->rom->mm_clock = cpu_to_le32(mm_time); |
476 |
qxl_rom_set_dirty(qxl); |
477 |
} |
478 |
|
479 |
static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) |
480 |
{ |
481 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
482 |
|
483 |
trace_qxl_interface_get_init_info(qxl->id); |
484 |
info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; |
485 |
info->memslot_id_bits = MEMSLOT_SLOT_BITS; |
486 |
info->num_memslots = NUM_MEMSLOTS; |
487 |
info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; |
488 |
info->internal_groupslot_id = 0;
|
489 |
info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS; |
490 |
info->n_surfaces = NUM_SURFACES; |
491 |
} |
492 |
|
493 |
static const char *qxl_mode_to_string(int mode) |
494 |
{ |
495 |
switch (mode) {
|
496 |
case QXL_MODE_COMPAT:
|
497 |
return "compat"; |
498 |
case QXL_MODE_NATIVE:
|
499 |
return "native"; |
500 |
case QXL_MODE_UNDEFINED:
|
501 |
return "undefined"; |
502 |
case QXL_MODE_VGA:
|
503 |
return "vga"; |
504 |
} |
505 |
return "INVALID"; |
506 |
} |
507 |
|
508 |
static const char *io_port_to_string(uint32_t io_port) |
509 |
{ |
510 |
if (io_port >= QXL_IO_RANGE_SIZE) {
|
511 |
return "out of range"; |
512 |
} |
513 |
static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { |
514 |
[QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
|
515 |
[QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
|
516 |
[QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
|
517 |
[QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
|
518 |
[QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
|
519 |
[QXL_IO_RESET] = "QXL_IO_RESET",
|
520 |
[QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
|
521 |
[QXL_IO_LOG] = "QXL_IO_LOG",
|
522 |
[QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
|
523 |
[QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
|
524 |
[QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
|
525 |
[QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
|
526 |
[QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
|
527 |
[QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
|
528 |
[QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
|
529 |
[QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
|
530 |
[QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
|
531 |
[QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
|
532 |
[QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
|
533 |
[QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
|
534 |
[QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
|
535 |
[QXL_IO_DESTROY_ALL_SURFACES_ASYNC] |
536 |
= "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
|
537 |
[QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
|
538 |
[QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
|
539 |
}; |
540 |
return io_port_to_string[io_port];
|
541 |
} |
542 |
|
543 |
/* called from spice server thread context only */
|
544 |
static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) |
545 |
{ |
546 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
547 |
SimpleSpiceUpdate *update; |
548 |
QXLCommandRing *ring; |
549 |
QXLCommand *cmd; |
550 |
int notify, ret;
|
551 |
|
552 |
trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode)); |
553 |
|
554 |
switch (qxl->mode) {
|
555 |
case QXL_MODE_VGA:
|
556 |
ret = false;
|
557 |
qemu_mutex_lock(&qxl->ssd.lock); |
558 |
if (qxl->ssd.update != NULL) { |
559 |
update = qxl->ssd.update; |
560 |
qxl->ssd.update = NULL;
|
561 |
*ext = update->ext; |
562 |
ret = true;
|
563 |
} |
564 |
qemu_mutex_unlock(&qxl->ssd.lock); |
565 |
if (ret) {
|
566 |
trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); |
567 |
qxl_log_command(qxl, "vga", ext);
|
568 |
} |
569 |
return ret;
|
570 |
case QXL_MODE_COMPAT:
|
571 |
case QXL_MODE_NATIVE:
|
572 |
case QXL_MODE_UNDEFINED:
|
573 |
ring = &qxl->ram->cmd_ring; |
574 |
if (SPICE_RING_IS_EMPTY(ring)) {
|
575 |
return false; |
576 |
} |
577 |
SPICE_RING_CONS_ITEM(qxl, ring, cmd); |
578 |
if (!cmd) {
|
579 |
return false; |
580 |
} |
581 |
ext->cmd = *cmd; |
582 |
ext->group_id = MEMSLOT_GROUP_GUEST; |
583 |
ext->flags = qxl->cmdflags; |
584 |
SPICE_RING_POP(ring, notify); |
585 |
qxl_ring_set_dirty(qxl); |
586 |
if (notify) {
|
587 |
qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); |
588 |
} |
589 |
qxl->guest_primary.commands++; |
590 |
qxl_track_command(qxl, ext); |
591 |
qxl_log_command(qxl, "cmd", ext);
|
592 |
trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); |
593 |
return true; |
594 |
default:
|
595 |
return false; |
596 |
} |
597 |
} |
598 |
|
599 |
/* called from spice server thread context only */
|
600 |
static int interface_req_cmd_notification(QXLInstance *sin) |
601 |
{ |
602 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
603 |
int wait = 1; |
604 |
|
605 |
trace_qxl_ring_command_req_notification(qxl->id); |
606 |
switch (qxl->mode) {
|
607 |
case QXL_MODE_COMPAT:
|
608 |
case QXL_MODE_NATIVE:
|
609 |
case QXL_MODE_UNDEFINED:
|
610 |
SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); |
611 |
qxl_ring_set_dirty(qxl); |
612 |
break;
|
613 |
default:
|
614 |
/* nothing */
|
615 |
break;
|
616 |
} |
617 |
return wait;
|
618 |
} |
619 |
|
620 |
/* called from spice server thread context only */
|
621 |
static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) |
622 |
{ |
623 |
QXLReleaseRing *ring = &d->ram->release_ring; |
624 |
uint64_t *item; |
625 |
int notify;
|
626 |
|
627 |
#define QXL_FREE_BUNCH_SIZE 32 |
628 |
|
629 |
if (ring->prod - ring->cons + 1 == ring->num_items) { |
630 |
/* ring full -- can't push */
|
631 |
return;
|
632 |
} |
633 |
if (!flush && d->oom_running) {
|
634 |
/* collect everything from oom handler before pushing */
|
635 |
return;
|
636 |
} |
637 |
if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
|
638 |
/* collect a bit more before pushing */
|
639 |
return;
|
640 |
} |
641 |
|
642 |
SPICE_RING_PUSH(ring, notify); |
643 |
trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode), |
644 |
d->guest_surfaces.count, d->num_free_res, |
645 |
d->last_release, notify ? "yes" : "no"); |
646 |
trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons, |
647 |
ring->num_items, ring->prod, ring->cons); |
648 |
if (notify) {
|
649 |
qxl_send_events(d, QXL_INTERRUPT_DISPLAY); |
650 |
} |
651 |
SPICE_RING_PROD_ITEM(d, ring, item); |
652 |
if (!item) {
|
653 |
return;
|
654 |
} |
655 |
*item = 0;
|
656 |
d->num_free_res = 0;
|
657 |
d->last_release = NULL;
|
658 |
qxl_ring_set_dirty(d); |
659 |
} |
660 |
|
661 |
/* called from spice server thread context only */
|
662 |
static void interface_release_resource(QXLInstance *sin, |
663 |
struct QXLReleaseInfoExt ext)
|
664 |
{ |
665 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
666 |
QXLReleaseRing *ring; |
667 |
uint64_t *item, id; |
668 |
|
669 |
if (ext.group_id == MEMSLOT_GROUP_HOST) {
|
670 |
/* host group -> vga mode update request */
|
671 |
qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id);
|
672 |
return;
|
673 |
} |
674 |
|
675 |
/*
|
676 |
* ext->info points into guest-visible memory
|
677 |
* pci bar 0, $command.release_info
|
678 |
*/
|
679 |
ring = &qxl->ram->release_ring; |
680 |
SPICE_RING_PROD_ITEM(qxl, ring, item); |
681 |
if (!item) {
|
682 |
return;
|
683 |
} |
684 |
if (*item == 0) { |
685 |
/* stick head into the ring */
|
686 |
id = ext.info->id; |
687 |
ext.info->next = 0;
|
688 |
qxl_ram_set_dirty(qxl, &ext.info->next); |
689 |
*item = id; |
690 |
qxl_ring_set_dirty(qxl); |
691 |
} else {
|
692 |
/* append item to the list */
|
693 |
qxl->last_release->next = ext.info->id; |
694 |
qxl_ram_set_dirty(qxl, &qxl->last_release->next); |
695 |
ext.info->next = 0;
|
696 |
qxl_ram_set_dirty(qxl, &ext.info->next); |
697 |
} |
698 |
qxl->last_release = ext.info; |
699 |
qxl->num_free_res++; |
700 |
trace_qxl_ring_res_put(qxl->id, qxl->num_free_res); |
701 |
qxl_push_free_res(qxl, 0);
|
702 |
} |
703 |
|
704 |
/* called from spice server thread context only */
|
705 |
static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) |
706 |
{ |
707 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
708 |
QXLCursorRing *ring; |
709 |
QXLCommand *cmd; |
710 |
int notify;
|
711 |
|
712 |
trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode)); |
713 |
|
714 |
switch (qxl->mode) {
|
715 |
case QXL_MODE_COMPAT:
|
716 |
case QXL_MODE_NATIVE:
|
717 |
case QXL_MODE_UNDEFINED:
|
718 |
ring = &qxl->ram->cursor_ring; |
719 |
if (SPICE_RING_IS_EMPTY(ring)) {
|
720 |
return false; |
721 |
} |
722 |
SPICE_RING_CONS_ITEM(qxl, ring, cmd); |
723 |
if (!cmd) {
|
724 |
return false; |
725 |
} |
726 |
ext->cmd = *cmd; |
727 |
ext->group_id = MEMSLOT_GROUP_GUEST; |
728 |
ext->flags = qxl->cmdflags; |
729 |
SPICE_RING_POP(ring, notify); |
730 |
qxl_ring_set_dirty(qxl); |
731 |
if (notify) {
|
732 |
qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); |
733 |
} |
734 |
qxl->guest_primary.commands++; |
735 |
qxl_track_command(qxl, ext); |
736 |
qxl_log_command(qxl, "csr", ext);
|
737 |
if (qxl->id == 0) { |
738 |
qxl_render_cursor(qxl, ext); |
739 |
} |
740 |
trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode)); |
741 |
return true; |
742 |
default:
|
743 |
return false; |
744 |
} |
745 |
} |
746 |
|
747 |
/* called from spice server thread context only */
|
748 |
static int interface_req_cursor_notification(QXLInstance *sin) |
749 |
{ |
750 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
751 |
int wait = 1; |
752 |
|
753 |
trace_qxl_ring_cursor_req_notification(qxl->id); |
754 |
switch (qxl->mode) {
|
755 |
case QXL_MODE_COMPAT:
|
756 |
case QXL_MODE_NATIVE:
|
757 |
case QXL_MODE_UNDEFINED:
|
758 |
SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); |
759 |
qxl_ring_set_dirty(qxl); |
760 |
break;
|
761 |
default:
|
762 |
/* nothing */
|
763 |
break;
|
764 |
} |
765 |
return wait;
|
766 |
} |
767 |
|
768 |
/* called from spice server thread context */
|
769 |
static void interface_notify_update(QXLInstance *sin, uint32_t update_id) |
770 |
{ |
771 |
/*
|
772 |
* Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
|
773 |
* use by xf86-video-qxl and is defined out in the qxl windows driver.
|
774 |
* Probably was at some earlier version that is prior to git start (2009),
|
775 |
* and is still guest trigerrable.
|
776 |
*/
|
777 |
fprintf(stderr, "%s: deprecated\n", __func__);
|
778 |
} |
779 |
|
780 |
/* called from spice server thread context only */
|
781 |
static int interface_flush_resources(QXLInstance *sin) |
782 |
{ |
783 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
784 |
int ret;
|
785 |
|
786 |
ret = qxl->num_free_res; |
787 |
if (ret) {
|
788 |
qxl_push_free_res(qxl, 1);
|
789 |
} |
790 |
return ret;
|
791 |
} |
792 |
|
793 |
static void qxl_create_guest_primary_complete(PCIQXLDevice *d); |
794 |
|
795 |
/* called from spice server thread context only */
|
796 |
static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie) |
797 |
{ |
798 |
uint32_t current_async; |
799 |
|
800 |
qemu_mutex_lock(&qxl->async_lock); |
801 |
current_async = qxl->current_async; |
802 |
qxl->current_async = QXL_UNDEFINED_IO; |
803 |
qemu_mutex_unlock(&qxl->async_lock); |
804 |
|
805 |
trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie); |
806 |
if (!cookie) {
|
807 |
fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
|
808 |
return;
|
809 |
} |
810 |
if (cookie && current_async != cookie->io) {
|
811 |
fprintf(stderr, |
812 |
"qxl: %s: error: current_async = %d != %"
|
813 |
PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
|
814 |
} |
815 |
switch (current_async) {
|
816 |
case QXL_IO_MEMSLOT_ADD_ASYNC:
|
817 |
case QXL_IO_DESTROY_PRIMARY_ASYNC:
|
818 |
case QXL_IO_UPDATE_AREA_ASYNC:
|
819 |
case QXL_IO_FLUSH_SURFACES_ASYNC:
|
820 |
break;
|
821 |
case QXL_IO_CREATE_PRIMARY_ASYNC:
|
822 |
qxl_create_guest_primary_complete(qxl); |
823 |
break;
|
824 |
case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
|
825 |
qxl_spice_destroy_surfaces_complete(qxl); |
826 |
break;
|
827 |
case QXL_IO_DESTROY_SURFACE_ASYNC:
|
828 |
qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); |
829 |
break;
|
830 |
default:
|
831 |
fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
|
832 |
current_async); |
833 |
} |
834 |
qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD); |
835 |
} |
836 |
|
837 |
/* called from spice server thread context only */
|
838 |
static void interface_update_area_complete(QXLInstance *sin, |
839 |
uint32_t surface_id, |
840 |
QXLRect *dirty, uint32_t num_updated_rects) |
841 |
{ |
842 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
843 |
int i;
|
844 |
int qxl_i;
|
845 |
|
846 |
qemu_mutex_lock(&qxl->ssd.lock); |
847 |
if (surface_id != 0 || !qxl->render_update_cookie_num) { |
848 |
qemu_mutex_unlock(&qxl->ssd.lock); |
849 |
return;
|
850 |
} |
851 |
trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left, |
852 |
dirty->right, dirty->top, dirty->bottom); |
853 |
trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects); |
854 |
if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
|
855 |
/*
|
856 |
* overflow - treat this as a full update. Not expected to be common.
|
857 |
*/
|
858 |
trace_qxl_interface_update_area_complete_overflow(qxl->id, |
859 |
QXL_NUM_DIRTY_RECTS); |
860 |
qxl->guest_primary.resized = 1;
|
861 |
} |
862 |
if (qxl->guest_primary.resized) {
|
863 |
/*
|
864 |
* Don't bother copying or scheduling the bh since we will flip
|
865 |
* the whole area anyway on completion of the update_area async call
|
866 |
*/
|
867 |
qemu_mutex_unlock(&qxl->ssd.lock); |
868 |
return;
|
869 |
} |
870 |
qxl_i = qxl->num_dirty_rects; |
871 |
for (i = 0; i < num_updated_rects; i++) { |
872 |
qxl->dirty[qxl_i++] = dirty[i]; |
873 |
} |
874 |
qxl->num_dirty_rects += num_updated_rects; |
875 |
trace_qxl_interface_update_area_complete_schedule_bh(qxl->id, |
876 |
qxl->num_dirty_rects); |
877 |
qemu_bh_schedule(qxl->update_area_bh); |
878 |
qemu_mutex_unlock(&qxl->ssd.lock); |
879 |
} |
880 |
|
881 |
/* called from spice server thread context only */
|
882 |
static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token) |
883 |
{ |
884 |
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); |
885 |
QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token; |
886 |
|
887 |
switch (cookie->type) {
|
888 |
case QXL_COOKIE_TYPE_IO:
|
889 |
interface_async_complete_io(qxl, cookie); |
890 |
g_free(cookie); |
891 |
break;
|
892 |
case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
|
893 |
qxl_render_update_area_done(qxl, cookie); |
894 |
break;
|
895 |
default:
|
896 |
fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
|
897 |
__func__, cookie->type); |
898 |
g_free(cookie); |
899 |
} |
900 |
} |
901 |
|
902 |
static const QXLInterface qxl_interface = { |
903 |
.base.type = SPICE_INTERFACE_QXL, |
904 |
.base.description = "qxl gpu",
|
905 |
.base.major_version = SPICE_INTERFACE_QXL_MAJOR, |
906 |
.base.minor_version = SPICE_INTERFACE_QXL_MINOR, |
907 |
|
908 |
.attache_worker = interface_attach_worker, |
909 |
.set_compression_level = interface_set_compression_level, |
910 |
.set_mm_time = interface_set_mm_time, |
911 |
.get_init_info = interface_get_init_info, |
912 |
|
913 |
/* the callbacks below are called from spice server thread context */
|
914 |
.get_command = interface_get_command, |
915 |
.req_cmd_notification = interface_req_cmd_notification, |
916 |
.release_resource = interface_release_resource, |
917 |
.get_cursor_command = interface_get_cursor_command, |
918 |
.req_cursor_notification = interface_req_cursor_notification, |
919 |
.notify_update = interface_notify_update, |
920 |
.flush_resources = interface_flush_resources, |
921 |
.async_complete = interface_async_complete, |
922 |
.update_area_complete = interface_update_area_complete, |
923 |
}; |
924 |
|
925 |
static void qxl_enter_vga_mode(PCIQXLDevice *d) |
926 |
{ |
927 |
if (d->mode == QXL_MODE_VGA) {
|
928 |
return;
|
929 |
} |
930 |
trace_qxl_enter_vga_mode(d->id); |
931 |
qemu_spice_create_host_primary(&d->ssd); |
932 |
d->mode = QXL_MODE_VGA; |
933 |
memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); |
934 |
} |
935 |
|
936 |
static void qxl_exit_vga_mode(PCIQXLDevice *d) |
937 |
{ |
938 |
if (d->mode != QXL_MODE_VGA) {
|
939 |
return;
|
940 |
} |
941 |
trace_qxl_exit_vga_mode(d->id); |
942 |
qxl_destroy_primary(d, QXL_SYNC); |
943 |
} |
944 |
|
945 |
static void qxl_update_irq(PCIQXLDevice *d) |
946 |
{ |
947 |
uint32_t pending = le32_to_cpu(d->ram->int_pending); |
948 |
uint32_t mask = le32_to_cpu(d->ram->int_mask); |
949 |
int level = !!(pending & mask);
|
950 |
qemu_set_irq(d->pci.irq[0], level);
|
951 |
qxl_ring_set_dirty(d); |
952 |
} |
953 |
|
954 |
static void qxl_check_state(PCIQXLDevice *d) |
955 |
{ |
956 |
QXLRam *ram = d->ram; |
957 |
|
958 |
assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); |
959 |
assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); |
960 |
} |
961 |
|
962 |
static void qxl_reset_state(PCIQXLDevice *d) |
963 |
{ |
964 |
QXLRom *rom = d->rom; |
965 |
|
966 |
qxl_check_state(d); |
967 |
d->shadow_rom.update_id = cpu_to_le32(0);
|
968 |
*rom = d->shadow_rom; |
969 |
qxl_rom_set_dirty(d); |
970 |
init_qxl_ram(d); |
971 |
d->num_free_res = 0;
|
972 |
d->last_release = NULL;
|
973 |
memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); |
974 |
} |
975 |
|
976 |
static void qxl_soft_reset(PCIQXLDevice *d) |
977 |
{ |
978 |
trace_qxl_soft_reset(d->id); |
979 |
qxl_check_state(d); |
980 |
|
981 |
if (d->id == 0) { |
982 |
qxl_enter_vga_mode(d); |
983 |
} else {
|
984 |
d->mode = QXL_MODE_UNDEFINED; |
985 |
} |
986 |
} |
987 |
|
988 |
static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) |
989 |
{ |
990 |
trace_qxl_hard_reset(d->id, loadvm); |
991 |
|
992 |
qxl_spice_reset_cursor(d); |
993 |
qxl_spice_reset_image_cache(d); |
994 |
qxl_reset_surfaces(d); |
995 |
qxl_reset_memslots(d); |
996 |
|
997 |
/* pre loadvm reset must not touch QXLRam. This lives in
|
998 |
* device memory, is migrated together with RAM and thus
|
999 |
* already loaded at this point */
|
1000 |
if (!loadvm) {
|
1001 |
qxl_reset_state(d); |
1002 |
} |
1003 |
qemu_spice_create_host_memslot(&d->ssd); |
1004 |
qxl_soft_reset(d); |
1005 |
} |
1006 |
|
1007 |
static void qxl_reset_handler(DeviceState *dev) |
1008 |
{ |
1009 |
PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev); |
1010 |
|
1011 |
qxl_hard_reset(d, 0);
|
1012 |
} |
1013 |
|
1014 |
static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
1015 |
{ |
1016 |
VGACommonState *vga = opaque; |
1017 |
PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); |
1018 |
|
1019 |
trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val); |
1020 |
if (qxl->mode != QXL_MODE_VGA) {
|
1021 |
qxl_destroy_primary(qxl, QXL_SYNC); |
1022 |
qxl_soft_reset(qxl); |
1023 |
} |
1024 |
vga_ioport_write(opaque, addr, val); |
1025 |
} |
1026 |
|
1027 |
static const MemoryRegionPortio qxl_vga_portio_list[] = { |
1028 |
{ 0x04, 2, 1, .read = vga_ioport_read, |
1029 |
.write = qxl_vga_ioport_write }, /* 3b4 */
|
1030 |
{ 0x0a, 1, 1, .read = vga_ioport_read, |
1031 |
.write = qxl_vga_ioport_write }, /* 3ba */
|
1032 |
{ 0x10, 16, 1, .read = vga_ioport_read, |
1033 |
.write = qxl_vga_ioport_write }, /* 3c0 */
|
1034 |
{ 0x24, 2, 1, .read = vga_ioport_read, |
1035 |
.write = qxl_vga_ioport_write }, /* 3d4 */
|
1036 |
{ 0x2a, 1, 1, .read = vga_ioport_read, |
1037 |
.write = qxl_vga_ioport_write }, /* 3da */
|
1038 |
PORTIO_END_OF_LIST(), |
1039 |
}; |
1040 |
|
1041 |
static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta, |
1042 |
qxl_async_io async) |
1043 |
{ |
1044 |
static const int regions[] = { |
1045 |
QXL_RAM_RANGE_INDEX, |
1046 |
QXL_VRAM_RANGE_INDEX, |
1047 |
QXL_VRAM64_RANGE_INDEX, |
1048 |
}; |
1049 |
uint64_t guest_start; |
1050 |
uint64_t guest_end; |
1051 |
int pci_region;
|
1052 |
pcibus_t pci_start; |
1053 |
pcibus_t pci_end; |
1054 |
intptr_t virt_start; |
1055 |
QXLDevMemSlot memslot; |
1056 |
int i;
|
1057 |
|
1058 |
guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); |
1059 |
guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); |
1060 |
|
1061 |
trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end); |
1062 |
|
1063 |
if (slot_id >= NUM_MEMSLOTS) {
|
1064 |
qxl_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
|
1065 |
slot_id, NUM_MEMSLOTS); |
1066 |
return 1; |
1067 |
} |
1068 |
if (guest_start > guest_end) {
|
1069 |
qxl_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
|
1070 |
" > 0x%" PRIx64, __func__, guest_start, guest_end);
|
1071 |
return 1; |
1072 |
} |
1073 |
|
1074 |
for (i = 0; i < ARRAY_SIZE(regions); i++) { |
1075 |
pci_region = regions[i]; |
1076 |
pci_start = d->pci.io_regions[pci_region].addr; |
1077 |
pci_end = pci_start + d->pci.io_regions[pci_region].size; |
1078 |
/* mapped? */
|
1079 |
if (pci_start == -1) { |
1080 |
continue;
|
1081 |
} |
1082 |
/* start address in range ? */
|
1083 |
if (guest_start < pci_start || guest_start > pci_end) {
|
1084 |
continue;
|
1085 |
} |
1086 |
/* end address in range ? */
|
1087 |
if (guest_end > pci_end) {
|
1088 |
continue;
|
1089 |
} |
1090 |
/* passed */
|
1091 |
break;
|
1092 |
} |
1093 |
if (i == ARRAY_SIZE(regions)) {
|
1094 |
qxl_guest_bug(d, "%s: finished loop without match", __func__);
|
1095 |
return 1; |
1096 |
} |
1097 |
|
1098 |
switch (pci_region) {
|
1099 |
case QXL_RAM_RANGE_INDEX:
|
1100 |
virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram); |
1101 |
break;
|
1102 |
case QXL_VRAM_RANGE_INDEX:
|
1103 |
case 4 /* vram 64bit */: |
1104 |
virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar); |
1105 |
break;
|
1106 |
default:
|
1107 |
/* should not happen */
|
1108 |
qxl_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
|
1109 |
return 1; |
1110 |
} |
1111 |
|
1112 |
memslot.slot_id = slot_id; |
1113 |
memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
|
1114 |
memslot.virt_start = virt_start + (guest_start - pci_start); |
1115 |
memslot.virt_end = virt_start + (guest_end - pci_start); |
1116 |
memslot.addr_delta = memslot.virt_start - delta; |
1117 |
memslot.generation = d->rom->slot_generation = 0;
|
1118 |
qxl_rom_set_dirty(d); |
1119 |
|
1120 |
qemu_spice_add_memslot(&d->ssd, &memslot, async); |
1121 |
d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
|
1122 |
d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; |
1123 |
d->guest_slots[slot_id].delta = delta; |
1124 |
d->guest_slots[slot_id].active = 1;
|
1125 |
return 0; |
1126 |
} |
1127 |
|
1128 |
static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) |
1129 |
{ |
1130 |
qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); |
1131 |
d->guest_slots[slot_id].active = 0;
|
1132 |
} |
1133 |
|
1134 |
static void qxl_reset_memslots(PCIQXLDevice *d) |
1135 |
{ |
1136 |
qxl_spice_reset_memslots(d); |
1137 |
memset(&d->guest_slots, 0, sizeof(d->guest_slots)); |
1138 |
} |
1139 |
|
1140 |
static void qxl_reset_surfaces(PCIQXLDevice *d) |
1141 |
{ |
1142 |
trace_qxl_reset_surfaces(d->id); |
1143 |
d->mode = QXL_MODE_UNDEFINED; |
1144 |
qxl_spice_destroy_surfaces(d, QXL_SYNC); |
1145 |
} |
1146 |
|
1147 |
/* can be also called from spice server thread context */
|
1148 |
void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) |
1149 |
{ |
1150 |
uint64_t phys = le64_to_cpu(pqxl); |
1151 |
uint32_t slot = (phys >> (64 - 8)) & 0xff; |
1152 |
uint64_t offset = phys & 0xffffffffffff;
|
1153 |
|
1154 |
switch (group_id) {
|
1155 |
case MEMSLOT_GROUP_HOST:
|
1156 |
return (void *)(intptr_t)offset; |
1157 |
case MEMSLOT_GROUP_GUEST:
|
1158 |
if (slot >= NUM_MEMSLOTS) {
|
1159 |
qxl_guest_bug(qxl, "slot too large %d >= %d", slot, NUM_MEMSLOTS);
|
1160 |
return NULL; |
1161 |
} |
1162 |
if (!qxl->guest_slots[slot].active) {
|
1163 |
qxl_guest_bug(qxl, "inactive slot %d\n", slot);
|
1164 |
return NULL; |
1165 |
} |
1166 |
if (offset < qxl->guest_slots[slot].delta) {
|
1167 |
qxl_guest_bug(qxl, "slot %d offset %"PRIu64" < delta %"PRIu64"\n", |
1168 |
slot, offset, qxl->guest_slots[slot].delta); |
1169 |
return NULL; |
1170 |
} |
1171 |
offset -= qxl->guest_slots[slot].delta; |
1172 |
if (offset > qxl->guest_slots[slot].size) {
|
1173 |
qxl_guest_bug(qxl, "slot %d offset %"PRIu64" > size %"PRIu64"\n", |
1174 |
slot, offset, qxl->guest_slots[slot].size); |
1175 |
return NULL; |
1176 |
} |
1177 |
return qxl->guest_slots[slot].ptr + offset;
|
1178 |
} |
1179 |
return NULL; |
1180 |
} |
1181 |
|
1182 |
static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl) |
1183 |
{ |
1184 |
/* for local rendering */
|
1185 |
qxl_render_resize(qxl); |
1186 |
} |
1187 |
|
1188 |
static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, |
1189 |
qxl_async_io async) |
1190 |
{ |
1191 |
QXLDevSurfaceCreate surface; |
1192 |
QXLSurfaceCreate *sc = &qxl->guest_primary.surface; |
1193 |
|
1194 |
if (qxl->mode == QXL_MODE_NATIVE) {
|
1195 |
qxl_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
|
1196 |
__func__); |
1197 |
} |
1198 |
qxl_exit_vga_mode(qxl); |
1199 |
|
1200 |
surface.format = le32_to_cpu(sc->format); |
1201 |
surface.height = le32_to_cpu(sc->height); |
1202 |
surface.mem = le64_to_cpu(sc->mem); |
1203 |
surface.position = le32_to_cpu(sc->position); |
1204 |
surface.stride = le32_to_cpu(sc->stride); |
1205 |
surface.width = le32_to_cpu(sc->width); |
1206 |
surface.type = le32_to_cpu(sc->type); |
1207 |
surface.flags = le32_to_cpu(sc->flags); |
1208 |
trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem, |
1209 |
sc->format, sc->position); |
1210 |
trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type, |
1211 |
sc->flags); |
1212 |
|
1213 |
surface.mouse_mode = true;
|
1214 |
surface.group_id = MEMSLOT_GROUP_GUEST; |
1215 |
if (loadvm) {
|
1216 |
surface.flags |= QXL_SURF_FLAG_KEEP_DATA; |
1217 |
} |
1218 |
|
1219 |
qxl->mode = QXL_MODE_NATIVE; |
1220 |
qxl->cmdflags = 0;
|
1221 |
qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
|
1222 |
|
1223 |
if (async == QXL_SYNC) {
|
1224 |
qxl_create_guest_primary_complete(qxl); |
1225 |
} |
1226 |
} |
1227 |
|
1228 |
/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
|
1229 |
* done (in QXL_SYNC case), 0 otherwise. */
|
1230 |
static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) |
1231 |
{ |
1232 |
if (d->mode == QXL_MODE_UNDEFINED) {
|
1233 |
return 0; |
1234 |
} |
1235 |
trace_qxl_destroy_primary(d->id); |
1236 |
d->mode = QXL_MODE_UNDEFINED; |
1237 |
qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
|
1238 |
qxl_spice_reset_cursor(d); |
1239 |
return 1; |
1240 |
} |
1241 |
|
1242 |
static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm) |
1243 |
{ |
1244 |
pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; |
1245 |
pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; |
1246 |
QXLMode *mode = d->modes->modes + modenr; |
1247 |
uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; |
1248 |
QXLMemSlot slot = { |
1249 |
.mem_start = start, |
1250 |
.mem_end = end |
1251 |
}; |
1252 |
QXLSurfaceCreate surface = { |
1253 |
.width = mode->x_res, |
1254 |
.height = mode->y_res, |
1255 |
.stride = -mode->x_res * 4,
|
1256 |
.format = SPICE_SURFACE_FMT_32_xRGB, |
1257 |
.flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
|
1258 |
.mouse_mode = true,
|
1259 |
.mem = devmem + d->shadow_rom.draw_area_offset, |
1260 |
}; |
1261 |
|
1262 |
trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits, |
1263 |
devmem); |
1264 |
if (!loadvm) {
|
1265 |
qxl_hard_reset(d, 0);
|
1266 |
} |
1267 |
|
1268 |
d->guest_slots[0].slot = slot;
|
1269 |
assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0); |
1270 |
|
1271 |
d->guest_primary.surface = surface; |
1272 |
qxl_create_guest_primary(d, 0, QXL_SYNC);
|
1273 |
|
1274 |
d->mode = QXL_MODE_COMPAT; |
1275 |
d->cmdflags = QXL_COMMAND_FLAG_COMPAT; |
1276 |
#ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */ |
1277 |
if (mode->bits == 16) { |
1278 |
d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; |
1279 |
} |
1280 |
#endif
|
1281 |
d->shadow_rom.mode = cpu_to_le32(modenr); |
1282 |
d->rom->mode = cpu_to_le32(modenr); |
1283 |
qxl_rom_set_dirty(d); |
1284 |
} |
1285 |
|
1286 |
static void ioport_write(void *opaque, target_phys_addr_t addr, |
1287 |
uint64_t val, unsigned size)
|
1288 |
{ |
1289 |
PCIQXLDevice *d = opaque; |
1290 |
uint32_t io_port = addr; |
1291 |
qxl_async_io async = QXL_SYNC; |
1292 |
uint32_t orig_io_port = io_port; |
1293 |
|
1294 |
switch (io_port) {
|
1295 |
case QXL_IO_RESET:
|
1296 |
case QXL_IO_SET_MODE:
|
1297 |
case QXL_IO_MEMSLOT_ADD:
|
1298 |
case QXL_IO_MEMSLOT_DEL:
|
1299 |
case QXL_IO_CREATE_PRIMARY:
|
1300 |
case QXL_IO_UPDATE_IRQ:
|
1301 |
case QXL_IO_LOG:
|
1302 |
case QXL_IO_MEMSLOT_ADD_ASYNC:
|
1303 |
case QXL_IO_CREATE_PRIMARY_ASYNC:
|
1304 |
break;
|
1305 |
default:
|
1306 |
if (d->mode != QXL_MODE_VGA) {
|
1307 |
break;
|
1308 |
} |
1309 |
trace_qxl_io_unexpected_vga_mode(d->id, |
1310 |
io_port, io_port_to_string(io_port)); |
1311 |
/* be nice to buggy guest drivers */
|
1312 |
if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
|
1313 |
io_port <= QXL_IO_DESTROY_ALL_SURFACES_ASYNC) { |
1314 |
qxl_send_events(d, QXL_INTERRUPT_IO_CMD); |
1315 |
} |
1316 |
return;
|
1317 |
} |
1318 |
|
1319 |
/* we change the io_port to avoid ifdeffery in the main switch */
|
1320 |
orig_io_port = io_port; |
1321 |
switch (io_port) {
|
1322 |
case QXL_IO_UPDATE_AREA_ASYNC:
|
1323 |
io_port = QXL_IO_UPDATE_AREA; |
1324 |
goto async_common;
|
1325 |
case QXL_IO_MEMSLOT_ADD_ASYNC:
|
1326 |
io_port = QXL_IO_MEMSLOT_ADD; |
1327 |
goto async_common;
|
1328 |
case QXL_IO_CREATE_PRIMARY_ASYNC:
|
1329 |
io_port = QXL_IO_CREATE_PRIMARY; |
1330 |
goto async_common;
|
1331 |
case QXL_IO_DESTROY_PRIMARY_ASYNC:
|
1332 |
io_port = QXL_IO_DESTROY_PRIMARY; |
1333 |
goto async_common;
|
1334 |
case QXL_IO_DESTROY_SURFACE_ASYNC:
|
1335 |
io_port = QXL_IO_DESTROY_SURFACE_WAIT; |
1336 |
goto async_common;
|
1337 |
case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
|
1338 |
io_port = QXL_IO_DESTROY_ALL_SURFACES; |
1339 |
goto async_common;
|
1340 |
case QXL_IO_FLUSH_SURFACES_ASYNC:
|
1341 |
async_common:
|
1342 |
async = QXL_ASYNC; |
1343 |
qemu_mutex_lock(&d->async_lock); |
1344 |
if (d->current_async != QXL_UNDEFINED_IO) {
|
1345 |
qxl_guest_bug(d, "%d async started before last (%d) complete",
|
1346 |
io_port, d->current_async); |
1347 |
qemu_mutex_unlock(&d->async_lock); |
1348 |
return;
|
1349 |
} |
1350 |
d->current_async = orig_io_port; |
1351 |
qemu_mutex_unlock(&d->async_lock); |
1352 |
break;
|
1353 |
default:
|
1354 |
break;
|
1355 |
} |
1356 |
trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), addr, val, size, |
1357 |
async); |
1358 |
|
1359 |
switch (io_port) {
|
1360 |
case QXL_IO_UPDATE_AREA:
|
1361 |
{ |
1362 |
QXLCookie *cookie = NULL;
|
1363 |
QXLRect update = d->ram->update_area; |
1364 |
|
1365 |
if (async == QXL_ASYNC) {
|
1366 |
cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
1367 |
QXL_IO_UPDATE_AREA_ASYNC); |
1368 |
cookie->u.area = update; |
1369 |
} |
1370 |
qxl_spice_update_area(d, d->ram->update_surface, |
1371 |
cookie ? &cookie->u.area : &update, |
1372 |
NULL, 0, 0, async, cookie); |
1373 |
break;
|
1374 |
} |
1375 |
case QXL_IO_NOTIFY_CMD:
|
1376 |
qemu_spice_wakeup(&d->ssd); |
1377 |
break;
|
1378 |
case QXL_IO_NOTIFY_CURSOR:
|
1379 |
qemu_spice_wakeup(&d->ssd); |
1380 |
break;
|
1381 |
case QXL_IO_UPDATE_IRQ:
|
1382 |
qxl_update_irq(d); |
1383 |
break;
|
1384 |
case QXL_IO_NOTIFY_OOM:
|
1385 |
if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
|
1386 |
break;
|
1387 |
} |
1388 |
d->oom_running = 1;
|
1389 |
qxl_spice_oom(d); |
1390 |
d->oom_running = 0;
|
1391 |
break;
|
1392 |
case QXL_IO_SET_MODE:
|
1393 |
qxl_set_mode(d, val, 0);
|
1394 |
break;
|
1395 |
case QXL_IO_LOG:
|
1396 |
if (d->guestdebug) {
|
1397 |
fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id, |
1398 |
qemu_get_clock_ns(vm_clock), d->ram->log_buf); |
1399 |
} |
1400 |
break;
|
1401 |
case QXL_IO_RESET:
|
1402 |
qxl_hard_reset(d, 0);
|
1403 |
break;
|
1404 |
case QXL_IO_MEMSLOT_ADD:
|
1405 |
if (val >= NUM_MEMSLOTS) {
|
1406 |
qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
|
1407 |
break;
|
1408 |
} |
1409 |
if (d->guest_slots[val].active) {
|
1410 |
qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: memory slot already active");
|
1411 |
break;
|
1412 |
} |
1413 |
d->guest_slots[val].slot = d->ram->mem_slot; |
1414 |
qxl_add_memslot(d, val, 0, async);
|
1415 |
break;
|
1416 |
case QXL_IO_MEMSLOT_DEL:
|
1417 |
if (val >= NUM_MEMSLOTS) {
|
1418 |
qxl_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
|
1419 |
break;
|
1420 |
} |
1421 |
qxl_del_memslot(d, val); |
1422 |
break;
|
1423 |
case QXL_IO_CREATE_PRIMARY:
|
1424 |
if (val != 0) { |
1425 |
qxl_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
|
1426 |
async); |
1427 |
goto cancel_async;
|
1428 |
} |
1429 |
d->guest_primary.surface = d->ram->create_surface; |
1430 |
qxl_create_guest_primary(d, 0, async);
|
1431 |
break;
|
1432 |
case QXL_IO_DESTROY_PRIMARY:
|
1433 |
if (val != 0) { |
1434 |
qxl_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
|
1435 |
async); |
1436 |
goto cancel_async;
|
1437 |
} |
1438 |
if (!qxl_destroy_primary(d, async)) {
|
1439 |
trace_qxl_io_destroy_primary_ignored(d->id, |
1440 |
qxl_mode_to_string(d->mode)); |
1441 |
goto cancel_async;
|
1442 |
} |
1443 |
break;
|
1444 |
case QXL_IO_DESTROY_SURFACE_WAIT:
|
1445 |
if (val >= NUM_SURFACES) {
|
1446 |
qxl_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
|
1447 |
"%" PRIu64 " >= NUM_SURFACES", async, val); |
1448 |
goto cancel_async;
|
1449 |
} |
1450 |
qxl_spice_destroy_surface_wait(d, val, async); |
1451 |
break;
|
1452 |
case QXL_IO_FLUSH_RELEASE: {
|
1453 |
QXLReleaseRing *ring = &d->ram->release_ring; |
1454 |
if (ring->prod - ring->cons + 1 == ring->num_items) { |
1455 |
fprintf(stderr, |
1456 |
"ERROR: no flush, full release ring [p%d,%dc]\n",
|
1457 |
ring->prod, ring->cons); |
1458 |
} |
1459 |
qxl_push_free_res(d, 1 /* flush */); |
1460 |
break;
|
1461 |
} |
1462 |
case QXL_IO_FLUSH_SURFACES_ASYNC:
|
1463 |
qxl_spice_flush_surfaces_async(d); |
1464 |
break;
|
1465 |
case QXL_IO_DESTROY_ALL_SURFACES:
|
1466 |
d->mode = QXL_MODE_UNDEFINED; |
1467 |
qxl_spice_destroy_surfaces(d, async); |
1468 |
break;
|
1469 |
default:
|
1470 |
qxl_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
|
1471 |
} |
1472 |
return;
|
1473 |
cancel_async:
|
1474 |
if (async) {
|
1475 |
qxl_send_events(d, QXL_INTERRUPT_IO_CMD); |
1476 |
qemu_mutex_lock(&d->async_lock); |
1477 |
d->current_async = QXL_UNDEFINED_IO; |
1478 |
qemu_mutex_unlock(&d->async_lock); |
1479 |
} |
1480 |
} |
1481 |
|
1482 |
static uint64_t ioport_read(void *opaque, target_phys_addr_t addr, |
1483 |
unsigned size)
|
1484 |
{ |
1485 |
PCIQXLDevice *d = opaque; |
1486 |
|
1487 |
trace_qxl_io_read_unexpected(d->id); |
1488 |
return 0xff; |
1489 |
} |
1490 |
|
1491 |
static const MemoryRegionOps qxl_io_ops = { |
1492 |
.read = ioport_read, |
1493 |
.write = ioport_write, |
1494 |
.valid = { |
1495 |
.min_access_size = 1,
|
1496 |
.max_access_size = 1,
|
1497 |
}, |
1498 |
}; |
1499 |
|
1500 |
static void pipe_read(void *opaque) |
1501 |
{ |
1502 |
PCIQXLDevice *d = opaque; |
1503 |
char dummy;
|
1504 |
int len;
|
1505 |
|
1506 |
do {
|
1507 |
len = read(d->pipe[0], &dummy, sizeof(dummy)); |
1508 |
} while (len == sizeof(dummy)); |
1509 |
qxl_update_irq(d); |
1510 |
} |
1511 |
|
1512 |
static void qxl_send_events(PCIQXLDevice *d, uint32_t events) |
1513 |
{ |
1514 |
uint32_t old_pending; |
1515 |
uint32_t le_events = cpu_to_le32(events); |
1516 |
|
1517 |
assert(d->ssd.running); |
1518 |
old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events); |
1519 |
if ((old_pending & le_events) == le_events) {
|
1520 |
return;
|
1521 |
} |
1522 |
if (qemu_thread_is_self(&d->main)) {
|
1523 |
qxl_update_irq(d); |
1524 |
} else {
|
1525 |
if (write(d->pipe[1], d, 1) != 1) { |
1526 |
dprint(d, 1, "%s: write to pipe failed\n", __func__); |
1527 |
} |
1528 |
} |
1529 |
} |
1530 |
|
1531 |
static void init_pipe_signaling(PCIQXLDevice *d) |
1532 |
{ |
1533 |
if (pipe(d->pipe) < 0) { |
1534 |
fprintf(stderr, "%s:%s: qxl pipe creation failed\n",
|
1535 |
__FILE__, __func__); |
1536 |
exit(1);
|
1537 |
} |
1538 |
fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
|
1539 |
fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
|
1540 |
fcntl(d->pipe[0], F_SETOWN, getpid());
|
1541 |
|
1542 |
qemu_thread_get_self(&d->main); |
1543 |
qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d); |
1544 |
} |
1545 |
|
1546 |
/* graphics console */
|
1547 |
|
1548 |
static void qxl_hw_update(void *opaque) |
1549 |
{ |
1550 |
PCIQXLDevice *qxl = opaque; |
1551 |
VGACommonState *vga = &qxl->vga; |
1552 |
|
1553 |
switch (qxl->mode) {
|
1554 |
case QXL_MODE_VGA:
|
1555 |
vga->update(vga); |
1556 |
break;
|
1557 |
case QXL_MODE_COMPAT:
|
1558 |
case QXL_MODE_NATIVE:
|
1559 |
qxl_render_update(qxl); |
1560 |
break;
|
1561 |
default:
|
1562 |
break;
|
1563 |
} |
1564 |
} |
1565 |
|
1566 |
static void qxl_hw_invalidate(void *opaque) |
1567 |
{ |
1568 |
PCIQXLDevice *qxl = opaque; |
1569 |
VGACommonState *vga = &qxl->vga; |
1570 |
|
1571 |
vga->invalidate(vga); |
1572 |
} |
1573 |
|
1574 |
static void qxl_hw_screen_dump(void *opaque, const char *filename, bool cswitch) |
1575 |
{ |
1576 |
PCIQXLDevice *qxl = opaque; |
1577 |
VGACommonState *vga = &qxl->vga; |
1578 |
|
1579 |
switch (qxl->mode) {
|
1580 |
case QXL_MODE_COMPAT:
|
1581 |
case QXL_MODE_NATIVE:
|
1582 |
qxl_render_update(qxl); |
1583 |
ppm_save(filename, qxl->ssd.ds->surface); |
1584 |
break;
|
1585 |
case QXL_MODE_VGA:
|
1586 |
vga->screen_dump(vga, filename, cswitch); |
1587 |
break;
|
1588 |
default:
|
1589 |
break;
|
1590 |
} |
1591 |
} |
1592 |
|
1593 |
static void qxl_hw_text_update(void *opaque, console_ch_t *chardata) |
1594 |
{ |
1595 |
PCIQXLDevice *qxl = opaque; |
1596 |
VGACommonState *vga = &qxl->vga; |
1597 |
|
1598 |
if (qxl->mode == QXL_MODE_VGA) {
|
1599 |
vga->text_update(vga, chardata); |
1600 |
return;
|
1601 |
} |
1602 |
} |
1603 |
|
1604 |
static void qxl_dirty_surfaces(PCIQXLDevice *qxl) |
1605 |
{ |
1606 |
intptr_t vram_start; |
1607 |
int i;
|
1608 |
|
1609 |
if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
|
1610 |
return;
|
1611 |
} |
1612 |
|
1613 |
/* dirty the primary surface */
|
1614 |
qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset, |
1615 |
qxl->shadow_rom.surface0_area_size); |
1616 |
|
1617 |
vram_start = (intptr_t)memory_region_get_ram_ptr(&qxl->vram_bar); |
1618 |
|
1619 |
/* dirty the off-screen surfaces */
|
1620 |
for (i = 0; i < NUM_SURFACES; i++) { |
1621 |
QXLSurfaceCmd *cmd; |
1622 |
intptr_t surface_offset; |
1623 |
int surface_size;
|
1624 |
|
1625 |
if (qxl->guest_surfaces.cmds[i] == 0) { |
1626 |
continue;
|
1627 |
} |
1628 |
|
1629 |
cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i], |
1630 |
MEMSLOT_GROUP_GUEST); |
1631 |
assert(cmd); |
1632 |
assert(cmd->type == QXL_SURFACE_CMD_CREATE); |
1633 |
surface_offset = (intptr_t)qxl_phys2virt(qxl, |
1634 |
cmd->u.surface_create.data, |
1635 |
MEMSLOT_GROUP_GUEST); |
1636 |
assert(surface_offset); |
1637 |
surface_offset -= vram_start; |
1638 |
surface_size = cmd->u.surface_create.height * |
1639 |
abs(cmd->u.surface_create.stride); |
1640 |
trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
|
1641 |
qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size); |
1642 |
} |
1643 |
} |
1644 |
|
1645 |
static void qxl_vm_change_state_handler(void *opaque, int running, |
1646 |
RunState state) |
1647 |
{ |
1648 |
PCIQXLDevice *qxl = opaque; |
1649 |
qemu_spice_vm_change_state_handler(&qxl->ssd, running, state); |
1650 |
|
1651 |
if (running) {
|
1652 |
/*
|
1653 |
* if qxl_send_events was called from spice server context before
|
1654 |
* migration ended, qxl_update_irq for these events might not have been
|
1655 |
* called
|
1656 |
*/
|
1657 |
qxl_update_irq(qxl); |
1658 |
} else {
|
1659 |
/* make sure surfaces are saved before migration */
|
1660 |
qxl_dirty_surfaces(qxl); |
1661 |
} |
1662 |
} |
1663 |
|
1664 |
/* display change listener */
|
1665 |
|
1666 |
static void display_update(struct DisplayState *ds, int x, int y, int w, int h) |
1667 |
{ |
1668 |
if (qxl0->mode == QXL_MODE_VGA) {
|
1669 |
qemu_spice_display_update(&qxl0->ssd, x, y, w, h); |
1670 |
} |
1671 |
} |
1672 |
|
1673 |
static void display_resize(struct DisplayState *ds) |
1674 |
{ |
1675 |
if (qxl0->mode == QXL_MODE_VGA) {
|
1676 |
qemu_spice_display_resize(&qxl0->ssd); |
1677 |
} |
1678 |
} |
1679 |
|
1680 |
static void display_refresh(struct DisplayState *ds) |
1681 |
{ |
1682 |
if (qxl0->mode == QXL_MODE_VGA) {
|
1683 |
qemu_spice_display_refresh(&qxl0->ssd); |
1684 |
} else {
|
1685 |
qemu_mutex_lock(&qxl0->ssd.lock); |
1686 |
qemu_spice_cursor_refresh_unlocked(&qxl0->ssd); |
1687 |
qemu_mutex_unlock(&qxl0->ssd.lock); |
1688 |
} |
1689 |
} |
1690 |
|
1691 |
static DisplayChangeListener display_listener = {
|
1692 |
.dpy_update = display_update, |
1693 |
.dpy_resize = display_resize, |
1694 |
.dpy_refresh = display_refresh, |
1695 |
}; |
1696 |
|
1697 |
static void qxl_init_ramsize(PCIQXLDevice *qxl, uint32_t ram_min_mb) |
1698 |
{ |
1699 |
/* vga ram (bar 0) */
|
1700 |
if (qxl->ram_size_mb != -1) { |
1701 |
qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024; |
1702 |
} |
1703 |
if (qxl->vga.vram_size < ram_min_mb * 1024 * 1024) { |
1704 |
qxl->vga.vram_size = ram_min_mb * 1024 * 1024; |
1705 |
} |
1706 |
|
1707 |
/* vram32 (surfaces, 32bit, bar 1) */
|
1708 |
if (qxl->vram32_size_mb != -1) { |
1709 |
qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024; |
1710 |
} |
1711 |
if (qxl->vram32_size < 4096) { |
1712 |
qxl->vram32_size = 4096;
|
1713 |
} |
1714 |
|
1715 |
/* vram (surfaces, 64bit, bar 4+5) */
|
1716 |
if (qxl->vram_size_mb != -1) { |
1717 |
qxl->vram_size = qxl->vram_size_mb * 1024 * 1024; |
1718 |
} |
1719 |
if (qxl->vram_size < qxl->vram32_size) {
|
1720 |
qxl->vram_size = qxl->vram32_size; |
1721 |
} |
1722 |
|
1723 |
if (qxl->revision == 1) { |
1724 |
qxl->vram32_size = 4096;
|
1725 |
qxl->vram_size = 4096;
|
1726 |
} |
1727 |
qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1); |
1728 |
qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1); |
1729 |
qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1); |
1730 |
} |
1731 |
|
1732 |
static int qxl_init_common(PCIQXLDevice *qxl) |
1733 |
{ |
1734 |
uint8_t* config = qxl->pci.config; |
1735 |
uint32_t pci_device_rev; |
1736 |
uint32_t io_size; |
1737 |
|
1738 |
qxl->mode = QXL_MODE_UNDEFINED; |
1739 |
qxl->generation = 1;
|
1740 |
qxl->num_memslots = NUM_MEMSLOTS; |
1741 |
qxl->num_surfaces = NUM_SURFACES; |
1742 |
qemu_mutex_init(&qxl->track_lock); |
1743 |
qemu_mutex_init(&qxl->async_lock); |
1744 |
qxl->current_async = QXL_UNDEFINED_IO; |
1745 |
|
1746 |
switch (qxl->revision) {
|
1747 |
case 1: /* spice 0.4 -- qxl-1 */ |
1748 |
pci_device_rev = QXL_REVISION_STABLE_V04; |
1749 |
io_size = 8;
|
1750 |
break;
|
1751 |
case 2: /* spice 0.6 -- qxl-2 */ |
1752 |
pci_device_rev = QXL_REVISION_STABLE_V06; |
1753 |
io_size = 16;
|
1754 |
break;
|
1755 |
case 3: /* qxl-3 */ |
1756 |
default:
|
1757 |
pci_device_rev = QXL_DEFAULT_REVISION; |
1758 |
io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1); |
1759 |
break;
|
1760 |
} |
1761 |
|
1762 |
pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); |
1763 |
pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
|
1764 |
|
1765 |
qxl->rom_size = qxl_rom_size(); |
1766 |
memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size);
|
1767 |
vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev); |
1768 |
init_qxl_rom(qxl); |
1769 |
init_qxl_ram(qxl); |
1770 |
|
1771 |
memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size);
|
1772 |
vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev); |
1773 |
memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar,
|
1774 |
0, qxl->vram32_size);
|
1775 |
|
1776 |
memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl, |
1777 |
"qxl-ioports", io_size);
|
1778 |
if (qxl->id == 0) { |
1779 |
vga_dirty_log_start(&qxl->vga); |
1780 |
} |
1781 |
|
1782 |
|
1783 |
pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, |
1784 |
PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar); |
1785 |
|
1786 |
pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, |
1787 |
PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); |
1788 |
|
1789 |
pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, |
1790 |
PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram); |
1791 |
|
1792 |
pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, |
1793 |
PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar); |
1794 |
|
1795 |
if (qxl->vram32_size < qxl->vram_size) {
|
1796 |
/*
|
1797 |
* Make the 64bit vram bar show up only in case it is
|
1798 |
* configured to be larger than the 32bit vram bar.
|
1799 |
*/
|
1800 |
pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX, |
1801 |
PCI_BASE_ADDRESS_SPACE_MEMORY | |
1802 |
PCI_BASE_ADDRESS_MEM_TYPE_64 | |
1803 |
PCI_BASE_ADDRESS_MEM_PREFETCH, |
1804 |
&qxl->vram_bar); |
1805 |
} |
1806 |
|
1807 |
/* print pci bar details */
|
1808 |
dprint(qxl, 1, "ram/%s: %d MB [region 0]\n", |
1809 |
qxl->id == 0 ? "pri" : "sec", |
1810 |
qxl->vga.vram_size / (1024*1024)); |
1811 |
dprint(qxl, 1, "vram/32: %d MB [region 1]\n", |
1812 |
qxl->vram32_size / (1024*1024)); |
1813 |
dprint(qxl, 1, "vram/64: %d MB %s\n", |
1814 |
qxl->vram_size / (1024*1024), |
1815 |
qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]"); |
1816 |
|
1817 |
qxl->ssd.qxl.base.sif = &qxl_interface.base; |
1818 |
qxl->ssd.qxl.id = qxl->id; |
1819 |
qemu_spice_add_interface(&qxl->ssd.qxl.base); |
1820 |
qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); |
1821 |
|
1822 |
init_pipe_signaling(qxl); |
1823 |
qxl_reset_state(qxl); |
1824 |
|
1825 |
qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); |
1826 |
|
1827 |
return 0; |
1828 |
} |
1829 |
|
1830 |
static int qxl_init_primary(PCIDevice *dev) |
1831 |
{ |
1832 |
PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); |
1833 |
VGACommonState *vga = &qxl->vga; |
1834 |
PortioList *qxl_vga_port_list = g_new(PortioList, 1);
|
1835 |
|
1836 |
qxl->id = 0;
|
1837 |
qxl_init_ramsize(qxl, 32);
|
1838 |
vga_common_init(vga, qxl->vga.vram_size); |
1839 |
vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false);
|
1840 |
portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga");
|
1841 |
portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
|
1842 |
|
1843 |
vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate, |
1844 |
qxl_hw_screen_dump, qxl_hw_text_update, qxl); |
1845 |
qemu_spice_display_init_common(&qxl->ssd, vga->ds); |
1846 |
|
1847 |
qxl0 = qxl; |
1848 |
register_displaychangelistener(vga->ds, &display_listener); |
1849 |
|
1850 |
return qxl_init_common(qxl);
|
1851 |
} |
1852 |
|
1853 |
static int qxl_init_secondary(PCIDevice *dev) |
1854 |
{ |
1855 |
static int device_id = 1; |
1856 |
PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); |
1857 |
|
1858 |
qxl->id = device_id++; |
1859 |
qxl_init_ramsize(qxl, 16);
|
1860 |
memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size);
|
1861 |
vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev); |
1862 |
qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); |
1863 |
|
1864 |
return qxl_init_common(qxl);
|
1865 |
} |
1866 |
|
1867 |
static void qxl_pre_save(void *opaque) |
1868 |
{ |
1869 |
PCIQXLDevice* d = opaque; |
1870 |
uint8_t *ram_start = d->vga.vram_ptr; |
1871 |
|
1872 |
trace_qxl_pre_save(d->id); |
1873 |
if (d->last_release == NULL) { |
1874 |
d->last_release_offset = 0;
|
1875 |
} else {
|
1876 |
d->last_release_offset = (uint8_t *)d->last_release - ram_start; |
1877 |
} |
1878 |
assert(d->last_release_offset < d->vga.vram_size); |
1879 |
} |
1880 |
|
1881 |
static int qxl_pre_load(void *opaque) |
1882 |
{ |
1883 |
PCIQXLDevice* d = opaque; |
1884 |
|
1885 |
trace_qxl_pre_load(d->id); |
1886 |
qxl_hard_reset(d, 1);
|
1887 |
qxl_exit_vga_mode(d); |
1888 |
return 0; |
1889 |
} |
1890 |
|
1891 |
static void qxl_create_memslots(PCIQXLDevice *d) |
1892 |
{ |
1893 |
int i;
|
1894 |
|
1895 |
for (i = 0; i < NUM_MEMSLOTS; i++) { |
1896 |
if (!d->guest_slots[i].active) {
|
1897 |
continue;
|
1898 |
} |
1899 |
qxl_add_memslot(d, i, 0, QXL_SYNC);
|
1900 |
} |
1901 |
} |
1902 |
|
1903 |
static int qxl_post_load(void *opaque, int version) |
1904 |
{ |
1905 |
PCIQXLDevice* d = opaque; |
1906 |
uint8_t *ram_start = d->vga.vram_ptr; |
1907 |
QXLCommandExt *cmds; |
1908 |
int in, out, newmode;
|
1909 |
|
1910 |
assert(d->last_release_offset < d->vga.vram_size); |
1911 |
if (d->last_release_offset == 0) { |
1912 |
d->last_release = NULL;
|
1913 |
} else {
|
1914 |
d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); |
1915 |
} |
1916 |
|
1917 |
d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); |
1918 |
|
1919 |
trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode)); |
1920 |
newmode = d->mode; |
1921 |
d->mode = QXL_MODE_UNDEFINED; |
1922 |
|
1923 |
switch (newmode) {
|
1924 |
case QXL_MODE_UNDEFINED:
|
1925 |
break;
|
1926 |
case QXL_MODE_VGA:
|
1927 |
qxl_create_memslots(d); |
1928 |
qxl_enter_vga_mode(d); |
1929 |
break;
|
1930 |
case QXL_MODE_NATIVE:
|
1931 |
qxl_create_memslots(d); |
1932 |
qxl_create_guest_primary(d, 1, QXL_SYNC);
|
1933 |
|
1934 |
/* replay surface-create and cursor-set commands */
|
1935 |
cmds = g_malloc0(sizeof(QXLCommandExt) * (NUM_SURFACES + 1)); |
1936 |
for (in = 0, out = 0; in < NUM_SURFACES; in++) { |
1937 |
if (d->guest_surfaces.cmds[in] == 0) { |
1938 |
continue;
|
1939 |
} |
1940 |
cmds[out].cmd.data = d->guest_surfaces.cmds[in]; |
1941 |
cmds[out].cmd.type = QXL_CMD_SURFACE; |
1942 |
cmds[out].group_id = MEMSLOT_GROUP_GUEST; |
1943 |
out++; |
1944 |
} |
1945 |
if (d->guest_cursor) {
|
1946 |
cmds[out].cmd.data = d->guest_cursor; |
1947 |
cmds[out].cmd.type = QXL_CMD_CURSOR; |
1948 |
cmds[out].group_id = MEMSLOT_GROUP_GUEST; |
1949 |
out++; |
1950 |
} |
1951 |
qxl_spice_loadvm_commands(d, cmds, out); |
1952 |
g_free(cmds); |
1953 |
|
1954 |
break;
|
1955 |
case QXL_MODE_COMPAT:
|
1956 |
/* note: no need to call qxl_create_memslots, qxl_set_mode
|
1957 |
* creates the mem slot. */
|
1958 |
qxl_set_mode(d, d->shadow_rom.mode, 1);
|
1959 |
break;
|
1960 |
} |
1961 |
return 0; |
1962 |
} |
1963 |
|
1964 |
#define QXL_SAVE_VERSION 21 |
1965 |
|
1966 |
static VMStateDescription qxl_memslot = {
|
1967 |
.name = "qxl-memslot",
|
1968 |
.version_id = QXL_SAVE_VERSION, |
1969 |
.minimum_version_id = QXL_SAVE_VERSION, |
1970 |
.fields = (VMStateField[]) { |
1971 |
VMSTATE_UINT64(slot.mem_start, struct guest_slots),
|
1972 |
VMSTATE_UINT64(slot.mem_end, struct guest_slots),
|
1973 |
VMSTATE_UINT32(active, struct guest_slots),
|
1974 |
VMSTATE_END_OF_LIST() |
1975 |
} |
1976 |
}; |
1977 |
|
1978 |
static VMStateDescription qxl_surface = {
|
1979 |
.name = "qxl-surface",
|
1980 |
.version_id = QXL_SAVE_VERSION, |
1981 |
.minimum_version_id = QXL_SAVE_VERSION, |
1982 |
.fields = (VMStateField[]) { |
1983 |
VMSTATE_UINT32(width, QXLSurfaceCreate), |
1984 |
VMSTATE_UINT32(height, QXLSurfaceCreate), |
1985 |
VMSTATE_INT32(stride, QXLSurfaceCreate), |
1986 |
VMSTATE_UINT32(format, QXLSurfaceCreate), |
1987 |
VMSTATE_UINT32(position, QXLSurfaceCreate), |
1988 |
VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), |
1989 |
VMSTATE_UINT32(flags, QXLSurfaceCreate), |
1990 |
VMSTATE_UINT32(type, QXLSurfaceCreate), |
1991 |
VMSTATE_UINT64(mem, QXLSurfaceCreate), |
1992 |
VMSTATE_END_OF_LIST() |
1993 |
} |
1994 |
}; |
1995 |
|
1996 |
static VMStateDescription qxl_vmstate = {
|
1997 |
.name = "qxl",
|
1998 |
.version_id = QXL_SAVE_VERSION, |
1999 |
.minimum_version_id = QXL_SAVE_VERSION, |
2000 |
.pre_save = qxl_pre_save, |
2001 |
.pre_load = qxl_pre_load, |
2002 |
.post_load = qxl_post_load, |
2003 |
.fields = (VMStateField []) { |
2004 |
VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), |
2005 |
VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
|
2006 |
VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), |
2007 |
VMSTATE_UINT32(num_free_res, PCIQXLDevice), |
2008 |
VMSTATE_UINT32(last_release_offset, PCIQXLDevice), |
2009 |
VMSTATE_UINT32(mode, PCIQXLDevice), |
2010 |
VMSTATE_UINT32(ssd.unique, PCIQXLDevice), |
2011 |
VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice), |
2012 |
VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
|
2013 |
qxl_memslot, struct guest_slots),
|
2014 |
VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
|
2015 |
qxl_surface, QXLSurfaceCreate), |
2016 |
VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice), |
2017 |
VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
|
2018 |
vmstate_info_uint64, uint64_t), |
2019 |
VMSTATE_UINT64(guest_cursor, PCIQXLDevice), |
2020 |
VMSTATE_END_OF_LIST() |
2021 |
}, |
2022 |
}; |
2023 |
|
2024 |
static Property qxl_properties[] = {
|
2025 |
DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
|
2026 |
64 * 1024 * 1024), |
2027 |
DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
|
2028 |
64 * 1024 * 1024), |
2029 |
DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
|
2030 |
QXL_DEFAULT_REVISION), |
2031 |
DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), |
2032 |
DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), |
2033 |
DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), |
2034 |
DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1), |
2035 |
DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1), |
2036 |
DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1), |
2037 |
DEFINE_PROP_END_OF_LIST(), |
2038 |
}; |
2039 |
|
2040 |
static void qxl_primary_class_init(ObjectClass *klass, void *data) |
2041 |
{ |
2042 |
DeviceClass *dc = DEVICE_CLASS(klass); |
2043 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2044 |
|
2045 |
k->no_hotplug = 1;
|
2046 |
k->init = qxl_init_primary; |
2047 |
k->romfile = "vgabios-qxl.bin";
|
2048 |
k->vendor_id = REDHAT_PCI_VENDOR_ID; |
2049 |
k->device_id = QXL_DEVICE_ID_STABLE; |
2050 |
k->class_id = PCI_CLASS_DISPLAY_VGA; |
2051 |
dc->desc = "Spice QXL GPU (primary, vga compatible)";
|
2052 |
dc->reset = qxl_reset_handler; |
2053 |
dc->vmsd = &qxl_vmstate; |
2054 |
dc->props = qxl_properties; |
2055 |
} |
2056 |
|
2057 |
static TypeInfo qxl_primary_info = {
|
2058 |
.name = "qxl-vga",
|
2059 |
.parent = TYPE_PCI_DEVICE, |
2060 |
.instance_size = sizeof(PCIQXLDevice),
|
2061 |
.class_init = qxl_primary_class_init, |
2062 |
}; |
2063 |
|
2064 |
static void qxl_secondary_class_init(ObjectClass *klass, void *data) |
2065 |
{ |
2066 |
DeviceClass *dc = DEVICE_CLASS(klass); |
2067 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2068 |
|
2069 |
k->init = qxl_init_secondary; |
2070 |
k->vendor_id = REDHAT_PCI_VENDOR_ID; |
2071 |
k->device_id = QXL_DEVICE_ID_STABLE; |
2072 |
k->class_id = PCI_CLASS_DISPLAY_OTHER; |
2073 |
dc->desc = "Spice QXL GPU (secondary)";
|
2074 |
dc->reset = qxl_reset_handler; |
2075 |
dc->vmsd = &qxl_vmstate; |
2076 |
dc->props = qxl_properties; |
2077 |
} |
2078 |
|
2079 |
static TypeInfo qxl_secondary_info = {
|
2080 |
.name = "qxl",
|
2081 |
.parent = TYPE_PCI_DEVICE, |
2082 |
.instance_size = sizeof(PCIQXLDevice),
|
2083 |
.class_init = qxl_secondary_class_init, |
2084 |
}; |
2085 |
|
2086 |
static void qxl_register_types(void) |
2087 |
{ |
2088 |
type_register_static(&qxl_primary_info); |
2089 |
type_register_static(&qxl_secondary_info); |
2090 |
} |
2091 |
|
2092 |
type_init(qxl_register_types) |