root / hw / ppce500_mpc8544ds.c @ 4b78a802
History | View | Annotate | Download (8.9 kB)
1 | 1db09b84 | aurel32 | /*
|
---|---|---|---|
2 | 1db09b84 | aurel32 | * Qemu PowerPC MPC8544DS board emualtion
|
3 | 1db09b84 | aurel32 | *
|
4 | 1db09b84 | aurel32 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
|
5 | 1db09b84 | aurel32 | *
|
6 | 1db09b84 | aurel32 | * Author: Yu Liu, <yu.liu@freescale.com>
|
7 | 1db09b84 | aurel32 | *
|
8 | 1db09b84 | aurel32 | * This file is derived from hw/ppc440_bamboo.c,
|
9 | 1db09b84 | aurel32 | * the copyright for that material belongs to the original owners.
|
10 | 1db09b84 | aurel32 | *
|
11 | 1db09b84 | aurel32 | * This is free software; you can redistribute it and/or modify
|
12 | 1db09b84 | aurel32 | * it under the terms of the GNU General Public License as published by
|
13 | 1db09b84 | aurel32 | * the Free Software Foundation; either version 2 of the License, or
|
14 | 1db09b84 | aurel32 | * (at your option) any later version.
|
15 | 1db09b84 | aurel32 | */
|
16 | 1db09b84 | aurel32 | |
17 | 1db09b84 | aurel32 | #include <dirent.h> |
18 | 1db09b84 | aurel32 | |
19 | 1db09b84 | aurel32 | #include "config.h" |
20 | 1db09b84 | aurel32 | #include "qemu-common.h" |
21 | 1db09b84 | aurel32 | #include "net.h" |
22 | 1db09b84 | aurel32 | #include "hw.h" |
23 | 1db09b84 | aurel32 | #include "pc.h" |
24 | 1db09b84 | aurel32 | #include "pci.h" |
25 | 1db09b84 | aurel32 | #include "boards.h" |
26 | 1db09b84 | aurel32 | #include "sysemu.h" |
27 | 1db09b84 | aurel32 | #include "kvm.h" |
28 | 1db09b84 | aurel32 | #include "kvm_ppc.h" |
29 | 1db09b84 | aurel32 | #include "device_tree.h" |
30 | 1db09b84 | aurel32 | #include "openpic.h" |
31 | 1db09b84 | aurel32 | #include "ppce500.h" |
32 | ca20cf32 | Blue Swirl | #include "loader.h" |
33 | ca20cf32 | Blue Swirl | #include "elf.h" |
34 | 1db09b84 | aurel32 | |
35 | 1db09b84 | aurel32 | #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" |
36 | 1db09b84 | aurel32 | #define UIMAGE_LOAD_BASE 0 |
37 | 75bb6589 | Liu Yu | #define DTC_LOAD_PAD 0x500000 |
38 | 75bb6589 | Liu Yu | #define DTC_PAD_MASK 0xFFFFF |
39 | 75bb6589 | Liu Yu | #define INITRD_LOAD_PAD 0x2000000 |
40 | 75bb6589 | Liu Yu | #define INITRD_PAD_MASK 0xFFFFFF |
41 | 1db09b84 | aurel32 | |
42 | 1db09b84 | aurel32 | #define RAM_SIZES_ALIGN (64UL << 20) |
43 | 1db09b84 | aurel32 | |
44 | 1db09b84 | aurel32 | #define MPC8544_CCSRBAR_BASE 0xE0000000 |
45 | 1db09b84 | aurel32 | #define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000) |
46 | 1db09b84 | aurel32 | #define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500) |
47 | 1db09b84 | aurel32 | #define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600) |
48 | 1db09b84 | aurel32 | #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000) |
49 | 1db09b84 | aurel32 | #define MPC8544_PCI_REGS_SIZE 0x1000 |
50 | 1db09b84 | aurel32 | #define MPC8544_PCI_IO 0xE1000000 |
51 | 1db09b84 | aurel32 | #define MPC8544_PCI_IOLEN 0x10000 |
52 | 1db09b84 | aurel32 | |
53 | 3f0855b1 | Juan Quintela | #ifdef CONFIG_FDT
|
54 | 1db09b84 | aurel32 | static int mpc8544_copy_soc_cell(void *fdt, const char *node, const char *prop) |
55 | 1db09b84 | aurel32 | { |
56 | 1db09b84 | aurel32 | uint32_t cell; |
57 | 1db09b84 | aurel32 | int ret;
|
58 | 1db09b84 | aurel32 | |
59 | 1db09b84 | aurel32 | ret = kvmppc_read_host_property(node, prop, &cell, sizeof(cell));
|
60 | 1db09b84 | aurel32 | if (ret < 0) { |
61 | 1db09b84 | aurel32 | fprintf(stderr, "couldn't read host %s/%s\n", node, prop);
|
62 | 1db09b84 | aurel32 | goto out;
|
63 | 1db09b84 | aurel32 | } |
64 | 1db09b84 | aurel32 | |
65 | 1db09b84 | aurel32 | ret = qemu_devtree_setprop_cell(fdt, "/cpus/PowerPC,8544@0",
|
66 | 1db09b84 | aurel32 | prop, cell); |
67 | 1db09b84 | aurel32 | if (ret < 0) { |
68 | 1db09b84 | aurel32 | fprintf(stderr, "couldn't set guest /cpus/PowerPC,8544@0/%s\n", prop);
|
69 | 1db09b84 | aurel32 | goto out;
|
70 | 1db09b84 | aurel32 | } |
71 | 1db09b84 | aurel32 | |
72 | 1db09b84 | aurel32 | out:
|
73 | 1db09b84 | aurel32 | return ret;
|
74 | 1db09b84 | aurel32 | } |
75 | 511d2b14 | blueswir1 | #endif
|
76 | 1db09b84 | aurel32 | |
77 | 04088adb | Liu Yu | static int mpc8544_load_device_tree(target_phys_addr_t addr, |
78 | 1db09b84 | aurel32 | uint32_t ramsize, |
79 | c227f099 | Anthony Liguori | target_phys_addr_t initrd_base, |
80 | c227f099 | Anthony Liguori | target_phys_addr_t initrd_size, |
81 | 1db09b84 | aurel32 | const char *kernel_cmdline) |
82 | 1db09b84 | aurel32 | { |
83 | dbf916d8 | Aurelien Jarno | int ret = -1; |
84 | 3f0855b1 | Juan Quintela | #ifdef CONFIG_FDT
|
85 | 1db09b84 | aurel32 | uint32_t mem_reg_property[] = {0, ramsize};
|
86 | 5cea8590 | Paul Brook | char *filename;
|
87 | 7ec632b4 | pbrook | int fdt_size;
|
88 | dbf916d8 | Aurelien Jarno | void *fdt;
|
89 | 1db09b84 | aurel32 | |
90 | 5cea8590 | Paul Brook | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); |
91 | 5cea8590 | Paul Brook | if (!filename) {
|
92 | 1db09b84 | aurel32 | goto out;
|
93 | 5cea8590 | Paul Brook | } |
94 | 5cea8590 | Paul Brook | fdt = load_device_tree(filename, &fdt_size); |
95 | 5cea8590 | Paul Brook | qemu_free(filename); |
96 | 5cea8590 | Paul Brook | if (fdt == NULL) { |
97 | 5cea8590 | Paul Brook | goto out;
|
98 | 5cea8590 | Paul Brook | } |
99 | 1db09b84 | aurel32 | |
100 | 1db09b84 | aurel32 | /* Manipulate device tree in memory. */
|
101 | 1db09b84 | aurel32 | ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, |
102 | 1db09b84 | aurel32 | sizeof(mem_reg_property));
|
103 | 1db09b84 | aurel32 | if (ret < 0) |
104 | 1db09b84 | aurel32 | fprintf(stderr, "couldn't set /memory/reg\n");
|
105 | 1db09b84 | aurel32 | |
106 | 1db09b84 | aurel32 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", |
107 | 1db09b84 | aurel32 | initrd_base); |
108 | 1db09b84 | aurel32 | if (ret < 0) |
109 | 1db09b84 | aurel32 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
|
110 | 1db09b84 | aurel32 | |
111 | 1db09b84 | aurel32 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
112 | 1db09b84 | aurel32 | (initrd_base + initrd_size)); |
113 | 1db09b84 | aurel32 | if (ret < 0) |
114 | 1db09b84 | aurel32 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
|
115 | 1db09b84 | aurel32 | |
116 | 1db09b84 | aurel32 | ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", |
117 | 1db09b84 | aurel32 | kernel_cmdline); |
118 | 1db09b84 | aurel32 | if (ret < 0) |
119 | 1db09b84 | aurel32 | fprintf(stderr, "couldn't set /chosen/bootargs\n");
|
120 | 1db09b84 | aurel32 | |
121 | 1db09b84 | aurel32 | if (kvm_enabled()) {
|
122 | 1db09b84 | aurel32 | struct dirent *dirp;
|
123 | 1db09b84 | aurel32 | DIR *dp; |
124 | 1db09b84 | aurel32 | char buf[128]; |
125 | 1db09b84 | aurel32 | |
126 | 1db09b84 | aurel32 | if ((dp = opendir("/proc/device-tree/cpus/")) == NULL) { |
127 | 1db09b84 | aurel32 | printf("Can't open directory /proc/device-tree/cpus/\n");
|
128 | 04088adb | Liu Yu | ret = -1;
|
129 | 1db09b84 | aurel32 | goto out;
|
130 | 1db09b84 | aurel32 | } |
131 | 1db09b84 | aurel32 | |
132 | 1db09b84 | aurel32 | buf[0] = '\0'; |
133 | 1db09b84 | aurel32 | while ((dirp = readdir(dp)) != NULL) { |
134 | 1db09b84 | aurel32 | if (strncmp(dirp->d_name, "PowerPC", 7) == 0) { |
135 | 1db09b84 | aurel32 | snprintf(buf, 128, "/cpus/%s", dirp->d_name); |
136 | 1db09b84 | aurel32 | break;
|
137 | 1db09b84 | aurel32 | } |
138 | 1db09b84 | aurel32 | } |
139 | 1db09b84 | aurel32 | closedir(dp); |
140 | 1db09b84 | aurel32 | if (buf[0] == '\0') { |
141 | 1db09b84 | aurel32 | printf("Unknow host!\n");
|
142 | 04088adb | Liu Yu | ret = -1;
|
143 | 1db09b84 | aurel32 | goto out;
|
144 | 1db09b84 | aurel32 | } |
145 | 1db09b84 | aurel32 | |
146 | 1db09b84 | aurel32 | mpc8544_copy_soc_cell(fdt, buf, "clock-frequency");
|
147 | 1db09b84 | aurel32 | mpc8544_copy_soc_cell(fdt, buf, "timebase-frequency");
|
148 | 1db09b84 | aurel32 | } |
149 | 1db09b84 | aurel32 | |
150 | 04088adb | Liu Yu | ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
151 | 04088adb | Liu Yu | qemu_free(fdt); |
152 | 7ec632b4 | pbrook | |
153 | 1db09b84 | aurel32 | out:
|
154 | 1db09b84 | aurel32 | #endif
|
155 | 1db09b84 | aurel32 | |
156 | 04088adb | Liu Yu | return ret;
|
157 | 1db09b84 | aurel32 | } |
158 | 1db09b84 | aurel32 | |
159 | c227f099 | Anthony Liguori | static void mpc8544ds_init(ram_addr_t ram_size, |
160 | 1db09b84 | aurel32 | const char *boot_device, |
161 | 1db09b84 | aurel32 | const char *kernel_filename, |
162 | 1db09b84 | aurel32 | const char *kernel_cmdline, |
163 | 1db09b84 | aurel32 | const char *initrd_filename, |
164 | 1db09b84 | aurel32 | const char *cpu_model) |
165 | 1db09b84 | aurel32 | { |
166 | 1db09b84 | aurel32 | PCIBus *pci_bus; |
167 | 1db09b84 | aurel32 | CPUState *env; |
168 | 1db09b84 | aurel32 | uint64_t elf_entry; |
169 | 1db09b84 | aurel32 | uint64_t elf_lowaddr; |
170 | c227f099 | Anthony Liguori | target_phys_addr_t entry=0;
|
171 | c227f099 | Anthony Liguori | target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE; |
172 | 1db09b84 | aurel32 | target_long kernel_size=0;
|
173 | 75bb6589 | Liu Yu | target_ulong dt_base = 0;
|
174 | 75bb6589 | Liu Yu | target_ulong initrd_base = 0;
|
175 | 1db09b84 | aurel32 | target_long initrd_size=0;
|
176 | 1db09b84 | aurel32 | int i=0; |
177 | 1db09b84 | aurel32 | unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; |
178 | 1db09b84 | aurel32 | qemu_irq *irqs, *mpic, *pci_irqs; |
179 | 1db09b84 | aurel32 | |
180 | 1db09b84 | aurel32 | /* Setup CPU */
|
181 | 1db09b84 | aurel32 | env = cpu_ppc_init("e500v2_v30");
|
182 | 1db09b84 | aurel32 | if (!env) {
|
183 | 1db09b84 | aurel32 | fprintf(stderr, "Unable to initialize CPU!\n");
|
184 | 1db09b84 | aurel32 | exit(1);
|
185 | 1db09b84 | aurel32 | } |
186 | 1db09b84 | aurel32 | |
187 | 1db09b84 | aurel32 | /* Fixup Memory size on a alignment boundary */
|
188 | 1db09b84 | aurel32 | ram_size &= ~(RAM_SIZES_ALIGN - 1);
|
189 | 1db09b84 | aurel32 | |
190 | 1db09b84 | aurel32 | /* Register Memory */
|
191 | 1724f049 | Alex Williamson | cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(NULL, |
192 | 1724f049 | Alex Williamson | "mpc8544ds.ram", ram_size));
|
193 | 1db09b84 | aurel32 | |
194 | 1db09b84 | aurel32 | /* MPIC */
|
195 | 1db09b84 | aurel32 | irqs = qemu_mallocz(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
|
196 | 1db09b84 | aurel32 | irqs[OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_INT]; |
197 | 1db09b84 | aurel32 | irqs[OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_CINT]; |
198 | 1db09b84 | aurel32 | mpic = mpic_init(MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL); |
199 | 1db09b84 | aurel32 | |
200 | 1db09b84 | aurel32 | /* Serial */
|
201 | 2d48377a | Blue Swirl | if (serial_hds[0]) { |
202 | 49a2942d | Blue Swirl | serial_mm_init(MPC8544_SERIAL0_REGS_BASE, |
203 | 49a2942d | Blue Swirl | 0, mpic[12+26], 399193, |
204 | 49a2942d | Blue Swirl | serial_hds[0], 1, 1); |
205 | 2d48377a | Blue Swirl | } |
206 | 1db09b84 | aurel32 | |
207 | 2d48377a | Blue Swirl | if (serial_hds[1]) { |
208 | 49a2942d | Blue Swirl | serial_mm_init(MPC8544_SERIAL1_REGS_BASE, |
209 | 49a2942d | Blue Swirl | 0, mpic[12+26], 399193, |
210 | 49a2942d | Blue Swirl | serial_hds[0], 1, 1); |
211 | 2d48377a | Blue Swirl | } |
212 | 1db09b84 | aurel32 | |
213 | 1db09b84 | aurel32 | /* PCI */
|
214 | 1db09b84 | aurel32 | pci_irqs = qemu_malloc(sizeof(qemu_irq) * 4); |
215 | 1db09b84 | aurel32 | pci_irqs[0] = mpic[pci_irq_nrs[0]]; |
216 | 1db09b84 | aurel32 | pci_irqs[1] = mpic[pci_irq_nrs[1]]; |
217 | 1db09b84 | aurel32 | pci_irqs[2] = mpic[pci_irq_nrs[2]]; |
218 | 1db09b84 | aurel32 | pci_irqs[3] = mpic[pci_irq_nrs[3]]; |
219 | 1db09b84 | aurel32 | pci_bus = ppce500_pci_init(pci_irqs, MPC8544_PCI_REGS_BASE); |
220 | 1db09b84 | aurel32 | if (!pci_bus)
|
221 | 1db09b84 | aurel32 | printf("couldn't create PCI controller!\n");
|
222 | 1db09b84 | aurel32 | |
223 | 968d683c | Alexander Graf | isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN); |
224 | 1db09b84 | aurel32 | |
225 | 1db09b84 | aurel32 | if (pci_bus) {
|
226 | 1db09b84 | aurel32 | /* Register network interfaces. */
|
227 | 1db09b84 | aurel32 | for (i = 0; i < nb_nics; i++) { |
228 | 07caea31 | Markus Armbruster | pci_nic_init_nofail(&nd_table[i], "virtio", NULL); |
229 | 1db09b84 | aurel32 | } |
230 | 1db09b84 | aurel32 | } |
231 | 1db09b84 | aurel32 | |
232 | 1db09b84 | aurel32 | /* Load kernel. */
|
233 | 1db09b84 | aurel32 | if (kernel_filename) {
|
234 | 1db09b84 | aurel32 | kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
|
235 | 1db09b84 | aurel32 | if (kernel_size < 0) { |
236 | 409dbce5 | Aurelien Jarno | kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry, |
237 | 409dbce5 | Aurelien Jarno | &elf_lowaddr, NULL, 1, ELF_MACHINE, 0); |
238 | 1db09b84 | aurel32 | entry = elf_entry; |
239 | 1db09b84 | aurel32 | loadaddr = elf_lowaddr; |
240 | 1db09b84 | aurel32 | } |
241 | 1db09b84 | aurel32 | /* XXX try again as binary */
|
242 | 1db09b84 | aurel32 | if (kernel_size < 0) { |
243 | 1db09b84 | aurel32 | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
244 | 1db09b84 | aurel32 | kernel_filename); |
245 | 1db09b84 | aurel32 | exit(1);
|
246 | 1db09b84 | aurel32 | } |
247 | 1db09b84 | aurel32 | } |
248 | 1db09b84 | aurel32 | |
249 | 1db09b84 | aurel32 | /* Load initrd. */
|
250 | 1db09b84 | aurel32 | if (initrd_filename) {
|
251 | 75bb6589 | Liu Yu | initrd_base = (kernel_size + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; |
252 | d7585251 | pbrook | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
253 | d7585251 | pbrook | ram_size - initrd_base); |
254 | 1db09b84 | aurel32 | |
255 | 1db09b84 | aurel32 | if (initrd_size < 0) { |
256 | 1db09b84 | aurel32 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
257 | 1db09b84 | aurel32 | initrd_filename); |
258 | 1db09b84 | aurel32 | exit(1);
|
259 | 1db09b84 | aurel32 | } |
260 | 1db09b84 | aurel32 | } |
261 | 1db09b84 | aurel32 | |
262 | 1db09b84 | aurel32 | /* If we're loading a kernel directly, we must load the device tree too. */
|
263 | 1db09b84 | aurel32 | if (kernel_filename) {
|
264 | 75bb6589 | Liu Yu | dt_base = (kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; |
265 | 04088adb | Liu Yu | if (mpc8544_load_device_tree(dt_base, ram_size,
|
266 | 04088adb | Liu Yu | initrd_base, initrd_size, kernel_cmdline) < 0) {
|
267 | 1db09b84 | aurel32 | fprintf(stderr, "couldn't load device tree\n");
|
268 | 1db09b84 | aurel32 | exit(1);
|
269 | 1db09b84 | aurel32 | } |
270 | 1db09b84 | aurel32 | |
271 | c4963817 | Liu Yu | cpu_synchronize_state(env); |
272 | c4963817 | Liu Yu | |
273 | 1db09b84 | aurel32 | /* Set initial guest state. */
|
274 | 1db09b84 | aurel32 | env->gpr[1] = (16<<20) - 8; |
275 | 1db09b84 | aurel32 | env->gpr[3] = dt_base;
|
276 | 1db09b84 | aurel32 | env->nip = entry; |
277 | 1db09b84 | aurel32 | /* XXX we currently depend on KVM to create some initial TLB entries. */
|
278 | 1db09b84 | aurel32 | } |
279 | 1db09b84 | aurel32 | |
280 | 1db09b84 | aurel32 | if (kvm_enabled())
|
281 | 1db09b84 | aurel32 | kvmppc_init(); |
282 | 1db09b84 | aurel32 | |
283 | 1db09b84 | aurel32 | return;
|
284 | 1db09b84 | aurel32 | } |
285 | 1db09b84 | aurel32 | |
286 | f80f9ec9 | Anthony Liguori | static QEMUMachine mpc8544ds_machine = {
|
287 | 1db09b84 | aurel32 | .name = "mpc8544ds",
|
288 | 1db09b84 | aurel32 | .desc = "mpc8544ds",
|
289 | 1db09b84 | aurel32 | .init = mpc8544ds_init, |
290 | 1db09b84 | aurel32 | }; |
291 | f80f9ec9 | Anthony Liguori | |
292 | f80f9ec9 | Anthony Liguori | static void mpc8544ds_machine_init(void) |
293 | f80f9ec9 | Anthony Liguori | { |
294 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&mpc8544ds_machine); |
295 | f80f9ec9 | Anthony Liguori | } |
296 | f80f9ec9 | Anthony Liguori | |
297 | f80f9ec9 | Anthony Liguori | machine_init(mpc8544ds_machine_init); |