Revision 4b78a802 hw/pc.c
| b/hw/pc.c | ||
|---|---|---|
| 411 | 411 |
qemu_register_reset(pc_cmos_init_late, &arg); |
| 412 | 412 |
} |
| 413 | 413 |
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| 414 |
/* port 92 stuff: could be split off */ |
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typedef struct Port92State {
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| 416 |
ISADevice dev; |
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| 417 |
uint8_t outport; |
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| 418 |
qemu_irq *a20_out; |
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| 419 |
} Port92State; |
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| 420 |
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static void port92_write(void *opaque, uint32_t addr, uint32_t val) |
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| 422 |
{
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Port92State *s = opaque; |
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DPRINTF("port92: write 0x%02x\n", val);
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s->outport = val; |
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qemu_set_irq(*s->a20_out, (val >> 1) & 1); |
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| 428 |
if (val & 1) {
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qemu_system_reset_request(); |
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} |
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} |
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static uint32_t port92_read(void *opaque, uint32_t addr) |
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{
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Port92State *s = opaque; |
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uint32_t ret; |
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ret = s->outport; |
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DPRINTF("port92: read 0x%02x\n", ret);
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return ret; |
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} |
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static void port92_init(ISADevice *dev, qemu_irq *a20_out) |
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{
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Port92State *s = DO_UPCAST(Port92State, dev, dev); |
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s->a20_out = a20_out; |
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} |
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static const VMStateDescription vmstate_port92_isa = {
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.name = "port92", |
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.version_id = 1, |
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.minimum_version_id = 1, |
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.minimum_version_id_old = 1, |
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.fields = (VMStateField []) {
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VMSTATE_UINT8(outport, Port92State), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static void port92_reset(DeviceState *d) |
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{
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Port92State *s = container_of(d, Port92State, dev.qdev); |
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s->outport &= ~1; |
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} |
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static int port92_initfn(ISADevice *dev) |
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{
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Port92State *s = DO_UPCAST(Port92State, dev, dev); |
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register_ioport_read(0x92, 1, 1, port92_read, s); |
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register_ioport_write(0x92, 1, 1, port92_write, s); |
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isa_init_ioport(dev, 0x92); |
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s->outport = 0; |
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return 0; |
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} |
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static ISADeviceInfo port92_info = {
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.qdev.name = "port92", |
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.qdev.size = sizeof(Port92State), |
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.qdev.vmsd = &vmstate_port92_isa, |
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.qdev.no_user = 1, |
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.qdev.reset = port92_reset, |
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.init = port92_initfn, |
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}; |
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static void port92_register(void) |
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{
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isa_qdev_register(&port92_info); |
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} |
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device_init(port92_register) |
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| 414 | 494 |
static void handle_a20_line_change(void *opaque, int irq, int level) |
| 415 | 495 |
{
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| 416 | 496 |
CPUState *cpu = opaque; |
| 417 | 497 |
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/* XXX: send to all CPUs ? */ |
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/* XXX: add logic to handle multiple A20 line sources */ |
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| 419 | 500 |
cpu_x86_set_a20(cpu, level); |
| 420 | 501 |
} |
| 421 | 502 |
|
| ... | ... | |
| 1027 | 1108 |
PITState *pit; |
| 1028 | 1109 |
qemu_irq rtc_irq = NULL; |
| 1029 | 1110 |
qemu_irq *a20_line; |
| 1030 |
ISADevice *i8042; |
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| 1111 |
ISADevice *i8042, *port92;
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qemu_irq *cpu_exit_irq; |
| 1032 | 1113 |
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| 1033 | 1114 |
register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
| ... | ... | |
| 1061 | 1142 |
} |
| 1062 | 1143 |
} |
| 1063 | 1144 |
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a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1);
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a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
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| 1065 | 1146 |
i8042 = isa_create_simple("i8042");
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i8042_setup_a20_line(i8042, a20_line);
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i8042_setup_a20_line(i8042, &a20_line[0]);
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| 1067 | 1148 |
vmmouse_init(i8042); |
| 1149 |
port92 = isa_create_simple("port92");
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port92_init(port92, &a20_line[1]); |
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| 1068 | 1151 |
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| 1069 | 1152 |
cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
| 1070 | 1153 |
DMA_init(0, cpu_exit_irq); |
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