root / hw / etraxfs_dma.c @ 4b816985
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1 | 1ba13a5d | edgar_igl | /*
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2 | 1ba13a5d | edgar_igl | * QEMU ETRAX DMA Controller.
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3 | 1ba13a5d | edgar_igl | *
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4 | 1ba13a5d | edgar_igl | * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
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5 | 1ba13a5d | edgar_igl | *
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6 | 1ba13a5d | edgar_igl | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 1ba13a5d | edgar_igl | * of this software and associated documentation files (the "Software"), to deal
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8 | 1ba13a5d | edgar_igl | * in the Software without restriction, including without limitation the rights
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9 | 1ba13a5d | edgar_igl | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 1ba13a5d | edgar_igl | * copies of the Software, and to permit persons to whom the Software is
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11 | 1ba13a5d | edgar_igl | * furnished to do so, subject to the following conditions:
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12 | 1ba13a5d | edgar_igl | *
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13 | 1ba13a5d | edgar_igl | * The above copyright notice and this permission notice shall be included in
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14 | 1ba13a5d | edgar_igl | * all copies or substantial portions of the Software.
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15 | 1ba13a5d | edgar_igl | *
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16 | 1ba13a5d | edgar_igl | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 1ba13a5d | edgar_igl | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 1ba13a5d | edgar_igl | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 1ba13a5d | edgar_igl | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 1ba13a5d | edgar_igl | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 1ba13a5d | edgar_igl | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 1ba13a5d | edgar_igl | * THE SOFTWARE.
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23 | 1ba13a5d | edgar_igl | */
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24 | 1ba13a5d | edgar_igl | #include <stdio.h> |
25 | 1ba13a5d | edgar_igl | #include <sys/time.h> |
26 | 1ba13a5d | edgar_igl | #include "hw.h" |
27 | 492c30af | aliguori | #include "qemu-common.h" |
28 | 492c30af | aliguori | #include "sysemu.h" |
29 | 1ba13a5d | edgar_igl | |
30 | 1ba13a5d | edgar_igl | #include "etraxfs_dma.h" |
31 | 1ba13a5d | edgar_igl | |
32 | 1ba13a5d | edgar_igl | #define D(x)
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33 | 1ba13a5d | edgar_igl | |
34 | c01c07bb | edgar_igl | #define RW_DATA (0x0 / 4) |
35 | c01c07bb | edgar_igl | #define RW_SAVED_DATA (0x58 / 4) |
36 | c01c07bb | edgar_igl | #define RW_SAVED_DATA_BUF (0x5c / 4) |
37 | c01c07bb | edgar_igl | #define RW_GROUP (0x60 / 4) |
38 | c01c07bb | edgar_igl | #define RW_GROUP_DOWN (0x7c / 4) |
39 | c01c07bb | edgar_igl | #define RW_CMD (0x80 / 4) |
40 | c01c07bb | edgar_igl | #define RW_CFG (0x84 / 4) |
41 | c01c07bb | edgar_igl | #define RW_STAT (0x88 / 4) |
42 | c01c07bb | edgar_igl | #define RW_INTR_MASK (0x8c / 4) |
43 | c01c07bb | edgar_igl | #define RW_ACK_INTR (0x90 / 4) |
44 | c01c07bb | edgar_igl | #define R_INTR (0x94 / 4) |
45 | c01c07bb | edgar_igl | #define R_MASKED_INTR (0x98 / 4) |
46 | c01c07bb | edgar_igl | #define RW_STREAM_CMD (0x9c / 4) |
47 | c01c07bb | edgar_igl | |
48 | c01c07bb | edgar_igl | #define DMA_REG_MAX (0x100 / 4) |
49 | 1ba13a5d | edgar_igl | |
50 | 1ba13a5d | edgar_igl | /* descriptors */
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51 | 1ba13a5d | edgar_igl | |
52 | 1ba13a5d | edgar_igl | // ------------------------------------------------------------ dma_descr_group
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53 | 1ba13a5d | edgar_igl | typedef struct dma_descr_group { |
54 | 1ba13a5d | edgar_igl | struct dma_descr_group *next;
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55 | 1ba13a5d | edgar_igl | unsigned eol : 1; |
56 | 1ba13a5d | edgar_igl | unsigned tol : 1; |
57 | 1ba13a5d | edgar_igl | unsigned bol : 1; |
58 | 1ba13a5d | edgar_igl | unsigned : 1; |
59 | 1ba13a5d | edgar_igl | unsigned intr : 1; |
60 | 1ba13a5d | edgar_igl | unsigned : 2; |
61 | 1ba13a5d | edgar_igl | unsigned en : 1; |
62 | 1ba13a5d | edgar_igl | unsigned : 7; |
63 | 1ba13a5d | edgar_igl | unsigned dis : 1; |
64 | 1ba13a5d | edgar_igl | unsigned md : 16; |
65 | 1ba13a5d | edgar_igl | struct dma_descr_group *up;
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66 | 1ba13a5d | edgar_igl | union {
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67 | 1ba13a5d | edgar_igl | struct dma_descr_context *context;
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68 | 1ba13a5d | edgar_igl | struct dma_descr_group *group;
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69 | 1ba13a5d | edgar_igl | } down; |
70 | 1ba13a5d | edgar_igl | } dma_descr_group; |
71 | 1ba13a5d | edgar_igl | |
72 | 1ba13a5d | edgar_igl | // ---------------------------------------------------------- dma_descr_context
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73 | 1ba13a5d | edgar_igl | typedef struct dma_descr_context { |
74 | 1ba13a5d | edgar_igl | struct dma_descr_context *next;
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75 | 1ba13a5d | edgar_igl | unsigned eol : 1; |
76 | 1ba13a5d | edgar_igl | unsigned : 3; |
77 | 1ba13a5d | edgar_igl | unsigned intr : 1; |
78 | 1ba13a5d | edgar_igl | unsigned : 1; |
79 | 1ba13a5d | edgar_igl | unsigned store_mode : 1; |
80 | 1ba13a5d | edgar_igl | unsigned en : 1; |
81 | 1ba13a5d | edgar_igl | unsigned : 7; |
82 | 1ba13a5d | edgar_igl | unsigned dis : 1; |
83 | 1ba13a5d | edgar_igl | unsigned md0 : 16; |
84 | 1ba13a5d | edgar_igl | unsigned md1;
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85 | 1ba13a5d | edgar_igl | unsigned md2;
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86 | 1ba13a5d | edgar_igl | unsigned md3;
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87 | 1ba13a5d | edgar_igl | unsigned md4;
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88 | 1ba13a5d | edgar_igl | struct dma_descr_data *saved_data;
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89 | 1ba13a5d | edgar_igl | char *saved_data_buf;
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90 | 1ba13a5d | edgar_igl | } dma_descr_context; |
91 | 1ba13a5d | edgar_igl | |
92 | 1ba13a5d | edgar_igl | // ------------------------------------------------------------- dma_descr_data
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93 | 1ba13a5d | edgar_igl | typedef struct dma_descr_data { |
94 | 1ba13a5d | edgar_igl | struct dma_descr_data *next;
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95 | 1ba13a5d | edgar_igl | char *buf;
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96 | 1ba13a5d | edgar_igl | unsigned eol : 1; |
97 | 1ba13a5d | edgar_igl | unsigned : 2; |
98 | 1ba13a5d | edgar_igl | unsigned out_eop : 1; |
99 | 1ba13a5d | edgar_igl | unsigned intr : 1; |
100 | 1ba13a5d | edgar_igl | unsigned wait : 1; |
101 | 1ba13a5d | edgar_igl | unsigned : 2; |
102 | 1ba13a5d | edgar_igl | unsigned : 3; |
103 | 1ba13a5d | edgar_igl | unsigned in_eop : 1; |
104 | 1ba13a5d | edgar_igl | unsigned : 4; |
105 | 1ba13a5d | edgar_igl | unsigned md : 16; |
106 | 1ba13a5d | edgar_igl | char *after;
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107 | 1ba13a5d | edgar_igl | } dma_descr_data; |
108 | 1ba13a5d | edgar_igl | |
109 | 1ba13a5d | edgar_igl | /* Constants */
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110 | 1ba13a5d | edgar_igl | enum {
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111 | 1ba13a5d | edgar_igl | regk_dma_ack_pkt = 0x00000100,
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112 | 1ba13a5d | edgar_igl | regk_dma_anytime = 0x00000001,
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113 | 1ba13a5d | edgar_igl | regk_dma_array = 0x00000008,
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114 | 1ba13a5d | edgar_igl | regk_dma_burst = 0x00000020,
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115 | 1ba13a5d | edgar_igl | regk_dma_client = 0x00000002,
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116 | 1ba13a5d | edgar_igl | regk_dma_copy_next = 0x00000010,
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117 | 1ba13a5d | edgar_igl | regk_dma_copy_up = 0x00000020,
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118 | 1ba13a5d | edgar_igl | regk_dma_data_at_eol = 0x00000001,
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119 | 1ba13a5d | edgar_igl | regk_dma_dis_c = 0x00000010,
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120 | 1ba13a5d | edgar_igl | regk_dma_dis_g = 0x00000020,
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121 | 1ba13a5d | edgar_igl | regk_dma_idle = 0x00000001,
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122 | 1ba13a5d | edgar_igl | regk_dma_intern = 0x00000004,
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123 | 1ba13a5d | edgar_igl | regk_dma_load_c = 0x00000200,
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124 | 1ba13a5d | edgar_igl | regk_dma_load_c_n = 0x00000280,
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125 | 1ba13a5d | edgar_igl | regk_dma_load_c_next = 0x00000240,
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126 | 1ba13a5d | edgar_igl | regk_dma_load_d = 0x00000140,
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127 | 1ba13a5d | edgar_igl | regk_dma_load_g = 0x00000300,
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128 | 1ba13a5d | edgar_igl | regk_dma_load_g_down = 0x000003c0,
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129 | 1ba13a5d | edgar_igl | regk_dma_load_g_next = 0x00000340,
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130 | 1ba13a5d | edgar_igl | regk_dma_load_g_up = 0x00000380,
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131 | 1ba13a5d | edgar_igl | regk_dma_next_en = 0x00000010,
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132 | 1ba13a5d | edgar_igl | regk_dma_next_pkt = 0x00000010,
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133 | 1ba13a5d | edgar_igl | regk_dma_no = 0x00000000,
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134 | 1ba13a5d | edgar_igl | regk_dma_only_at_wait = 0x00000000,
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135 | 1ba13a5d | edgar_igl | regk_dma_restore = 0x00000020,
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136 | 1ba13a5d | edgar_igl | regk_dma_rst = 0x00000001,
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137 | 1ba13a5d | edgar_igl | regk_dma_running = 0x00000004,
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138 | 1ba13a5d | edgar_igl | regk_dma_rw_cfg_default = 0x00000000,
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139 | 1ba13a5d | edgar_igl | regk_dma_rw_cmd_default = 0x00000000,
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140 | 1ba13a5d | edgar_igl | regk_dma_rw_intr_mask_default = 0x00000000,
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141 | 1ba13a5d | edgar_igl | regk_dma_rw_stat_default = 0x00000101,
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142 | 1ba13a5d | edgar_igl | regk_dma_rw_stream_cmd_default = 0x00000000,
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143 | 1ba13a5d | edgar_igl | regk_dma_save_down = 0x00000020,
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144 | 1ba13a5d | edgar_igl | regk_dma_save_up = 0x00000020,
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145 | 1ba13a5d | edgar_igl | regk_dma_set_reg = 0x00000050,
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146 | 1ba13a5d | edgar_igl | regk_dma_set_w_size1 = 0x00000190,
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147 | 1ba13a5d | edgar_igl | regk_dma_set_w_size2 = 0x000001a0,
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148 | 1ba13a5d | edgar_igl | regk_dma_set_w_size4 = 0x000001c0,
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149 | 1ba13a5d | edgar_igl | regk_dma_stopped = 0x00000002,
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150 | 1ba13a5d | edgar_igl | regk_dma_store_c = 0x00000002,
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151 | 1ba13a5d | edgar_igl | regk_dma_store_descr = 0x00000000,
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152 | 1ba13a5d | edgar_igl | regk_dma_store_g = 0x00000004,
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153 | 1ba13a5d | edgar_igl | regk_dma_store_md = 0x00000001,
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154 | 1ba13a5d | edgar_igl | regk_dma_sw = 0x00000008,
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155 | 1ba13a5d | edgar_igl | regk_dma_update_down = 0x00000020,
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156 | 1ba13a5d | edgar_igl | regk_dma_yes = 0x00000001
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157 | 1ba13a5d | edgar_igl | }; |
158 | 1ba13a5d | edgar_igl | |
159 | 1ba13a5d | edgar_igl | enum dma_ch_state
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160 | 1ba13a5d | edgar_igl | { |
161 | 4487fd34 | edgar_igl | RST = 1,
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162 | 1ba13a5d | edgar_igl | STOPPED = 2,
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163 | 1ba13a5d | edgar_igl | RUNNING = 4
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164 | 1ba13a5d | edgar_igl | }; |
165 | 1ba13a5d | edgar_igl | |
166 | 1ba13a5d | edgar_igl | struct fs_dma_channel
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167 | 1ba13a5d | edgar_igl | { |
168 | 1ba13a5d | edgar_igl | qemu_irq *irq; |
169 | 1ba13a5d | edgar_igl | struct etraxfs_dma_client *client;
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170 | 1ba13a5d | edgar_igl | |
171 | 1ba13a5d | edgar_igl | /* Internal status. */
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172 | 1ba13a5d | edgar_igl | int stream_cmd_src;
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173 | 1ba13a5d | edgar_igl | enum dma_ch_state state;
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174 | 1ba13a5d | edgar_igl | |
175 | 1ba13a5d | edgar_igl | unsigned int input : 1; |
176 | 1ba13a5d | edgar_igl | unsigned int eol : 1; |
177 | 1ba13a5d | edgar_igl | |
178 | 1ba13a5d | edgar_igl | struct dma_descr_group current_g;
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179 | 1ba13a5d | edgar_igl | struct dma_descr_context current_c;
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180 | 1ba13a5d | edgar_igl | struct dma_descr_data current_d;
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181 | 1ba13a5d | edgar_igl | |
182 | 1ba13a5d | edgar_igl | /* Controll registers. */
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183 | 1ba13a5d | edgar_igl | uint32_t regs[DMA_REG_MAX]; |
184 | 1ba13a5d | edgar_igl | }; |
185 | 1ba13a5d | edgar_igl | |
186 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl
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187 | 1ba13a5d | edgar_igl | { |
188 | e6320485 | edgar_igl | int map;
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189 | 1ba13a5d | edgar_igl | CPUState *env; |
190 | 1ba13a5d | edgar_igl | |
191 | 1ba13a5d | edgar_igl | int nr_channels;
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192 | 1ba13a5d | edgar_igl | struct fs_dma_channel *channels;
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193 | 492c30af | aliguori | |
194 | 492c30af | aliguori | QEMUBH *bh; |
195 | 1ba13a5d | edgar_igl | }; |
196 | 1ba13a5d | edgar_igl | |
197 | c01c07bb | edgar_igl | static void DMA_run(void *opaque); |
198 | c01c07bb | edgar_igl | static int channel_out_run(struct fs_dma_ctrl *ctrl, int c); |
199 | c01c07bb | edgar_igl | |
200 | 1ba13a5d | edgar_igl | static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg) |
201 | 1ba13a5d | edgar_igl | { |
202 | 1ba13a5d | edgar_igl | return ctrl->channels[c].regs[reg];
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203 | 1ba13a5d | edgar_igl | } |
204 | 1ba13a5d | edgar_igl | |
205 | 1ba13a5d | edgar_igl | static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c) |
206 | 1ba13a5d | edgar_igl | { |
207 | 1ba13a5d | edgar_igl | return channel_reg(ctrl, c, RW_CFG) & 2; |
208 | 1ba13a5d | edgar_igl | } |
209 | 1ba13a5d | edgar_igl | |
210 | 1ba13a5d | edgar_igl | static inline int channel_en(struct fs_dma_ctrl *ctrl, int c) |
211 | 1ba13a5d | edgar_igl | { |
212 | 1ba13a5d | edgar_igl | return (channel_reg(ctrl, c, RW_CFG) & 1) |
213 | 1ba13a5d | edgar_igl | && ctrl->channels[c].client; |
214 | 1ba13a5d | edgar_igl | } |
215 | 1ba13a5d | edgar_igl | |
216 | 8da3ff18 | pbrook | static inline int fs_channel(target_phys_addr_t addr) |
217 | 1ba13a5d | edgar_igl | { |
218 | 1ba13a5d | edgar_igl | /* Every channel has a 0x2000 ctrl register map. */
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219 | 8da3ff18 | pbrook | return addr >> 13; |
220 | 1ba13a5d | edgar_igl | } |
221 | 1ba13a5d | edgar_igl | |
222 | d297f464 | edgar_igl | #ifdef USE_THIS_DEAD_CODE
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223 | 1ba13a5d | edgar_igl | static void channel_load_g(struct fs_dma_ctrl *ctrl, int c) |
224 | 1ba13a5d | edgar_igl | { |
225 | 1ba13a5d | edgar_igl | target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP); |
226 | 1ba13a5d | edgar_igl | |
227 | 1ba13a5d | edgar_igl | /* Load and decode. FIXME: handle endianness. */
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228 | 1ba13a5d | edgar_igl | cpu_physical_memory_read (addr, |
229 | 1ba13a5d | edgar_igl | (void *) &ctrl->channels[c].current_g,
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230 | 1ba13a5d | edgar_igl | sizeof ctrl->channels[c].current_g);
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231 | 1ba13a5d | edgar_igl | } |
232 | 1ba13a5d | edgar_igl | |
233 | 1ba13a5d | edgar_igl | static void dump_c(int ch, struct dma_descr_context *c) |
234 | 1ba13a5d | edgar_igl | { |
235 | 1ba13a5d | edgar_igl | printf("%s ch=%d\n", __func__, ch);
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236 | d297f464 | edgar_igl | printf("next=%p\n", c->next);
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237 | d297f464 | edgar_igl | printf("saved_data=%p\n", c->saved_data);
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238 | d297f464 | edgar_igl | printf("saved_data_buf=%p\n", c->saved_data_buf);
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239 | 1ba13a5d | edgar_igl | printf("eol=%x\n", (uint32_t) c->eol);
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240 | 1ba13a5d | edgar_igl | } |
241 | 1ba13a5d | edgar_igl | |
242 | 1ba13a5d | edgar_igl | static void dump_d(int ch, struct dma_descr_data *d) |
243 | 1ba13a5d | edgar_igl | { |
244 | 1ba13a5d | edgar_igl | printf("%s ch=%d\n", __func__, ch);
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245 | d297f464 | edgar_igl | printf("next=%p\n", d->next);
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246 | d297f464 | edgar_igl | printf("buf=%p\n", d->buf);
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247 | d297f464 | edgar_igl | printf("after=%p\n", d->after);
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248 | 1ba13a5d | edgar_igl | printf("intr=%x\n", (uint32_t) d->intr);
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249 | 1ba13a5d | edgar_igl | printf("out_eop=%x\n", (uint32_t) d->out_eop);
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250 | 1ba13a5d | edgar_igl | printf("in_eop=%x\n", (uint32_t) d->in_eop);
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251 | 1ba13a5d | edgar_igl | printf("eol=%x\n", (uint32_t) d->eol);
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252 | 1ba13a5d | edgar_igl | } |
253 | d297f464 | edgar_igl | #endif
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254 | 1ba13a5d | edgar_igl | |
255 | 1ba13a5d | edgar_igl | static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) |
256 | 1ba13a5d | edgar_igl | { |
257 | 1ba13a5d | edgar_igl | target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); |
258 | 1ba13a5d | edgar_igl | |
259 | 1ba13a5d | edgar_igl | /* Load and decode. FIXME: handle endianness. */
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260 | 1ba13a5d | edgar_igl | cpu_physical_memory_read (addr, |
261 | 1ba13a5d | edgar_igl | (void *) &ctrl->channels[c].current_c,
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262 | 1ba13a5d | edgar_igl | sizeof ctrl->channels[c].current_c);
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263 | 1ba13a5d | edgar_igl | |
264 | 1ba13a5d | edgar_igl | D(dump_c(c, &ctrl->channels[c].current_c)); |
265 | 1ba13a5d | edgar_igl | /* I guess this should update the current pos. */
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266 | d297f464 | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA] = |
267 | d297f464 | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data; |
268 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
269 | d297f464 | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data_buf; |
270 | 1ba13a5d | edgar_igl | } |
271 | 1ba13a5d | edgar_igl | |
272 | 1ba13a5d | edgar_igl | static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) |
273 | 1ba13a5d | edgar_igl | { |
274 | 1ba13a5d | edgar_igl | target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); |
275 | 1ba13a5d | edgar_igl | |
276 | 1ba13a5d | edgar_igl | /* Load and decode. FIXME: handle endianness. */
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277 | a8303d18 | edgar_igl | D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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278 | 1ba13a5d | edgar_igl | cpu_physical_memory_read (addr, |
279 | 1ba13a5d | edgar_igl | (void *) &ctrl->channels[c].current_d,
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280 | 1ba13a5d | edgar_igl | sizeof ctrl->channels[c].current_d);
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281 | 1ba13a5d | edgar_igl | |
282 | 1ba13a5d | edgar_igl | D(dump_d(c, &ctrl->channels[c].current_d)); |
283 | fa1bdde4 | edgar_igl | ctrl->channels[c].regs[RW_DATA] = addr; |
284 | a8303d18 | edgar_igl | } |
285 | a8303d18 | edgar_igl | |
286 | a8303d18 | edgar_igl | static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) |
287 | a8303d18 | edgar_igl | { |
288 | a8303d18 | edgar_igl | target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); |
289 | a8303d18 | edgar_igl | |
290 | a8303d18 | edgar_igl | /* Encode and store. FIXME: handle endianness. */
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291 | a8303d18 | edgar_igl | D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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292 | a8303d18 | edgar_igl | D(dump_d(c, &ctrl->channels[c].current_d)); |
293 | a8303d18 | edgar_igl | cpu_physical_memory_write (addr, |
294 | a8303d18 | edgar_igl | (void *) &ctrl->channels[c].current_c,
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295 | a8303d18 | edgar_igl | sizeof ctrl->channels[c].current_c);
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296 | 1ba13a5d | edgar_igl | } |
297 | 1ba13a5d | edgar_igl | |
298 | 1ba13a5d | edgar_igl | static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) |
299 | 1ba13a5d | edgar_igl | { |
300 | 1ba13a5d | edgar_igl | target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); |
301 | 1ba13a5d | edgar_igl | |
302 | a8303d18 | edgar_igl | /* Encode and store. FIXME: handle endianness. */
|
303 | a8303d18 | edgar_igl | D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
|
304 | 1ba13a5d | edgar_igl | cpu_physical_memory_write (addr, |
305 | 1ba13a5d | edgar_igl | (void *) &ctrl->channels[c].current_d,
|
306 | 1ba13a5d | edgar_igl | sizeof ctrl->channels[c].current_d);
|
307 | 1ba13a5d | edgar_igl | } |
308 | 1ba13a5d | edgar_igl | |
309 | 1ba13a5d | edgar_igl | static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c) |
310 | 1ba13a5d | edgar_igl | { |
311 | 1ba13a5d | edgar_igl | /* FIXME: */
|
312 | 1ba13a5d | edgar_igl | } |
313 | 1ba13a5d | edgar_igl | |
314 | 1ba13a5d | edgar_igl | static inline void channel_start(struct fs_dma_ctrl *ctrl, int c) |
315 | 1ba13a5d | edgar_igl | { |
316 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].client)
|
317 | 1ba13a5d | edgar_igl | { |
318 | 1ba13a5d | edgar_igl | ctrl->channels[c].eol = 0;
|
319 | 1ba13a5d | edgar_igl | ctrl->channels[c].state = RUNNING; |
320 | c01c07bb | edgar_igl | if (!ctrl->channels[c].input)
|
321 | c01c07bb | edgar_igl | channel_out_run(ctrl, c); |
322 | 1ba13a5d | edgar_igl | } else
|
323 | 1ba13a5d | edgar_igl | printf("WARNING: starting DMA ch %d with no client\n", c);
|
324 | 1ab5f75c | edgar_igl | |
325 | 1ab5f75c | edgar_igl | qemu_bh_schedule_idle(ctrl->bh); |
326 | 1ba13a5d | edgar_igl | } |
327 | 1ba13a5d | edgar_igl | |
328 | 1ba13a5d | edgar_igl | static void channel_continue(struct fs_dma_ctrl *ctrl, int c) |
329 | 1ba13a5d | edgar_igl | { |
330 | 1ba13a5d | edgar_igl | if (!channel_en(ctrl, c)
|
331 | 1ba13a5d | edgar_igl | || channel_stopped(ctrl, c) |
332 | 1ba13a5d | edgar_igl | || ctrl->channels[c].state != RUNNING |
333 | 1ba13a5d | edgar_igl | /* Only reload the current data descriptor if it has eol set. */
|
334 | 1ba13a5d | edgar_igl | || !ctrl->channels[c].current_d.eol) { |
335 | 1ba13a5d | edgar_igl | D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n",
|
336 | 1ba13a5d | edgar_igl | c, ctrl->channels[c].state, |
337 | 1ba13a5d | edgar_igl | channel_stopped(ctrl, c), |
338 | 1ba13a5d | edgar_igl | channel_en(ctrl,c), |
339 | 1ba13a5d | edgar_igl | ctrl->channels[c].eol)); |
340 | 1ba13a5d | edgar_igl | D(dump_d(c, &ctrl->channels[c].current_d)); |
341 | 1ba13a5d | edgar_igl | return;
|
342 | 1ba13a5d | edgar_igl | } |
343 | 1ba13a5d | edgar_igl | |
344 | 1ba13a5d | edgar_igl | /* Reload the current descriptor. */
|
345 | 1ba13a5d | edgar_igl | channel_load_d(ctrl, c); |
346 | 1ba13a5d | edgar_igl | |
347 | 1ba13a5d | edgar_igl | /* If the current descriptor cleared the eol flag and we had already
|
348 | 1ba13a5d | edgar_igl | reached eol state, do the continue. */
|
349 | 1ba13a5d | edgar_igl | if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
|
350 | a8303d18 | edgar_igl | D(printf("continue %d ok %p\n", c,
|
351 | 1ba13a5d | edgar_igl | ctrl->channels[c].current_d.next)); |
352 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA] = |
353 | d297f464 | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_d.next; |
354 | 1ba13a5d | edgar_igl | channel_load_d(ctrl, c); |
355 | c01c07bb | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
356 | c01c07bb | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf; |
357 | c01c07bb | edgar_igl | |
358 | 1ba13a5d | edgar_igl | channel_start(ctrl, c); |
359 | 1ba13a5d | edgar_igl | } |
360 | a8303d18 | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
361 | d297f464 | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf; |
362 | 1ba13a5d | edgar_igl | } |
363 | 1ba13a5d | edgar_igl | |
364 | 1ba13a5d | edgar_igl | static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v) |
365 | 1ba13a5d | edgar_igl | { |
366 | 1ba13a5d | edgar_igl | unsigned int cmd = v & ((1 << 10) - 1); |
367 | 1ba13a5d | edgar_igl | |
368 | d27b2e50 | edgar_igl | D(printf("%s ch=%d cmd=%x\n",
|
369 | d27b2e50 | edgar_igl | __func__, c, cmd)); |
370 | 1ba13a5d | edgar_igl | if (cmd & regk_dma_load_d) {
|
371 | 1ba13a5d | edgar_igl | channel_load_d(ctrl, c); |
372 | 1ba13a5d | edgar_igl | if (cmd & regk_dma_burst)
|
373 | 1ba13a5d | edgar_igl | channel_start(ctrl, c); |
374 | 1ba13a5d | edgar_igl | } |
375 | 1ba13a5d | edgar_igl | |
376 | 1ba13a5d | edgar_igl | if (cmd & regk_dma_load_c) {
|
377 | 1ba13a5d | edgar_igl | channel_load_c(ctrl, c); |
378 | 1ba13a5d | edgar_igl | } |
379 | 1ba13a5d | edgar_igl | } |
380 | 1ba13a5d | edgar_igl | |
381 | 1ba13a5d | edgar_igl | static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c) |
382 | 1ba13a5d | edgar_igl | { |
383 | 1ba13a5d | edgar_igl | D(printf("%s %d\n", __func__, c));
|
384 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_INTR] &= |
385 | 1ba13a5d | edgar_igl | ~(ctrl->channels[c].regs[RW_ACK_INTR]); |
386 | 1ba13a5d | edgar_igl | |
387 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_MASKED_INTR] = |
388 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_INTR] |
389 | 1ba13a5d | edgar_igl | & ctrl->channels[c].regs[RW_INTR_MASK]; |
390 | 1ba13a5d | edgar_igl | |
391 | 1ba13a5d | edgar_igl | D(printf("%s: chan=%d masked_intr=%x\n", __func__,
|
392 | 1ba13a5d | edgar_igl | c, |
393 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_MASKED_INTR])); |
394 | 1ba13a5d | edgar_igl | |
395 | 7a3161ba | Edgar E. Iglesias | qemu_set_irq(ctrl->channels[c].irq[0],
|
396 | 7a3161ba | Edgar E. Iglesias | !!ctrl->channels[c].regs[R_MASKED_INTR]); |
397 | 1ba13a5d | edgar_igl | } |
398 | 1ba13a5d | edgar_igl | |
399 | 1ab5f75c | edgar_igl | static int channel_out_run(struct fs_dma_ctrl *ctrl, int c) |
400 | 1ba13a5d | edgar_igl | { |
401 | 1ba13a5d | edgar_igl | uint32_t len; |
402 | 1ba13a5d | edgar_igl | uint32_t saved_data_buf; |
403 | 1ba13a5d | edgar_igl | unsigned char buf[2 * 1024]; |
404 | 1ba13a5d | edgar_igl | |
405 | 1ab5f75c | edgar_igl | if (ctrl->channels[c].eol)
|
406 | 1ab5f75c | edgar_igl | return 0; |
407 | 1ab5f75c | edgar_igl | |
408 | 1ab5f75c | edgar_igl | do {
|
409 | c968ef8d | edgar_igl | D(printf("ch=%d buf=%x after=%x saved_data_buf=%x\n",
|
410 | c968ef8d | edgar_igl | c, |
411 | c968ef8d | edgar_igl | (uint32_t)ctrl->channels[c].current_d.buf, |
412 | c968ef8d | edgar_igl | (uint32_t)ctrl->channels[c].current_d.after, |
413 | c968ef8d | edgar_igl | saved_data_buf)); |
414 | c968ef8d | edgar_igl | |
415 | c01c07bb | edgar_igl | channel_load_d(ctrl, c); |
416 | c01c07bb | edgar_igl | saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); |
417 | ea0f49a7 | edgar_igl | len = (uint32_t)(unsigned long) |
418 | ea0f49a7 | edgar_igl | ctrl->channels[c].current_d.after; |
419 | c968ef8d | edgar_igl | len -= saved_data_buf; |
420 | c968ef8d | edgar_igl | |
421 | c968ef8d | edgar_igl | if (len > sizeof buf) |
422 | c968ef8d | edgar_igl | len = sizeof buf;
|
423 | c968ef8d | edgar_igl | cpu_physical_memory_read (saved_data_buf, buf, len); |
424 | c968ef8d | edgar_igl | |
425 | c968ef8d | edgar_igl | D(printf("channel %d pushes %x %u bytes\n", c,
|
426 | c968ef8d | edgar_igl | saved_data_buf, len)); |
427 | c968ef8d | edgar_igl | |
428 | c968ef8d | edgar_igl | if (ctrl->channels[c].client->client.push)
|
429 | c968ef8d | edgar_igl | ctrl->channels[c].client->client.push( |
430 | c968ef8d | edgar_igl | ctrl->channels[c].client->client.opaque, |
431 | c968ef8d | edgar_igl | buf, len); |
432 | c968ef8d | edgar_igl | else
|
433 | c968ef8d | edgar_igl | printf("WARNING: DMA ch%d dataloss,"
|
434 | c968ef8d | edgar_igl | " no attached client.\n", c);
|
435 | c968ef8d | edgar_igl | |
436 | c968ef8d | edgar_igl | saved_data_buf += len; |
437 | c968ef8d | edgar_igl | |
438 | ea0f49a7 | edgar_igl | if (saved_data_buf == (uint32_t)(unsigned long) |
439 | ea0f49a7 | edgar_igl | ctrl->channels[c].current_d.after) { |
440 | c968ef8d | edgar_igl | /* Done. Step to next. */
|
441 | c968ef8d | edgar_igl | if (ctrl->channels[c].current_d.out_eop) {
|
442 | c968ef8d | edgar_igl | /* TODO: signal eop to the client. */
|
443 | c968ef8d | edgar_igl | D(printf("signal eop\n"));
|
444 | c968ef8d | edgar_igl | } |
445 | c968ef8d | edgar_igl | if (ctrl->channels[c].current_d.intr) {
|
446 | c968ef8d | edgar_igl | /* TODO: signal eop to the client. */
|
447 | c968ef8d | edgar_igl | /* data intr. */
|
448 | c01c07bb | edgar_igl | D(printf("signal intr %d eol=%d\n",
|
449 | c01c07bb | edgar_igl | len, ctrl->channels[c].current_d.eol)); |
450 | c968ef8d | edgar_igl | ctrl->channels[c].regs[R_INTR] |= (1 << 2); |
451 | c968ef8d | edgar_igl | channel_update_irq(ctrl, c); |
452 | c968ef8d | edgar_igl | } |
453 | c01c07bb | edgar_igl | channel_store_d(ctrl, c); |
454 | c968ef8d | edgar_igl | if (ctrl->channels[c].current_d.eol) {
|
455 | c968ef8d | edgar_igl | D(printf("channel %d EOL\n", c));
|
456 | c968ef8d | edgar_igl | ctrl->channels[c].eol = 1;
|
457 | c968ef8d | edgar_igl | |
458 | c968ef8d | edgar_igl | /* Mark the context as disabled. */
|
459 | c968ef8d | edgar_igl | ctrl->channels[c].current_c.dis = 1;
|
460 | c968ef8d | edgar_igl | channel_store_c(ctrl, c); |
461 | c968ef8d | edgar_igl | |
462 | c968ef8d | edgar_igl | channel_stop(ctrl, c); |
463 | c968ef8d | edgar_igl | } else {
|
464 | c968ef8d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA] = |
465 | ea0f49a7 | edgar_igl | (uint32_t)(unsigned long)ctrl-> |
466 | ea0f49a7 | edgar_igl | channels[c].current_d.next; |
467 | c968ef8d | edgar_igl | /* Load new descriptor. */
|
468 | c968ef8d | edgar_igl | channel_load_d(ctrl, c); |
469 | c968ef8d | edgar_igl | saved_data_buf = (uint32_t)(unsigned long) |
470 | c968ef8d | edgar_igl | ctrl->channels[c].current_d.buf; |
471 | c968ef8d | edgar_igl | } |
472 | c968ef8d | edgar_igl | |
473 | c968ef8d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
474 | c968ef8d | edgar_igl | saved_data_buf; |
475 | c968ef8d | edgar_igl | D(dump_d(c, &ctrl->channels[c].current_d)); |
476 | 1ba13a5d | edgar_igl | } |
477 | a8303d18 | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; |
478 | 1ab5f75c | edgar_igl | } while (!ctrl->channels[c].eol);
|
479 | 1ab5f75c | edgar_igl | return 1; |
480 | 1ba13a5d | edgar_igl | } |
481 | 1ba13a5d | edgar_igl | |
482 | 1ba13a5d | edgar_igl | static int channel_in_process(struct fs_dma_ctrl *ctrl, int c, |
483 | 1ba13a5d | edgar_igl | unsigned char *buf, int buflen, int eop) |
484 | 1ba13a5d | edgar_igl | { |
485 | 1ba13a5d | edgar_igl | uint32_t len; |
486 | 1ba13a5d | edgar_igl | uint32_t saved_data_buf; |
487 | 1ba13a5d | edgar_igl | |
488 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].eol == 1) |
489 | 1ba13a5d | edgar_igl | return 0; |
490 | 1ba13a5d | edgar_igl | |
491 | c01c07bb | edgar_igl | channel_load_d(ctrl, c); |
492 | 1ba13a5d | edgar_igl | saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); |
493 | ea0f49a7 | edgar_igl | len = (uint32_t)(unsigned long)ctrl->channels[c].current_d.after; |
494 | 1ba13a5d | edgar_igl | len -= saved_data_buf; |
495 | 1ba13a5d | edgar_igl | |
496 | 1ba13a5d | edgar_igl | if (len > buflen)
|
497 | 1ba13a5d | edgar_igl | len = buflen; |
498 | 1ba13a5d | edgar_igl | |
499 | 1ba13a5d | edgar_igl | cpu_physical_memory_write (saved_data_buf, buf, len); |
500 | 1ba13a5d | edgar_igl | saved_data_buf += len; |
501 | 1ba13a5d | edgar_igl | |
502 | d297f464 | edgar_igl | if (saved_data_buf ==
|
503 | ea0f49a7 | edgar_igl | (uint32_t)(unsigned long)ctrl->channels[c].current_d.after |
504 | 1ba13a5d | edgar_igl | || eop) { |
505 | 1ba13a5d | edgar_igl | uint32_t r_intr = ctrl->channels[c].regs[R_INTR]; |
506 | 1ba13a5d | edgar_igl | |
507 | 1ba13a5d | edgar_igl | D(printf("in dscr end len=%d\n",
|
508 | 1ba13a5d | edgar_igl | ctrl->channels[c].current_d.after |
509 | 1ba13a5d | edgar_igl | - ctrl->channels[c].current_d.buf)); |
510 | 1ba13a5d | edgar_igl | ctrl->channels[c].current_d.after = |
511 | d297f464 | edgar_igl | (void *)(unsigned long) saved_data_buf; |
512 | 1ba13a5d | edgar_igl | |
513 | 1ba13a5d | edgar_igl | /* Done. Step to next. */
|
514 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].current_d.intr) {
|
515 | 1ba13a5d | edgar_igl | /* TODO: signal eop to the client. */
|
516 | 1ba13a5d | edgar_igl | /* data intr. */
|
517 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_INTR] |= 3;
|
518 | 1ba13a5d | edgar_igl | } |
519 | 1ba13a5d | edgar_igl | if (eop) {
|
520 | 1ba13a5d | edgar_igl | ctrl->channels[c].current_d.in_eop = 1;
|
521 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[R_INTR] |= 8;
|
522 | 1ba13a5d | edgar_igl | } |
523 | 1ba13a5d | edgar_igl | if (r_intr != ctrl->channels[c].regs[R_INTR])
|
524 | 1ba13a5d | edgar_igl | channel_update_irq(ctrl, c); |
525 | 1ba13a5d | edgar_igl | |
526 | 1ba13a5d | edgar_igl | channel_store_d(ctrl, c); |
527 | 1ba13a5d | edgar_igl | D(dump_d(c, &ctrl->channels[c].current_d)); |
528 | 1ba13a5d | edgar_igl | |
529 | 1ba13a5d | edgar_igl | if (ctrl->channels[c].current_d.eol) {
|
530 | 1ba13a5d | edgar_igl | D(printf("channel %d EOL\n", c));
|
531 | 1ba13a5d | edgar_igl | ctrl->channels[c].eol = 1;
|
532 | a8303d18 | edgar_igl | |
533 | a8303d18 | edgar_igl | /* Mark the context as disabled. */
|
534 | a8303d18 | edgar_igl | ctrl->channels[c].current_c.dis = 1;
|
535 | a8303d18 | edgar_igl | channel_store_c(ctrl, c); |
536 | a8303d18 | edgar_igl | |
537 | 1ba13a5d | edgar_igl | channel_stop(ctrl, c); |
538 | 1ba13a5d | edgar_igl | } else {
|
539 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA] = |
540 | ea0f49a7 | edgar_igl | (uint32_t)(unsigned long)ctrl-> |
541 | ea0f49a7 | edgar_igl | channels[c].current_d.next; |
542 | 1ba13a5d | edgar_igl | /* Load new descriptor. */
|
543 | 1ba13a5d | edgar_igl | channel_load_d(ctrl, c); |
544 | ea0f49a7 | edgar_igl | saved_data_buf = (uint32_t)(unsigned long) |
545 | a8303d18 | edgar_igl | ctrl->channels[c].current_d.buf; |
546 | 1ba13a5d | edgar_igl | } |
547 | 1ba13a5d | edgar_igl | } |
548 | 1ba13a5d | edgar_igl | |
549 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; |
550 | 1ba13a5d | edgar_igl | return len;
|
551 | 1ba13a5d | edgar_igl | } |
552 | 1ba13a5d | edgar_igl | |
553 | 1ab5f75c | edgar_igl | static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c) |
554 | 1ba13a5d | edgar_igl | { |
555 | 1ab5f75c | edgar_igl | if (ctrl->channels[c].client->client.pull) {
|
556 | 1ba13a5d | edgar_igl | ctrl->channels[c].client->client.pull( |
557 | 1ba13a5d | edgar_igl | ctrl->channels[c].client->client.opaque); |
558 | 1ab5f75c | edgar_igl | return 1; |
559 | 1ab5f75c | edgar_igl | } else
|
560 | 1ab5f75c | edgar_igl | return 0; |
561 | 1ba13a5d | edgar_igl | } |
562 | 1ba13a5d | edgar_igl | |
563 | 1ba13a5d | edgar_igl | static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr) |
564 | 1ba13a5d | edgar_igl | { |
565 | 2ac71179 | Paul Brook | hw_error("Unsupported short access. reg=" TARGET_FMT_plx "\n", addr); |
566 | 1ba13a5d | edgar_igl | return 0; |
567 | 1ba13a5d | edgar_igl | } |
568 | 1ba13a5d | edgar_igl | |
569 | 1ba13a5d | edgar_igl | static uint32_t
|
570 | 1ba13a5d | edgar_igl | dma_readl (void *opaque, target_phys_addr_t addr)
|
571 | 1ba13a5d | edgar_igl | { |
572 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
573 | 1ba13a5d | edgar_igl | int c;
|
574 | 1ba13a5d | edgar_igl | uint32_t r = 0;
|
575 | 1ba13a5d | edgar_igl | |
576 | e6320485 | edgar_igl | /* Make addr relative to this channel and bounded to nr regs. */
|
577 | 8da3ff18 | pbrook | c = fs_channel(addr); |
578 | e6320485 | edgar_igl | addr &= 0xff;
|
579 | c01c07bb | edgar_igl | addr >>= 2;
|
580 | 1ba13a5d | edgar_igl | switch (addr)
|
581 | a8303d18 | edgar_igl | { |
582 | 1ba13a5d | edgar_igl | case RW_STAT:
|
583 | 1ba13a5d | edgar_igl | r = ctrl->channels[c].state & 7;
|
584 | 1ba13a5d | edgar_igl | r |= ctrl->channels[c].eol << 5;
|
585 | 1ba13a5d | edgar_igl | r |= ctrl->channels[c].stream_cmd_src << 8;
|
586 | 1ba13a5d | edgar_igl | break;
|
587 | 1ba13a5d | edgar_igl | |
588 | a8303d18 | edgar_igl | default:
|
589 | 1ba13a5d | edgar_igl | r = ctrl->channels[c].regs[addr]; |
590 | d27b2e50 | edgar_igl | D(printf ("%s c=%d addr=%x\n",
|
591 | d27b2e50 | edgar_igl | __func__, c, addr)); |
592 | a8303d18 | edgar_igl | break;
|
593 | a8303d18 | edgar_igl | } |
594 | 1ba13a5d | edgar_igl | return r;
|
595 | 1ba13a5d | edgar_igl | } |
596 | 1ba13a5d | edgar_igl | |
597 | 1ba13a5d | edgar_igl | static void |
598 | 1ba13a5d | edgar_igl | dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
|
599 | 1ba13a5d | edgar_igl | { |
600 | 2ac71179 | Paul Brook | hw_error("Unsupported short access. reg=" TARGET_FMT_plx "\n", addr); |
601 | 1ba13a5d | edgar_igl | } |
602 | 1ba13a5d | edgar_igl | |
603 | 1ba13a5d | edgar_igl | static void |
604 | 4487fd34 | edgar_igl | dma_update_state(struct fs_dma_ctrl *ctrl, int c) |
605 | 4487fd34 | edgar_igl | { |
606 | 4487fd34 | edgar_igl | if ((ctrl->channels[c].regs[RW_CFG] & 1) != 3) { |
607 | 4487fd34 | edgar_igl | if (ctrl->channels[c].regs[RW_CFG] & 2) |
608 | 4487fd34 | edgar_igl | ctrl->channels[c].state = STOPPED; |
609 | 4487fd34 | edgar_igl | if (!(ctrl->channels[c].regs[RW_CFG] & 1)) |
610 | 4487fd34 | edgar_igl | ctrl->channels[c].state = RST; |
611 | 4487fd34 | edgar_igl | } |
612 | 4487fd34 | edgar_igl | } |
613 | 4487fd34 | edgar_igl | |
614 | 4487fd34 | edgar_igl | static void |
615 | 1ba13a5d | edgar_igl | dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
|
616 | 1ba13a5d | edgar_igl | { |
617 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
618 | 1ba13a5d | edgar_igl | int c;
|
619 | 1ba13a5d | edgar_igl | |
620 | e6320485 | edgar_igl | /* Make addr relative to this channel and bounded to nr regs. */
|
621 | 8da3ff18 | pbrook | c = fs_channel(addr); |
622 | e6320485 | edgar_igl | addr &= 0xff;
|
623 | c01c07bb | edgar_igl | addr >>= 2;
|
624 | 1ba13a5d | edgar_igl | switch (addr)
|
625 | a8303d18 | edgar_igl | { |
626 | 1ba13a5d | edgar_igl | case RW_DATA:
|
627 | fa1bdde4 | edgar_igl | ctrl->channels[c].regs[addr] = value; |
628 | 1ba13a5d | edgar_igl | break;
|
629 | 1ba13a5d | edgar_igl | |
630 | 1ba13a5d | edgar_igl | case RW_CFG:
|
631 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[addr] = value; |
632 | 4487fd34 | edgar_igl | dma_update_state(ctrl, c); |
633 | 1ba13a5d | edgar_igl | break;
|
634 | 1ba13a5d | edgar_igl | case RW_CMD:
|
635 | 1ba13a5d | edgar_igl | /* continue. */
|
636 | 4487fd34 | edgar_igl | if (value & ~1) |
637 | 4487fd34 | edgar_igl | printf("Invalid store to ch=%d RW_CMD %x\n",
|
638 | 4487fd34 | edgar_igl | c, value); |
639 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[addr] = value; |
640 | 1ba13a5d | edgar_igl | channel_continue(ctrl, c); |
641 | 1ba13a5d | edgar_igl | break;
|
642 | 1ba13a5d | edgar_igl | |
643 | 1ba13a5d | edgar_igl | case RW_SAVED_DATA:
|
644 | 1ba13a5d | edgar_igl | case RW_SAVED_DATA_BUF:
|
645 | 1ba13a5d | edgar_igl | case RW_GROUP:
|
646 | 1ba13a5d | edgar_igl | case RW_GROUP_DOWN:
|
647 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[addr] = value; |
648 | 1ba13a5d | edgar_igl | break;
|
649 | 1ba13a5d | edgar_igl | |
650 | 1ba13a5d | edgar_igl | case RW_ACK_INTR:
|
651 | 1ba13a5d | edgar_igl | case RW_INTR_MASK:
|
652 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[addr] = value; |
653 | 1ba13a5d | edgar_igl | channel_update_irq(ctrl, c); |
654 | 1ba13a5d | edgar_igl | if (addr == RW_ACK_INTR)
|
655 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[RW_ACK_INTR] = 0;
|
656 | 1ba13a5d | edgar_igl | break;
|
657 | 1ba13a5d | edgar_igl | |
658 | 1ba13a5d | edgar_igl | case RW_STREAM_CMD:
|
659 | 4487fd34 | edgar_igl | if (value & ~1023) |
660 | 4487fd34 | edgar_igl | printf("Invalid store to ch=%d "
|
661 | 4487fd34 | edgar_igl | "RW_STREAMCMD %x\n",
|
662 | 4487fd34 | edgar_igl | c, value); |
663 | 1ba13a5d | edgar_igl | ctrl->channels[c].regs[addr] = value; |
664 | d27b2e50 | edgar_igl | D(printf("stream_cmd ch=%d\n", c));
|
665 | 1ba13a5d | edgar_igl | channel_stream_cmd(ctrl, c, value); |
666 | 1ba13a5d | edgar_igl | break;
|
667 | 1ba13a5d | edgar_igl | |
668 | a8303d18 | edgar_igl | default:
|
669 | d27b2e50 | edgar_igl | D(printf ("%s c=%d %x %x\n", __func__, c, addr));
|
670 | a8303d18 | edgar_igl | break;
|
671 | 1ba13a5d | edgar_igl | } |
672 | 1ba13a5d | edgar_igl | } |
673 | 1ba13a5d | edgar_igl | |
674 | 1ba13a5d | edgar_igl | static CPUReadMemoryFunc *dma_read[] = {
|
675 | 1ba13a5d | edgar_igl | &dma_rinvalid, |
676 | 1ba13a5d | edgar_igl | &dma_rinvalid, |
677 | 1ba13a5d | edgar_igl | &dma_readl, |
678 | 1ba13a5d | edgar_igl | }; |
679 | 1ba13a5d | edgar_igl | |
680 | 1ba13a5d | edgar_igl | static CPUWriteMemoryFunc *dma_write[] = {
|
681 | 1ba13a5d | edgar_igl | &dma_winvalid, |
682 | 1ba13a5d | edgar_igl | &dma_winvalid, |
683 | 1ba13a5d | edgar_igl | &dma_writel, |
684 | 1ba13a5d | edgar_igl | }; |
685 | 1ba13a5d | edgar_igl | |
686 | 1ab5f75c | edgar_igl | static int etraxfs_dmac_run(void *opaque) |
687 | 1ba13a5d | edgar_igl | { |
688 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
689 | 1ba13a5d | edgar_igl | int i;
|
690 | 1ba13a5d | edgar_igl | int p = 0; |
691 | 1ba13a5d | edgar_igl | |
692 | 1ba13a5d | edgar_igl | for (i = 0; |
693 | 1ba13a5d | edgar_igl | i < ctrl->nr_channels; |
694 | 1ba13a5d | edgar_igl | i++) |
695 | 1ba13a5d | edgar_igl | { |
696 | 1ba13a5d | edgar_igl | if (ctrl->channels[i].state == RUNNING)
|
697 | 1ba13a5d | edgar_igl | { |
698 | 1ab5f75c | edgar_igl | if (ctrl->channels[i].input) {
|
699 | 1ab5f75c | edgar_igl | p += channel_in_run(ctrl, i); |
700 | 1ab5f75c | edgar_igl | } else {
|
701 | 1ab5f75c | edgar_igl | p += channel_out_run(ctrl, i); |
702 | 1ab5f75c | edgar_igl | } |
703 | 1ba13a5d | edgar_igl | } |
704 | 1ba13a5d | edgar_igl | } |
705 | 1ab5f75c | edgar_igl | return p;
|
706 | 1ba13a5d | edgar_igl | } |
707 | 1ba13a5d | edgar_igl | |
708 | 1ba13a5d | edgar_igl | int etraxfs_dmac_input(struct etraxfs_dma_client *client, |
709 | 1ba13a5d | edgar_igl | void *buf, int len, int eop) |
710 | 1ba13a5d | edgar_igl | { |
711 | 1ba13a5d | edgar_igl | return channel_in_process(client->ctrl, client->channel,
|
712 | 1ba13a5d | edgar_igl | buf, len, eop); |
713 | 1ba13a5d | edgar_igl | } |
714 | 1ba13a5d | edgar_igl | |
715 | 1ba13a5d | edgar_igl | /* Connect an IRQ line with a channel. */
|
716 | 1ba13a5d | edgar_igl | void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input) |
717 | 1ba13a5d | edgar_igl | { |
718 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
719 | 1ba13a5d | edgar_igl | ctrl->channels[c].irq = line; |
720 | 1ba13a5d | edgar_igl | ctrl->channels[c].input = input; |
721 | 1ba13a5d | edgar_igl | } |
722 | 1ba13a5d | edgar_igl | |
723 | 1ba13a5d | edgar_igl | void etraxfs_dmac_connect_client(void *opaque, int c, |
724 | 1ba13a5d | edgar_igl | struct etraxfs_dma_client *cl)
|
725 | 1ba13a5d | edgar_igl | { |
726 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = opaque;
|
727 | 1ba13a5d | edgar_igl | cl->ctrl = ctrl; |
728 | 1ba13a5d | edgar_igl | cl->channel = c; |
729 | 1ba13a5d | edgar_igl | ctrl->channels[c].client = cl; |
730 | 1ba13a5d | edgar_igl | } |
731 | 1ba13a5d | edgar_igl | |
732 | 1ba13a5d | edgar_igl | |
733 | 492c30af | aliguori | static void DMA_run(void *opaque) |
734 | fa1bdde4 | edgar_igl | { |
735 | 492c30af | aliguori | struct fs_dma_ctrl *etraxfs_dmac = opaque;
|
736 | 1ab5f75c | edgar_igl | int p = 1; |
737 | 1ab5f75c | edgar_igl | |
738 | 492c30af | aliguori | if (vm_running)
|
739 | 1ab5f75c | edgar_igl | p = etraxfs_dmac_run(etraxfs_dmac); |
740 | 1ab5f75c | edgar_igl | |
741 | 1ab5f75c | edgar_igl | if (p)
|
742 | 1ab5f75c | edgar_igl | qemu_bh_schedule_idle(etraxfs_dmac->bh); |
743 | fa1bdde4 | edgar_igl | } |
744 | fa1bdde4 | edgar_igl | |
745 | 1ba13a5d | edgar_igl | void *etraxfs_dmac_init(CPUState *env,
|
746 | 1ba13a5d | edgar_igl | target_phys_addr_t base, int nr_channels)
|
747 | 1ba13a5d | edgar_igl | { |
748 | 1ba13a5d | edgar_igl | struct fs_dma_ctrl *ctrl = NULL; |
749 | 1ba13a5d | edgar_igl | |
750 | 1ba13a5d | edgar_igl | ctrl = qemu_mallocz(sizeof *ctrl);
|
751 | 1ba13a5d | edgar_igl | |
752 | 492c30af | aliguori | ctrl->bh = qemu_bh_new(DMA_run, ctrl); |
753 | 492c30af | aliguori | |
754 | 1ba13a5d | edgar_igl | ctrl->env = env; |
755 | 1ba13a5d | edgar_igl | ctrl->nr_channels = nr_channels; |
756 | 1ba13a5d | edgar_igl | ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels); |
757 | 1ba13a5d | edgar_igl | |
758 | e6320485 | edgar_igl | ctrl->map = cpu_register_io_memory(0, dma_read, dma_write, ctrl);
|
759 | e6320485 | edgar_igl | cpu_register_physical_memory(base, nr_channels * 0x2000, ctrl->map);
|
760 | 1ba13a5d | edgar_igl | return ctrl;
|
761 | 1ba13a5d | edgar_igl | } |