root / hw / usb-uhci.c @ 4b816985
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/*
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* USB UHCI controller emulation
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Copyright (c) 2008 Max Krasnyansky
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* Magor rewrite of the UHCI data structures parser and frame processor
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* Support for fully async operation and multiple outstanding transactions
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "usb.h" |
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#include "pci.h" |
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#include "qemu-timer.h" |
32 |
|
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//#define DEBUG
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//#define DEBUG_DUMP_DATA
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|
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#define UHCI_CMD_FGR (1 << 4) |
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#define UHCI_CMD_EGSM (1 << 3) |
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#define UHCI_CMD_GRESET (1 << 2) |
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#define UHCI_CMD_HCRESET (1 << 1) |
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#define UHCI_CMD_RS (1 << 0) |
41 |
|
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#define UHCI_STS_HCHALTED (1 << 5) |
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#define UHCI_STS_HCPERR (1 << 4) |
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#define UHCI_STS_HSERR (1 << 3) |
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#define UHCI_STS_RD (1 << 2) |
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#define UHCI_STS_USBERR (1 << 1) |
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#define UHCI_STS_USBINT (1 << 0) |
48 |
|
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#define TD_CTRL_SPD (1 << 29) |
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#define TD_CTRL_ERROR_SHIFT 27 |
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#define TD_CTRL_IOS (1 << 25) |
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#define TD_CTRL_IOC (1 << 24) |
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#define TD_CTRL_ACTIVE (1 << 23) |
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#define TD_CTRL_STALL (1 << 22) |
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#define TD_CTRL_BABBLE (1 << 20) |
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#define TD_CTRL_NAK (1 << 19) |
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#define TD_CTRL_TIMEOUT (1 << 18) |
58 |
|
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#define UHCI_PORT_RESET (1 << 9) |
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#define UHCI_PORT_LSDA (1 << 8) |
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#define UHCI_PORT_ENC (1 << 3) |
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#define UHCI_PORT_EN (1 << 2) |
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#define UHCI_PORT_CSC (1 << 1) |
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#define UHCI_PORT_CCS (1 << 0) |
65 |
|
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#define FRAME_TIMER_FREQ 1000 |
67 |
|
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#define FRAME_MAX_LOOPS 100 |
69 |
|
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#define NB_PORTS 2 |
71 |
|
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#ifdef DEBUG
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#define dprintf printf
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const char *pid2str(int pid) |
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{ |
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switch (pid) {
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case USB_TOKEN_SETUP: return "SETUP"; |
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case USB_TOKEN_IN: return "IN"; |
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case USB_TOKEN_OUT: return "OUT"; |
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} |
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return "?"; |
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} |
84 |
|
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#else
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#define dprintf(...)
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#endif
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#ifdef DEBUG_DUMP_DATA
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static void dump_data(const uint8_t *data, int len) |
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{ |
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int i;
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printf("uhci: data: ");
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for(i = 0; i < len; i++) |
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printf(" %02x", data[i]);
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printf("\n");
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} |
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#else
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static void dump_data(const uint8_t *data, int len) {} |
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#endif
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/*
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* Pending async transaction.
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* 'packet' must be the first field because completion
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* handler does "(UHCIAsync *) pkt" cast.
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*/
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typedef struct UHCIAsync { |
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USBPacket packet; |
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struct UHCIAsync *next;
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uint32_t td; |
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uint32_t token; |
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int8_t valid; |
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uint8_t done; |
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uint8_t buffer[2048];
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} UHCIAsync; |
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typedef struct UHCIPort { |
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USBPort port; |
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uint16_t ctrl; |
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} UHCIPort; |
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typedef struct UHCIState { |
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PCIDevice dev; |
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uint16_t cmd; /* cmd register */
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uint16_t status; |
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uint16_t intr; /* interrupt enable register */
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uint16_t frnum; /* frame number */
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uint32_t fl_base_addr; /* frame list base address */
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uint8_t sof_timing; |
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uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
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QEMUTimer *frame_timer; |
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UHCIPort ports[NB_PORTS]; |
134 |
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/* Interrupts that should be raised at the end of the current frame. */
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uint32_t pending_int_mask; |
137 |
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/* Active packets */
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UHCIAsync *async_pending; |
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UHCIAsync *async_pool; |
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} UHCIState; |
142 |
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typedef struct UHCI_TD { |
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uint32_t link; |
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uint32_t ctrl; /* see TD_CTRL_xxx */
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uint32_t token; |
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uint32_t buffer; |
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} UHCI_TD; |
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typedef struct UHCI_QH { |
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uint32_t link; |
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uint32_t el_link; |
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} UHCI_QH; |
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static UHCIAsync *uhci_async_alloc(UHCIState *s)
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{ |
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UHCIAsync *async = qemu_malloc(sizeof(UHCIAsync));
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memset(&async->packet, 0, sizeof(async->packet)); |
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async->valid = 0;
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async->td = 0;
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async->token = 0;
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async->done = 0;
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async->next = NULL;
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return async;
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} |
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static void uhci_async_free(UHCIState *s, UHCIAsync *async) |
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{ |
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qemu_free(async); |
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} |
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static void uhci_async_link(UHCIState *s, UHCIAsync *async) |
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{ |
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async->next = s->async_pending; |
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s->async_pending = async; |
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} |
179 |
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static void uhci_async_unlink(UHCIState *s, UHCIAsync *async) |
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{ |
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UHCIAsync *curr = s->async_pending; |
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UHCIAsync **prev = &s->async_pending; |
184 |
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while (curr) {
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if (curr == async) {
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*prev = curr->next; |
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return;
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} |
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prev = &curr->next; |
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curr = curr->next; |
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} |
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} |
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static void uhci_async_cancel(UHCIState *s, UHCIAsync *async) |
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{ |
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dprintf("uhci: cancel td 0x%x token 0x%x done %u\n",
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async->td, async->token, async->done); |
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if (!async->done)
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usb_cancel_packet(&async->packet); |
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uhci_async_free(s, async); |
204 |
} |
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/*
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* Mark all outstanding async packets as invalid.
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* This is used for canceling them when TDs are removed by the HCD.
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*/
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static UHCIAsync *uhci_async_validate_begin(UHCIState *s)
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{ |
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UHCIAsync *async = s->async_pending; |
213 |
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while (async) {
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async->valid--; |
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async = async->next; |
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} |
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return NULL; |
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} |
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/*
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* Cancel async packets that are no longer valid
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*/
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static void uhci_async_validate_end(UHCIState *s) |
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{ |
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UHCIAsync *curr = s->async_pending; |
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UHCIAsync **prev = &s->async_pending; |
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UHCIAsync *next; |
229 |
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while (curr) {
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if (curr->valid > 0) { |
232 |
prev = &curr->next; |
233 |
curr = curr->next; |
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continue;
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} |
236 |
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next = curr->next; |
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/* Unlink */
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*prev = next; |
241 |
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uhci_async_cancel(s, curr); |
243 |
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curr = next; |
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} |
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} |
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static void uhci_async_cancel_all(UHCIState *s) |
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{ |
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UHCIAsync *curr = s->async_pending; |
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UHCIAsync *next; |
252 |
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while (curr) {
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next = curr->next; |
255 |
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uhci_async_cancel(s, curr); |
257 |
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curr = next; |
259 |
} |
260 |
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s->async_pending = NULL;
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} |
263 |
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static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, uint32_t token)
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{ |
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UHCIAsync *async = s->async_pending; |
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UHCIAsync *match = NULL;
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int count = 0; |
269 |
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/*
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* We're looking for the best match here. ie both td addr and token.
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* Otherwise we return last good match. ie just token.
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* It's ok to match just token because it identifies the transaction
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* rather well, token includes: device addr, endpoint, size, etc.
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*
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* Also since we queue async transactions in reverse order by returning
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* last good match we restores the order.
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*
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* It's expected that we wont have a ton of outstanding transactions.
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* If we ever do we'd want to optimize this algorithm.
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*/
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while (async) {
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if (async->token == token) {
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/* Good match */
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match = async; |
287 |
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if (async->td == addr) {
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/* Best match */
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break;
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} |
292 |
} |
293 |
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async = async->next; |
295 |
count++; |
296 |
} |
297 |
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if (count > 64) |
299 |
fprintf(stderr, "uhci: warning lots of async transactions\n");
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return match;
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} |
303 |
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304 |
static void uhci_attach(USBPort *port1, USBDevice *dev); |
305 |
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static void uhci_update_irq(UHCIState *s) |
307 |
{ |
308 |
int level;
|
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if (((s->status2 & 1) && (s->intr & (1 << 2))) || |
310 |
((s->status2 & 2) && (s->intr & (1 << 3))) || |
311 |
((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || |
312 |
((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || |
313 |
(s->status & UHCI_STS_HSERR) || |
314 |
(s->status & UHCI_STS_HCPERR)) { |
315 |
level = 1;
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316 |
} else {
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317 |
level = 0;
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318 |
} |
319 |
qemu_set_irq(s->dev.irq[3], level);
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320 |
} |
321 |
|
322 |
static void uhci_reset(UHCIState *s) |
323 |
{ |
324 |
uint8_t *pci_conf; |
325 |
int i;
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326 |
UHCIPort *port; |
327 |
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328 |
dprintf("uhci: full reset\n");
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329 |
|
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pci_conf = s->dev.config; |
331 |
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pci_conf[0x6a] = 0x01; /* usb clock */ |
333 |
pci_conf[0x6b] = 0x00; |
334 |
s->cmd = 0;
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s->status = 0;
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336 |
s->status2 = 0;
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337 |
s->intr = 0;
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338 |
s->fl_base_addr = 0;
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339 |
s->sof_timing = 64;
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340 |
|
341 |
for(i = 0; i < NB_PORTS; i++) { |
342 |
port = &s->ports[i]; |
343 |
port->ctrl = 0x0080;
|
344 |
if (port->port.dev)
|
345 |
uhci_attach(&port->port, port->port.dev); |
346 |
} |
347 |
|
348 |
uhci_async_cancel_all(s); |
349 |
} |
350 |
|
351 |
static void uhci_save(QEMUFile *f, void *opaque) |
352 |
{ |
353 |
UHCIState *s = opaque; |
354 |
uint8_t num_ports = NB_PORTS; |
355 |
int i;
|
356 |
|
357 |
uhci_async_cancel_all(s); |
358 |
|
359 |
pci_device_save(&s->dev, f); |
360 |
|
361 |
qemu_put_8s(f, &num_ports); |
362 |
for (i = 0; i < num_ports; ++i) |
363 |
qemu_put_be16s(f, &s->ports[i].ctrl); |
364 |
qemu_put_be16s(f, &s->cmd); |
365 |
qemu_put_be16s(f, &s->status); |
366 |
qemu_put_be16s(f, &s->intr); |
367 |
qemu_put_be16s(f, &s->frnum); |
368 |
qemu_put_be32s(f, &s->fl_base_addr); |
369 |
qemu_put_8s(f, &s->sof_timing); |
370 |
qemu_put_8s(f, &s->status2); |
371 |
qemu_put_timer(f, s->frame_timer); |
372 |
} |
373 |
|
374 |
static int uhci_load(QEMUFile *f, void *opaque, int version_id) |
375 |
{ |
376 |
UHCIState *s = opaque; |
377 |
uint8_t num_ports; |
378 |
int i, ret;
|
379 |
|
380 |
if (version_id > 1) |
381 |
return -EINVAL;
|
382 |
|
383 |
ret = pci_device_load(&s->dev, f); |
384 |
if (ret < 0) |
385 |
return ret;
|
386 |
|
387 |
qemu_get_8s(f, &num_ports); |
388 |
if (num_ports != NB_PORTS)
|
389 |
return -EINVAL;
|
390 |
|
391 |
for (i = 0; i < num_ports; ++i) |
392 |
qemu_get_be16s(f, &s->ports[i].ctrl); |
393 |
qemu_get_be16s(f, &s->cmd); |
394 |
qemu_get_be16s(f, &s->status); |
395 |
qemu_get_be16s(f, &s->intr); |
396 |
qemu_get_be16s(f, &s->frnum); |
397 |
qemu_get_be32s(f, &s->fl_base_addr); |
398 |
qemu_get_8s(f, &s->sof_timing); |
399 |
qemu_get_8s(f, &s->status2); |
400 |
qemu_get_timer(f, s->frame_timer); |
401 |
|
402 |
return 0; |
403 |
} |
404 |
|
405 |
static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
406 |
{ |
407 |
UHCIState *s = opaque; |
408 |
|
409 |
addr &= 0x1f;
|
410 |
switch(addr) {
|
411 |
case 0x0c: |
412 |
s->sof_timing = val; |
413 |
break;
|
414 |
} |
415 |
} |
416 |
|
417 |
static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) |
418 |
{ |
419 |
UHCIState *s = opaque; |
420 |
uint32_t val; |
421 |
|
422 |
addr &= 0x1f;
|
423 |
switch(addr) {
|
424 |
case 0x0c: |
425 |
val = s->sof_timing; |
426 |
break;
|
427 |
default:
|
428 |
val = 0xff;
|
429 |
break;
|
430 |
} |
431 |
return val;
|
432 |
} |
433 |
|
434 |
static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
435 |
{ |
436 |
UHCIState *s = opaque; |
437 |
|
438 |
addr &= 0x1f;
|
439 |
dprintf("uhci: writew port=0x%04x val=0x%04x\n", addr, val);
|
440 |
|
441 |
switch(addr) {
|
442 |
case 0x00: |
443 |
if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
|
444 |
/* start frame processing */
|
445 |
qemu_mod_timer(s->frame_timer, qemu_get_clock(vm_clock)); |
446 |
s->status &= ~UHCI_STS_HCHALTED; |
447 |
} else if (!(val & UHCI_CMD_RS)) { |
448 |
s->status |= UHCI_STS_HCHALTED; |
449 |
} |
450 |
if (val & UHCI_CMD_GRESET) {
|
451 |
UHCIPort *port; |
452 |
USBDevice *dev; |
453 |
int i;
|
454 |
|
455 |
/* send reset on the USB bus */
|
456 |
for(i = 0; i < NB_PORTS; i++) { |
457 |
port = &s->ports[i]; |
458 |
dev = port->port.dev; |
459 |
if (dev) {
|
460 |
usb_send_msg(dev, USB_MSG_RESET); |
461 |
} |
462 |
} |
463 |
uhci_reset(s); |
464 |
return;
|
465 |
} |
466 |
if (val & UHCI_CMD_HCRESET) {
|
467 |
uhci_reset(s); |
468 |
return;
|
469 |
} |
470 |
s->cmd = val; |
471 |
break;
|
472 |
case 0x02: |
473 |
s->status &= ~val; |
474 |
/* XXX: the chip spec is not coherent, so we add a hidden
|
475 |
register to distinguish between IOC and SPD */
|
476 |
if (val & UHCI_STS_USBINT)
|
477 |
s->status2 = 0;
|
478 |
uhci_update_irq(s); |
479 |
break;
|
480 |
case 0x04: |
481 |
s->intr = val; |
482 |
uhci_update_irq(s); |
483 |
break;
|
484 |
case 0x06: |
485 |
if (s->status & UHCI_STS_HCHALTED)
|
486 |
s->frnum = val & 0x7ff;
|
487 |
break;
|
488 |
case 0x10 ... 0x1f: |
489 |
{ |
490 |
UHCIPort *port; |
491 |
USBDevice *dev; |
492 |
int n;
|
493 |
|
494 |
n = (addr >> 1) & 7; |
495 |
if (n >= NB_PORTS)
|
496 |
return;
|
497 |
port = &s->ports[n]; |
498 |
dev = port->port.dev; |
499 |
if (dev) {
|
500 |
/* port reset */
|
501 |
if ( (val & UHCI_PORT_RESET) &&
|
502 |
!(port->ctrl & UHCI_PORT_RESET) ) { |
503 |
usb_send_msg(dev, USB_MSG_RESET); |
504 |
} |
505 |
} |
506 |
port->ctrl = (port->ctrl & 0x01fb) | (val & ~0x01fb); |
507 |
/* some bits are reset when a '1' is written to them */
|
508 |
port->ctrl &= ~(val & 0x000a);
|
509 |
} |
510 |
break;
|
511 |
} |
512 |
} |
513 |
|
514 |
static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) |
515 |
{ |
516 |
UHCIState *s = opaque; |
517 |
uint32_t val; |
518 |
|
519 |
addr &= 0x1f;
|
520 |
switch(addr) {
|
521 |
case 0x00: |
522 |
val = s->cmd; |
523 |
break;
|
524 |
case 0x02: |
525 |
val = s->status; |
526 |
break;
|
527 |
case 0x04: |
528 |
val = s->intr; |
529 |
break;
|
530 |
case 0x06: |
531 |
val = s->frnum; |
532 |
break;
|
533 |
case 0x10 ... 0x1f: |
534 |
{ |
535 |
UHCIPort *port; |
536 |
int n;
|
537 |
n = (addr >> 1) & 7; |
538 |
if (n >= NB_PORTS)
|
539 |
goto read_default;
|
540 |
port = &s->ports[n]; |
541 |
val = port->ctrl; |
542 |
} |
543 |
break;
|
544 |
default:
|
545 |
read_default:
|
546 |
val = 0xff7f; /* disabled port */ |
547 |
break;
|
548 |
} |
549 |
|
550 |
dprintf("uhci: readw port=0x%04x val=0x%04x\n", addr, val);
|
551 |
|
552 |
return val;
|
553 |
} |
554 |
|
555 |
static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
556 |
{ |
557 |
UHCIState *s = opaque; |
558 |
|
559 |
addr &= 0x1f;
|
560 |
dprintf("uhci: writel port=0x%04x val=0x%08x\n", addr, val);
|
561 |
|
562 |
switch(addr) {
|
563 |
case 0x08: |
564 |
s->fl_base_addr = val & ~0xfff;
|
565 |
break;
|
566 |
} |
567 |
} |
568 |
|
569 |
static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) |
570 |
{ |
571 |
UHCIState *s = opaque; |
572 |
uint32_t val; |
573 |
|
574 |
addr &= 0x1f;
|
575 |
switch(addr) {
|
576 |
case 0x08: |
577 |
val = s->fl_base_addr; |
578 |
break;
|
579 |
default:
|
580 |
val = 0xffffffff;
|
581 |
break;
|
582 |
} |
583 |
return val;
|
584 |
} |
585 |
|
586 |
/* signal resume if controller suspended */
|
587 |
static void uhci_resume (void *opaque) |
588 |
{ |
589 |
UHCIState *s = (UHCIState *)opaque; |
590 |
|
591 |
if (!s)
|
592 |
return;
|
593 |
|
594 |
if (s->cmd & UHCI_CMD_EGSM) {
|
595 |
s->cmd |= UHCI_CMD_FGR; |
596 |
s->status |= UHCI_STS_RD; |
597 |
uhci_update_irq(s); |
598 |
} |
599 |
} |
600 |
|
601 |
static void uhci_attach(USBPort *port1, USBDevice *dev) |
602 |
{ |
603 |
UHCIState *s = port1->opaque; |
604 |
UHCIPort *port = &s->ports[port1->index]; |
605 |
|
606 |
if (dev) {
|
607 |
if (port->port.dev) {
|
608 |
usb_attach(port1, NULL);
|
609 |
} |
610 |
/* set connect status */
|
611 |
port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; |
612 |
|
613 |
/* update speed */
|
614 |
if (dev->speed == USB_SPEED_LOW)
|
615 |
port->ctrl |= UHCI_PORT_LSDA; |
616 |
else
|
617 |
port->ctrl &= ~UHCI_PORT_LSDA; |
618 |
|
619 |
uhci_resume(s); |
620 |
|
621 |
port->port.dev = dev; |
622 |
/* send the attach message */
|
623 |
usb_send_msg(dev, USB_MSG_ATTACH); |
624 |
} else {
|
625 |
/* set connect status */
|
626 |
if (port->ctrl & UHCI_PORT_CCS) {
|
627 |
port->ctrl &= ~UHCI_PORT_CCS; |
628 |
port->ctrl |= UHCI_PORT_CSC; |
629 |
} |
630 |
/* disable port */
|
631 |
if (port->ctrl & UHCI_PORT_EN) {
|
632 |
port->ctrl &= ~UHCI_PORT_EN; |
633 |
port->ctrl |= UHCI_PORT_ENC; |
634 |
} |
635 |
|
636 |
uhci_resume(s); |
637 |
|
638 |
dev = port->port.dev; |
639 |
if (dev) {
|
640 |
/* send the detach message */
|
641 |
usb_send_msg(dev, USB_MSG_DETACH); |
642 |
} |
643 |
port->port.dev = NULL;
|
644 |
} |
645 |
} |
646 |
|
647 |
static int uhci_broadcast_packet(UHCIState *s, USBPacket *p) |
648 |
{ |
649 |
int i, ret;
|
650 |
|
651 |
dprintf("uhci: packet enter. pid %s addr 0x%02x ep %d len %d\n",
|
652 |
pid2str(p->pid), p->devaddr, p->devep, p->len); |
653 |
if (p->pid == USB_TOKEN_OUT || p->pid == USB_TOKEN_SETUP)
|
654 |
dump_data(p->data, p->len); |
655 |
|
656 |
ret = USB_RET_NODEV; |
657 |
for (i = 0; i < NB_PORTS && ret == USB_RET_NODEV; i++) { |
658 |
UHCIPort *port = &s->ports[i]; |
659 |
USBDevice *dev = port->port.dev; |
660 |
|
661 |
if (dev && (port->ctrl & UHCI_PORT_EN))
|
662 |
ret = dev->handle_packet(dev, p); |
663 |
} |
664 |
|
665 |
dprintf("uhci: packet exit. ret %d len %d\n", ret, p->len);
|
666 |
if (p->pid == USB_TOKEN_IN && ret > 0) |
667 |
dump_data(p->data, ret); |
668 |
|
669 |
return ret;
|
670 |
} |
671 |
|
672 |
static void uhci_async_complete(USBPacket * packet, void *opaque); |
673 |
static void uhci_process_frame(UHCIState *s); |
674 |
|
675 |
/* return -1 if fatal error (frame must be stopped)
|
676 |
0 if TD successful
|
677 |
1 if TD unsuccessful or inactive
|
678 |
*/
|
679 |
static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) |
680 |
{ |
681 |
int len = 0, max_len, err, ret; |
682 |
uint8_t pid; |
683 |
|
684 |
max_len = ((td->token >> 21) + 1) & 0x7ff; |
685 |
pid = td->token & 0xff;
|
686 |
|
687 |
ret = async->packet.len; |
688 |
|
689 |
if (td->ctrl & TD_CTRL_IOC)
|
690 |
*int_mask |= 0x01;
|
691 |
|
692 |
if (td->ctrl & TD_CTRL_IOS)
|
693 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
694 |
|
695 |
if (ret < 0) |
696 |
goto out;
|
697 |
|
698 |
len = async->packet.len; |
699 |
td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
700 |
|
701 |
/* The NAK bit may have been set by a previous frame, so clear it
|
702 |
here. The docs are somewhat unclear, but win2k relies on this
|
703 |
behavior. */
|
704 |
td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); |
705 |
|
706 |
if (pid == USB_TOKEN_IN) {
|
707 |
if (len > max_len) {
|
708 |
len = max_len; |
709 |
ret = USB_RET_BABBLE; |
710 |
goto out;
|
711 |
} |
712 |
|
713 |
if (len > 0) { |
714 |
/* write the data back */
|
715 |
cpu_physical_memory_write(td->buffer, async->buffer, len); |
716 |
} |
717 |
|
718 |
if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
|
719 |
*int_mask |= 0x02;
|
720 |
/* short packet: do not update QH */
|
721 |
dprintf("uhci: short packet. td 0x%x token 0x%x\n", async->td, async->token);
|
722 |
return 1; |
723 |
} |
724 |
} |
725 |
|
726 |
/* success */
|
727 |
return 0; |
728 |
|
729 |
out:
|
730 |
switch(ret) {
|
731 |
case USB_RET_STALL:
|
732 |
td->ctrl |= TD_CTRL_STALL; |
733 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
734 |
return 1; |
735 |
|
736 |
case USB_RET_BABBLE:
|
737 |
td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; |
738 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
739 |
/* frame interrupted */
|
740 |
return -1; |
741 |
|
742 |
case USB_RET_NAK:
|
743 |
td->ctrl |= TD_CTRL_NAK; |
744 |
if (pid == USB_TOKEN_SETUP)
|
745 |
break;
|
746 |
return 1; |
747 |
|
748 |
case USB_RET_NODEV:
|
749 |
default:
|
750 |
break;
|
751 |
} |
752 |
|
753 |
/* Retry the TD if error count is not zero */
|
754 |
|
755 |
td->ctrl |= TD_CTRL_TIMEOUT; |
756 |
err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
|
757 |
if (err != 0) { |
758 |
err--; |
759 |
if (err == 0) { |
760 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
761 |
s->status |= UHCI_STS_USBERR; |
762 |
uhci_update_irq(s); |
763 |
} |
764 |
} |
765 |
td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
|
766 |
(err << TD_CTRL_ERROR_SHIFT); |
767 |
return 1; |
768 |
} |
769 |
|
770 |
static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask) |
771 |
{ |
772 |
UHCIAsync *async; |
773 |
int len = 0, max_len; |
774 |
uint8_t pid; |
775 |
|
776 |
/* Is active ? */
|
777 |
if (!(td->ctrl & TD_CTRL_ACTIVE))
|
778 |
return 1; |
779 |
|
780 |
async = uhci_async_find_td(s, addr, td->token); |
781 |
if (async) {
|
782 |
/* Already submitted */
|
783 |
async->valid = 32;
|
784 |
|
785 |
if (!async->done)
|
786 |
return 1; |
787 |
|
788 |
uhci_async_unlink(s, async); |
789 |
goto done;
|
790 |
} |
791 |
|
792 |
/* Allocate new packet */
|
793 |
async = uhci_async_alloc(s); |
794 |
if (!async)
|
795 |
return 1; |
796 |
|
797 |
async->valid = 10;
|
798 |
async->td = addr; |
799 |
async->token = td->token; |
800 |
|
801 |
max_len = ((td->token >> 21) + 1) & 0x7ff; |
802 |
pid = td->token & 0xff;
|
803 |
|
804 |
async->packet.pid = pid; |
805 |
async->packet.devaddr = (td->token >> 8) & 0x7f; |
806 |
async->packet.devep = (td->token >> 15) & 0xf; |
807 |
async->packet.data = async->buffer; |
808 |
async->packet.len = max_len; |
809 |
async->packet.complete_cb = uhci_async_complete; |
810 |
async->packet.complete_opaque = s; |
811 |
|
812 |
switch(pid) {
|
813 |
case USB_TOKEN_OUT:
|
814 |
case USB_TOKEN_SETUP:
|
815 |
cpu_physical_memory_read(td->buffer, async->buffer, max_len); |
816 |
len = uhci_broadcast_packet(s, &async->packet); |
817 |
if (len >= 0) |
818 |
len = max_len; |
819 |
break;
|
820 |
|
821 |
case USB_TOKEN_IN:
|
822 |
len = uhci_broadcast_packet(s, &async->packet); |
823 |
break;
|
824 |
|
825 |
default:
|
826 |
/* invalid pid : frame interrupted */
|
827 |
uhci_async_free(s, async); |
828 |
s->status |= UHCI_STS_HCPERR; |
829 |
uhci_update_irq(s); |
830 |
return -1; |
831 |
} |
832 |
|
833 |
if (len == USB_RET_ASYNC) {
|
834 |
uhci_async_link(s, async); |
835 |
return 2; |
836 |
} |
837 |
|
838 |
async->packet.len = len; |
839 |
|
840 |
done:
|
841 |
len = uhci_complete_td(s, td, async, int_mask); |
842 |
uhci_async_free(s, async); |
843 |
return len;
|
844 |
} |
845 |
|
846 |
static void uhci_async_complete(USBPacket *packet, void *opaque) |
847 |
{ |
848 |
UHCIState *s = opaque; |
849 |
UHCIAsync *async = (UHCIAsync *) packet; |
850 |
|
851 |
dprintf("uhci: async complete. td 0x%x token 0x%x\n", async->td, async->token);
|
852 |
|
853 |
async->done = 1;
|
854 |
|
855 |
uhci_process_frame(s); |
856 |
} |
857 |
|
858 |
static int is_valid(uint32_t link) |
859 |
{ |
860 |
return (link & 1) == 0; |
861 |
} |
862 |
|
863 |
static int is_qh(uint32_t link) |
864 |
{ |
865 |
return (link & 2) != 0; |
866 |
} |
867 |
|
868 |
static int depth_first(uint32_t link) |
869 |
{ |
870 |
return (link & 4) != 0; |
871 |
} |
872 |
|
873 |
/* QH DB used for detecting QH loops */
|
874 |
#define UHCI_MAX_QUEUES 128 |
875 |
typedef struct { |
876 |
uint32_t addr[UHCI_MAX_QUEUES]; |
877 |
int count;
|
878 |
} QhDb; |
879 |
|
880 |
static void qhdb_reset(QhDb *db) |
881 |
{ |
882 |
db->count = 0;
|
883 |
} |
884 |
|
885 |
/* Add QH to DB. Returns 1 if already present or DB is full. */
|
886 |
static int qhdb_insert(QhDb *db, uint32_t addr) |
887 |
{ |
888 |
int i;
|
889 |
for (i = 0; i < db->count; i++) |
890 |
if (db->addr[i] == addr)
|
891 |
return 1; |
892 |
|
893 |
if (db->count >= UHCI_MAX_QUEUES)
|
894 |
return 1; |
895 |
|
896 |
db->addr[db->count++] = addr; |
897 |
return 0; |
898 |
} |
899 |
|
900 |
static void uhci_process_frame(UHCIState *s) |
901 |
{ |
902 |
uint32_t frame_addr, link, old_td_ctrl, val, int_mask; |
903 |
uint32_t curr_qh; |
904 |
int cnt, ret;
|
905 |
UHCI_TD td; |
906 |
UHCI_QH qh; |
907 |
QhDb qhdb; |
908 |
|
909 |
frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
910 |
|
911 |
dprintf("uhci: processing frame %d addr 0x%x\n" , s->frnum, frame_addr);
|
912 |
|
913 |
cpu_physical_memory_read(frame_addr, (uint8_t *)&link, 4);
|
914 |
le32_to_cpus(&link); |
915 |
|
916 |
int_mask = 0;
|
917 |
curr_qh = 0;
|
918 |
|
919 |
qhdb_reset(&qhdb); |
920 |
|
921 |
for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
|
922 |
if (is_qh(link)) {
|
923 |
/* QH */
|
924 |
|
925 |
if (qhdb_insert(&qhdb, link)) {
|
926 |
/*
|
927 |
* We're going in circles. Which is not a bug because
|
928 |
* HCD is allowed to do that as part of the BW management.
|
929 |
* In our case though it makes no sense to spin here. Sync transations
|
930 |
* are already done, and async completion handler will re-process
|
931 |
* the frame when something is ready.
|
932 |
*/
|
933 |
dprintf("uhci: detected loop. qh 0x%x\n", link);
|
934 |
break;
|
935 |
} |
936 |
|
937 |
cpu_physical_memory_read(link & ~0xf, (uint8_t *) &qh, sizeof(qh)); |
938 |
le32_to_cpus(&qh.link); |
939 |
le32_to_cpus(&qh.el_link); |
940 |
|
941 |
dprintf("uhci: QH 0x%x load. link 0x%x elink 0x%x\n",
|
942 |
link, qh.link, qh.el_link); |
943 |
|
944 |
if (!is_valid(qh.el_link)) {
|
945 |
/* QH w/o elements */
|
946 |
curr_qh = 0;
|
947 |
link = qh.link; |
948 |
} else {
|
949 |
/* QH with elements */
|
950 |
curr_qh = link; |
951 |
link = qh.el_link; |
952 |
} |
953 |
continue;
|
954 |
} |
955 |
|
956 |
/* TD */
|
957 |
cpu_physical_memory_read(link & ~0xf, (uint8_t *) &td, sizeof(td)); |
958 |
le32_to_cpus(&td.link); |
959 |
le32_to_cpus(&td.ctrl); |
960 |
le32_to_cpus(&td.token); |
961 |
le32_to_cpus(&td.buffer); |
962 |
|
963 |
dprintf("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
964 |
link, td.link, td.ctrl, td.token, curr_qh); |
965 |
|
966 |
old_td_ctrl = td.ctrl; |
967 |
ret = uhci_handle_td(s, link, &td, &int_mask); |
968 |
if (old_td_ctrl != td.ctrl) {
|
969 |
/* update the status bits of the TD */
|
970 |
val = cpu_to_le32(td.ctrl); |
971 |
cpu_physical_memory_write((link & ~0xf) + 4, |
972 |
(const uint8_t *)&val, sizeof(val)); |
973 |
} |
974 |
|
975 |
if (ret < 0) { |
976 |
/* interrupted frame */
|
977 |
break;
|
978 |
} |
979 |
|
980 |
if (ret == 2 || ret == 1) { |
981 |
dprintf("uhci: TD 0x%x %s. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
982 |
link, ret == 2 ? "pend" : "skip", |
983 |
td.link, td.ctrl, td.token, curr_qh); |
984 |
|
985 |
link = curr_qh ? qh.link : td.link; |
986 |
continue;
|
987 |
} |
988 |
|
989 |
/* completed TD */
|
990 |
|
991 |
dprintf("uhci: TD 0x%x done. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
992 |
link, td.link, td.ctrl, td.token, curr_qh); |
993 |
|
994 |
link = td.link; |
995 |
|
996 |
if (curr_qh) {
|
997 |
/* update QH element link */
|
998 |
qh.el_link = link; |
999 |
val = cpu_to_le32(qh.el_link); |
1000 |
cpu_physical_memory_write((curr_qh & ~0xf) + 4, |
1001 |
(const uint8_t *)&val, sizeof(val)); |
1002 |
|
1003 |
if (!depth_first(link)) {
|
1004 |
/* done with this QH */
|
1005 |
|
1006 |
dprintf("uhci: QH 0x%x done. link 0x%x elink 0x%x\n",
|
1007 |
curr_qh, qh.link, qh.el_link); |
1008 |
|
1009 |
curr_qh = 0;
|
1010 |
link = qh.link; |
1011 |
} |
1012 |
} |
1013 |
|
1014 |
/* go to the next entry */
|
1015 |
} |
1016 |
|
1017 |
s->pending_int_mask = int_mask; |
1018 |
} |
1019 |
|
1020 |
static void uhci_frame_timer(void *opaque) |
1021 |
{ |
1022 |
UHCIState *s = opaque; |
1023 |
int64_t expire_time; |
1024 |
|
1025 |
if (!(s->cmd & UHCI_CMD_RS)) {
|
1026 |
/* Full stop */
|
1027 |
qemu_del_timer(s->frame_timer); |
1028 |
/* set hchalted bit in status - UHCI11D 2.1.2 */
|
1029 |
s->status |= UHCI_STS_HCHALTED; |
1030 |
|
1031 |
dprintf("uhci: halted\n");
|
1032 |
return;
|
1033 |
} |
1034 |
|
1035 |
/* Complete the previous frame */
|
1036 |
if (s->pending_int_mask) {
|
1037 |
s->status2 |= s->pending_int_mask; |
1038 |
s->status |= UHCI_STS_USBINT; |
1039 |
uhci_update_irq(s); |
1040 |
} |
1041 |
|
1042 |
/* Start new frame */
|
1043 |
s->frnum = (s->frnum + 1) & 0x7ff; |
1044 |
|
1045 |
dprintf("uhci: new frame #%u\n" , s->frnum);
|
1046 |
|
1047 |
uhci_async_validate_begin(s); |
1048 |
|
1049 |
uhci_process_frame(s); |
1050 |
|
1051 |
uhci_async_validate_end(s); |
1052 |
|
1053 |
/* prepare the timer for the next frame */
|
1054 |
expire_time = qemu_get_clock(vm_clock) + |
1055 |
(ticks_per_sec / FRAME_TIMER_FREQ); |
1056 |
qemu_mod_timer(s->frame_timer, expire_time); |
1057 |
} |
1058 |
|
1059 |
static void uhci_map(PCIDevice *pci_dev, int region_num, |
1060 |
uint32_t addr, uint32_t size, int type)
|
1061 |
{ |
1062 |
UHCIState *s = (UHCIState *)pci_dev; |
1063 |
|
1064 |
register_ioport_write(addr, 32, 2, uhci_ioport_writew, s); |
1065 |
register_ioport_read(addr, 32, 2, uhci_ioport_readw, s); |
1066 |
register_ioport_write(addr, 32, 4, uhci_ioport_writel, s); |
1067 |
register_ioport_read(addr, 32, 4, uhci_ioport_readl, s); |
1068 |
register_ioport_write(addr, 32, 1, uhci_ioport_writeb, s); |
1069 |
register_ioport_read(addr, 32, 1, uhci_ioport_readb, s); |
1070 |
} |
1071 |
|
1072 |
void usb_uhci_piix3_init(PCIBus *bus, int devfn) |
1073 |
{ |
1074 |
UHCIState *s; |
1075 |
uint8_t *pci_conf; |
1076 |
int i;
|
1077 |
|
1078 |
s = (UHCIState *)pci_register_device(bus, |
1079 |
"USB-UHCI", sizeof(UHCIState), |
1080 |
devfn, NULL, NULL); |
1081 |
pci_conf = s->dev.config; |
1082 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
1083 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_2); |
1084 |
pci_conf[0x08] = 0x01; // revision number |
1085 |
pci_conf[0x09] = 0x00; |
1086 |
pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB); |
1087 |
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
1088 |
pci_conf[0x3d] = 4; // interrupt pin 3 |
1089 |
pci_conf[0x60] = 0x10; // release number |
1090 |
|
1091 |
for(i = 0; i < NB_PORTS; i++) { |
1092 |
qemu_register_usb_port(&s->ports[i].port, s, i, uhci_attach); |
1093 |
} |
1094 |
s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s); |
1095 |
|
1096 |
uhci_reset(s); |
1097 |
|
1098 |
/* Use region 4 for consistency with real hardware. BSD guests seem
|
1099 |
to rely on this. */
|
1100 |
pci_register_io_region(&s->dev, 4, 0x20, |
1101 |
PCI_ADDRESS_SPACE_IO, uhci_map); |
1102 |
|
1103 |
register_savevm("uhci", 0, 1, uhci_save, uhci_load, s); |
1104 |
} |
1105 |
|
1106 |
void usb_uhci_piix4_init(PCIBus *bus, int devfn) |
1107 |
{ |
1108 |
UHCIState *s; |
1109 |
uint8_t *pci_conf; |
1110 |
int i;
|
1111 |
|
1112 |
s = (UHCIState *)pci_register_device(bus, |
1113 |
"USB-UHCI", sizeof(UHCIState), |
1114 |
devfn, NULL, NULL); |
1115 |
pci_conf = s->dev.config; |
1116 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
1117 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_2); |
1118 |
pci_conf[0x08] = 0x01; // revision number |
1119 |
pci_conf[0x09] = 0x00; |
1120 |
pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB); |
1121 |
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
1122 |
pci_conf[0x3d] = 4; // interrupt pin 3 |
1123 |
pci_conf[0x60] = 0x10; // release number |
1124 |
|
1125 |
for(i = 0; i < NB_PORTS; i++) { |
1126 |
qemu_register_usb_port(&s->ports[i].port, s, i, uhci_attach); |
1127 |
} |
1128 |
s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s); |
1129 |
|
1130 |
uhci_reset(s); |
1131 |
|
1132 |
/* Use region 4 for consistency with real hardware. BSD guests seem
|
1133 |
to rely on this. */
|
1134 |
pci_register_io_region(&s->dev, 4, 0x20, |
1135 |
PCI_ADDRESS_SPACE_IO, uhci_map); |
1136 |
|
1137 |
register_savevm("uhci", 0, 1, uhci_save, uhci_load, s); |
1138 |
} |