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/*
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 * Device model for Cadence UART
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 *
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 * Copyright (c) 2010 Xilinx Inc.
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 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
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 * Copyright (c) 2012 PetaLogix Pty Ltd.
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 * Written by Haibing Ma
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 *            M.Habib
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License
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 * as published by the Free Software Foundation; either version
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 * 2 of the License, or (at your option) any later version.
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 *
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 * You should have received a copy of the GNU General Public License along
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 * with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "sysbus.h"
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#include "qemu-char.h"
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#include "qemu-timer.h"
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#ifdef CADENCE_UART_ERR_DEBUG
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#define DB_PRINT(...) do { \
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    fprintf(stderr,  ": %s: ", __func__); \
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    fprintf(stderr, ## __VA_ARGS__); \
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    } while (0);
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#else
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    #define DB_PRINT(...)
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#endif
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#define UART_SR_INTR_RTRIG     0x00000001
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#define UART_SR_INTR_REMPTY    0x00000002
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#define UART_SR_INTR_RFUL      0x00000004
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#define UART_SR_INTR_TEMPTY    0x00000008
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#define UART_SR_INTR_TFUL      0x00000010
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/* bits fields in CSR that correlate to CISR. If any of these bits are set in
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 * SR, then the same bit in CISR is set high too */
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#define UART_SR_TO_CISR_MASK   0x0000001F
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#define UART_INTR_ROVR         0x00000020
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#define UART_INTR_FRAME        0x00000040
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#define UART_INTR_PARE         0x00000080
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#define UART_INTR_TIMEOUT      0x00000100
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#define UART_INTR_DMSI         0x00000200
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#define UART_SR_RACTIVE    0x00000400
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#define UART_SR_TACTIVE    0x00000800
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#define UART_SR_FDELT      0x00001000
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#define UART_CR_RXRST       0x00000001
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#define UART_CR_TXRST       0x00000002
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#define UART_CR_RX_EN       0x00000004
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#define UART_CR_RX_DIS      0x00000008
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#define UART_CR_TX_EN       0x00000010
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#define UART_CR_TX_DIS      0x00000020
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#define UART_CR_RST_TO      0x00000040
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#define UART_CR_STARTBRK    0x00000080
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#define UART_CR_STOPBRK     0x00000100
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#define UART_MR_CLKS            0x00000001
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#define UART_MR_CHRL            0x00000006
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#define UART_MR_CHRL_SH         1
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#define UART_MR_PAR             0x00000038
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#define UART_MR_PAR_SH          3
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#define UART_MR_NBSTOP          0x000000C0
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#define UART_MR_NBSTOP_SH       6
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#define UART_MR_CHMODE          0x00000300
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#define UART_MR_CHMODE_SH       8
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#define UART_MR_UCLKEN          0x00000400
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#define UART_MR_IRMODE          0x00000800
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#define UART_DATA_BITS_6       (0x3 << UART_MR_CHRL_SH)
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#define UART_DATA_BITS_7       (0x2 << UART_MR_CHRL_SH)
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#define UART_PARITY_ODD        (0x1 << UART_MR_PAR_SH)
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#define UART_PARITY_EVEN       (0x0 << UART_MR_PAR_SH)
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#define UART_STOP_BITS_1       (0x3 << UART_MR_NBSTOP_SH)
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#define UART_STOP_BITS_2       (0x2 << UART_MR_NBSTOP_SH)
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#define NORMAL_MODE            (0x0 << UART_MR_CHMODE_SH)
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#define ECHO_MODE              (0x1 << UART_MR_CHMODE_SH)
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#define LOCAL_LOOPBACK         (0x2 << UART_MR_CHMODE_SH)
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#define REMOTE_LOOPBACK        (0x3 << UART_MR_CHMODE_SH)
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#define RX_FIFO_SIZE           16
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#define TX_FIFO_SIZE           16
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#define UART_INPUT_CLK         50000000
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#define R_CR       (0x00/4)
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#define R_MR       (0x04/4)
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#define R_IER      (0x08/4)
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#define R_IDR      (0x0C/4)
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#define R_IMR      (0x10/4)
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#define R_CISR     (0x14/4)
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#define R_BRGR     (0x18/4)
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#define R_RTOR     (0x1C/4)
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#define R_RTRIG    (0x20/4)
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#define R_MCR      (0x24/4)
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#define R_MSR      (0x28/4)
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#define R_SR       (0x2C/4)
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#define R_TX_RX    (0x30/4)
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#define R_BDIV     (0x34/4)
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#define R_FDEL     (0x38/4)
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#define R_PMIN     (0x3C/4)
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#define R_PWID     (0x40/4)
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#define R_TTRIG    (0x44/4)
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#define R_MAX (R_TTRIG + 1)
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typedef struct {
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    SysBusDevice busdev;
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    MemoryRegion iomem;
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    uint32_t r[R_MAX];
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    uint8_t r_fifo[RX_FIFO_SIZE];
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    uint32_t rx_wpos;
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    uint32_t rx_count;
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    uint64_t char_tx_time;
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    CharDriverState *chr;
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    qemu_irq irq;
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    struct QEMUTimer *fifo_trigger_handle;
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    struct QEMUTimer *tx_time_handle;
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} UartState;
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static void uart_update_status(UartState *s)
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{
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    s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
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    qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
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}
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static void fifo_trigger_update(void *opaque)
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{
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    UartState *s = (UartState *)opaque;
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    s->r[R_CISR] |= UART_INTR_TIMEOUT;
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    uart_update_status(s);
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}
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static void uart_tx_redo(UartState *s)
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{
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    uint64_t new_tx_time = qemu_get_clock_ns(vm_clock);
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    qemu_mod_timer(s->tx_time_handle, new_tx_time + s->char_tx_time);
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    s->r[R_SR] |= UART_SR_INTR_TEMPTY;
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    uart_update_status(s);
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}
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static void uart_tx_write(void *opaque)
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{
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    UartState *s = (UartState *)opaque;
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    uart_tx_redo(s);
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}
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static void uart_rx_reset(UartState *s)
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{
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    s->rx_wpos = 0;
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    s->rx_count = 0;
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    s->r[R_SR] |= UART_SR_INTR_REMPTY;
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    s->r[R_SR] &= ~UART_SR_INTR_RFUL;
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}
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static void uart_tx_reset(UartState *s)
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{
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    s->r[R_SR] |= UART_SR_INTR_TEMPTY;
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    s->r[R_SR] &= ~UART_SR_INTR_TFUL;
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}
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static void uart_send_breaks(UartState *s)
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{
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    int break_enabled = 1;
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    qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
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                               &break_enabled);
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}
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static void uart_parameters_setup(UartState *s)
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{
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    QEMUSerialSetParams ssp;
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    unsigned int baud_rate, packet_size;
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    baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
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            UART_INPUT_CLK / 8 : UART_INPUT_CLK;
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    ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
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    packet_size = 1;
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    switch (s->r[R_MR] & UART_MR_PAR) {
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    case UART_PARITY_EVEN:
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        ssp.parity = 'E';
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        packet_size++;
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        break;
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    case UART_PARITY_ODD:
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        ssp.parity = 'O';
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        packet_size++;
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        break;
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    default:
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        ssp.parity = 'N';
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        break;
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    }
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    switch (s->r[R_MR] & UART_MR_CHRL) {
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    case UART_DATA_BITS_6:
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        ssp.data_bits = 6;
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        break;
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    case UART_DATA_BITS_7:
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        ssp.data_bits = 7;
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        break;
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    default:
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        ssp.data_bits = 8;
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        break;
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    }
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    switch (s->r[R_MR] & UART_MR_NBSTOP) {
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    case UART_STOP_BITS_1:
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        ssp.stop_bits = 1;
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        break;
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    default:
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        ssp.stop_bits = 2;
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        break;
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    }
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    packet_size += ssp.data_bits + ssp.stop_bits;
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    s->char_tx_time = (get_ticks_per_sec() / ssp.speed) * packet_size;
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    qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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}
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static int uart_can_receive(void *opaque)
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{
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    UartState *s = (UartState *)opaque;
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    return RX_FIFO_SIZE - s->rx_count;
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}
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static void uart_ctrl_update(UartState *s)
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{
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    if (s->r[R_CR] & UART_CR_TXRST) {
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        uart_tx_reset(s);
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    }
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    if (s->r[R_CR] & UART_CR_RXRST) {
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        uart_rx_reset(s);
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    }
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    s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
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    if ((s->r[R_CR] & UART_CR_TX_EN) && !(s->r[R_CR] & UART_CR_TX_DIS)) {
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            uart_tx_redo(s);
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    }
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    if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
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        uart_send_breaks(s);
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    }
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}
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static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
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{
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    UartState *s = (UartState *)opaque;
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    uint64_t new_rx_time = qemu_get_clock_ns(vm_clock);
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    int i;
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    if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
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        return;
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    }
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    s->r[R_SR] &= ~UART_SR_INTR_REMPTY;
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    if (s->rx_count == RX_FIFO_SIZE) {
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        s->r[R_CISR] |= UART_INTR_ROVR;
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    } else {
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        for (i = 0; i < size; i++) {
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            s->r_fifo[s->rx_wpos] = buf[i];
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            s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE;
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            s->rx_count++;
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            if (s->rx_count == RX_FIFO_SIZE) {
279 35548b06 Peter A. G. Crosthwaite
                s->r[R_SR] |= UART_SR_INTR_RFUL;
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                break;
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            }
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283 35548b06 Peter A. G. Crosthwaite
            if (s->rx_count >= s->r[R_RTRIG]) {
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                s->r[R_SR] |= UART_SR_INTR_RTRIG;
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            }
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        }
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        qemu_mod_timer(s->fifo_trigger_handle, new_rx_time +
288 35548b06 Peter A. G. Crosthwaite
                                                (s->char_tx_time * 4));
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    }
290 35548b06 Peter A. G. Crosthwaite
    uart_update_status(s);
291 35548b06 Peter A. G. Crosthwaite
}
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static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size)
294 35548b06 Peter A. G. Crosthwaite
{
295 35548b06 Peter A. G. Crosthwaite
    if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
296 35548b06 Peter A. G. Crosthwaite
        return;
297 35548b06 Peter A. G. Crosthwaite
    }
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299 35548b06 Peter A. G. Crosthwaite
    while (size) {
300 35548b06 Peter A. G. Crosthwaite
        size -= qemu_chr_fe_write(s->chr, buf, size);
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    }
302 35548b06 Peter A. G. Crosthwaite
}
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static void uart_receive(void *opaque, const uint8_t *buf, int size)
305 35548b06 Peter A. G. Crosthwaite
{
306 35548b06 Peter A. G. Crosthwaite
    UartState *s = (UartState *)opaque;
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    uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
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309 35548b06 Peter A. G. Crosthwaite
    if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
310 35548b06 Peter A. G. Crosthwaite
        uart_write_rx_fifo(opaque, buf, size);
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    }
312 35548b06 Peter A. G. Crosthwaite
    if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
313 35548b06 Peter A. G. Crosthwaite
        uart_write_tx_fifo(s, buf, size);
314 35548b06 Peter A. G. Crosthwaite
    }
315 35548b06 Peter A. G. Crosthwaite
}
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317 35548b06 Peter A. G. Crosthwaite
static void uart_event(void *opaque, int event)
318 35548b06 Peter A. G. Crosthwaite
{
319 35548b06 Peter A. G. Crosthwaite
    UartState *s = (UartState *)opaque;
320 35548b06 Peter A. G. Crosthwaite
    uint8_t buf = '\0';
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322 35548b06 Peter A. G. Crosthwaite
    if (event == CHR_EVENT_BREAK) {
323 35548b06 Peter A. G. Crosthwaite
        uart_write_rx_fifo(opaque, &buf, 1);
324 35548b06 Peter A. G. Crosthwaite
    }
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326 35548b06 Peter A. G. Crosthwaite
    uart_update_status(s);
327 35548b06 Peter A. G. Crosthwaite
}
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329 35548b06 Peter A. G. Crosthwaite
static void uart_read_rx_fifo(UartState *s, uint32_t *c)
330 35548b06 Peter A. G. Crosthwaite
{
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    if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
332 35548b06 Peter A. G. Crosthwaite
        return;
333 35548b06 Peter A. G. Crosthwaite
    }
334 35548b06 Peter A. G. Crosthwaite
335 35548b06 Peter A. G. Crosthwaite
    s->r[R_SR] &= ~UART_SR_INTR_RFUL;
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337 35548b06 Peter A. G. Crosthwaite
    if (s->rx_count) {
338 35548b06 Peter A. G. Crosthwaite
        uint32_t rx_rpos =
339 35548b06 Peter A. G. Crosthwaite
                (RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE;
340 35548b06 Peter A. G. Crosthwaite
        *c = s->r_fifo[rx_rpos];
341 35548b06 Peter A. G. Crosthwaite
        s->rx_count--;
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343 35548b06 Peter A. G. Crosthwaite
        if (!s->rx_count) {
344 35548b06 Peter A. G. Crosthwaite
            s->r[R_SR] |= UART_SR_INTR_REMPTY;
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        }
346 35548b06 Peter A. G. Crosthwaite
    } else {
347 35548b06 Peter A. G. Crosthwaite
        *c = 0;
348 35548b06 Peter A. G. Crosthwaite
        s->r[R_SR] |= UART_SR_INTR_REMPTY;
349 35548b06 Peter A. G. Crosthwaite
    }
350 35548b06 Peter A. G. Crosthwaite
351 35548b06 Peter A. G. Crosthwaite
    if (s->rx_count < s->r[R_RTRIG]) {
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        s->r[R_SR] &= ~UART_SR_INTR_RTRIG;
353 35548b06 Peter A. G. Crosthwaite
    }
354 35548b06 Peter A. G. Crosthwaite
    uart_update_status(s);
355 35548b06 Peter A. G. Crosthwaite
}
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357 35548b06 Peter A. G. Crosthwaite
static void uart_write(void *opaque, target_phys_addr_t offset,
358 35548b06 Peter A. G. Crosthwaite
                          uint64_t value, unsigned size)
359 35548b06 Peter A. G. Crosthwaite
{
360 35548b06 Peter A. G. Crosthwaite
    UartState *s = (UartState *)opaque;
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362 35548b06 Peter A. G. Crosthwaite
    DB_PRINT(" offset:%x data:%08x\n", offset, (unsigned)value);
363 35548b06 Peter A. G. Crosthwaite
    offset >>= 2;
364 35548b06 Peter A. G. Crosthwaite
    switch (offset) {
365 35548b06 Peter A. G. Crosthwaite
    case R_IER: /* ier (wts imr) */
366 35548b06 Peter A. G. Crosthwaite
        s->r[R_IMR] |= value;
367 35548b06 Peter A. G. Crosthwaite
        break;
368 35548b06 Peter A. G. Crosthwaite
    case R_IDR: /* idr (wtc imr) */
369 35548b06 Peter A. G. Crosthwaite
        s->r[R_IMR] &= ~value;
370 35548b06 Peter A. G. Crosthwaite
        break;
371 35548b06 Peter A. G. Crosthwaite
    case R_IMR: /* imr (read only) */
372 35548b06 Peter A. G. Crosthwaite
        break;
373 35548b06 Peter A. G. Crosthwaite
    case R_CISR: /* cisr (wtc) */
374 35548b06 Peter A. G. Crosthwaite
        s->r[R_CISR] &= ~value;
375 35548b06 Peter A. G. Crosthwaite
        break;
376 35548b06 Peter A. G. Crosthwaite
    case R_TX_RX: /* UARTDR */
377 35548b06 Peter A. G. Crosthwaite
        switch (s->r[R_MR] & UART_MR_CHMODE) {
378 35548b06 Peter A. G. Crosthwaite
        case NORMAL_MODE:
379 35548b06 Peter A. G. Crosthwaite
            uart_write_tx_fifo(s, (uint8_t *) &value, 1);
380 35548b06 Peter A. G. Crosthwaite
            break;
381 35548b06 Peter A. G. Crosthwaite
        case LOCAL_LOOPBACK:
382 35548b06 Peter A. G. Crosthwaite
            uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
383 35548b06 Peter A. G. Crosthwaite
            break;
384 35548b06 Peter A. G. Crosthwaite
        }
385 35548b06 Peter A. G. Crosthwaite
        break;
386 35548b06 Peter A. G. Crosthwaite
    default:
387 35548b06 Peter A. G. Crosthwaite
        s->r[offset] = value;
388 35548b06 Peter A. G. Crosthwaite
    }
389 35548b06 Peter A. G. Crosthwaite
390 35548b06 Peter A. G. Crosthwaite
    switch (offset) {
391 35548b06 Peter A. G. Crosthwaite
    case R_CR:
392 35548b06 Peter A. G. Crosthwaite
        uart_ctrl_update(s);
393 35548b06 Peter A. G. Crosthwaite
        break;
394 35548b06 Peter A. G. Crosthwaite
    case R_MR:
395 35548b06 Peter A. G. Crosthwaite
        uart_parameters_setup(s);
396 35548b06 Peter A. G. Crosthwaite
        break;
397 35548b06 Peter A. G. Crosthwaite
    }
398 35548b06 Peter A. G. Crosthwaite
}
399 35548b06 Peter A. G. Crosthwaite
400 35548b06 Peter A. G. Crosthwaite
static uint64_t uart_read(void *opaque, target_phys_addr_t offset,
401 35548b06 Peter A. G. Crosthwaite
        unsigned size)
402 35548b06 Peter A. G. Crosthwaite
{
403 35548b06 Peter A. G. Crosthwaite
    UartState *s = (UartState *)opaque;
404 35548b06 Peter A. G. Crosthwaite
    uint32_t c = 0;
405 35548b06 Peter A. G. Crosthwaite
406 35548b06 Peter A. G. Crosthwaite
    offset >>= 2;
407 35548b06 Peter A. G. Crosthwaite
    if (offset > R_MAX) {
408 35548b06 Peter A. G. Crosthwaite
        return 0;
409 35548b06 Peter A. G. Crosthwaite
    } else if (offset == R_TX_RX) {
410 35548b06 Peter A. G. Crosthwaite
        uart_read_rx_fifo(s, &c);
411 35548b06 Peter A. G. Crosthwaite
        return c;
412 35548b06 Peter A. G. Crosthwaite
    }
413 35548b06 Peter A. G. Crosthwaite
    return s->r[offset];
414 35548b06 Peter A. G. Crosthwaite
}
415 35548b06 Peter A. G. Crosthwaite
416 35548b06 Peter A. G. Crosthwaite
static const MemoryRegionOps uart_ops = {
417 35548b06 Peter A. G. Crosthwaite
    .read = uart_read,
418 35548b06 Peter A. G. Crosthwaite
    .write = uart_write,
419 35548b06 Peter A. G. Crosthwaite
    .endianness = DEVICE_NATIVE_ENDIAN,
420 35548b06 Peter A. G. Crosthwaite
};
421 35548b06 Peter A. G. Crosthwaite
422 35548b06 Peter A. G. Crosthwaite
static void cadence_uart_reset(UartState *s)
423 35548b06 Peter A. G. Crosthwaite
{
424 35548b06 Peter A. G. Crosthwaite
    s->r[R_CR] = 0x00000128;
425 35548b06 Peter A. G. Crosthwaite
    s->r[R_IMR] = 0;
426 35548b06 Peter A. G. Crosthwaite
    s->r[R_CISR] = 0;
427 35548b06 Peter A. G. Crosthwaite
    s->r[R_RTRIG] = 0x00000020;
428 35548b06 Peter A. G. Crosthwaite
    s->r[R_BRGR] = 0x0000000F;
429 35548b06 Peter A. G. Crosthwaite
    s->r[R_TTRIG] = 0x00000020;
430 35548b06 Peter A. G. Crosthwaite
431 35548b06 Peter A. G. Crosthwaite
    uart_rx_reset(s);
432 35548b06 Peter A. G. Crosthwaite
    uart_tx_reset(s);
433 35548b06 Peter A. G. Crosthwaite
434 35548b06 Peter A. G. Crosthwaite
    s->rx_count = 0;
435 35548b06 Peter A. G. Crosthwaite
    s->rx_wpos = 0;
436 35548b06 Peter A. G. Crosthwaite
}
437 35548b06 Peter A. G. Crosthwaite
438 35548b06 Peter A. G. Crosthwaite
static int cadence_uart_init(SysBusDevice *dev)
439 35548b06 Peter A. G. Crosthwaite
{
440 35548b06 Peter A. G. Crosthwaite
    UartState *s = FROM_SYSBUS(UartState, dev);
441 35548b06 Peter A. G. Crosthwaite
442 35548b06 Peter A. G. Crosthwaite
    memory_region_init_io(&s->iomem, &uart_ops, s, "uart", 0x1000);
443 35548b06 Peter A. G. Crosthwaite
    sysbus_init_mmio(dev, &s->iomem);
444 35548b06 Peter A. G. Crosthwaite
    sysbus_init_irq(dev, &s->irq);
445 35548b06 Peter A. G. Crosthwaite
446 35548b06 Peter A. G. Crosthwaite
    s->fifo_trigger_handle = qemu_new_timer_ns(vm_clock,
447 35548b06 Peter A. G. Crosthwaite
            (QEMUTimerCB *)fifo_trigger_update, s);
448 35548b06 Peter A. G. Crosthwaite
449 35548b06 Peter A. G. Crosthwaite
    s->tx_time_handle = qemu_new_timer_ns(vm_clock,
450 35548b06 Peter A. G. Crosthwaite
            (QEMUTimerCB *)uart_tx_write, s);
451 35548b06 Peter A. G. Crosthwaite
452 35548b06 Peter A. G. Crosthwaite
    s->char_tx_time = (get_ticks_per_sec() / 9600) * 10;
453 35548b06 Peter A. G. Crosthwaite
454 35548b06 Peter A. G. Crosthwaite
    s->chr = qemu_char_get_next_serial();
455 35548b06 Peter A. G. Crosthwaite
456 35548b06 Peter A. G. Crosthwaite
    cadence_uart_reset(s);
457 35548b06 Peter A. G. Crosthwaite
458 35548b06 Peter A. G. Crosthwaite
    if (s->chr) {
459 35548b06 Peter A. G. Crosthwaite
        qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
460 35548b06 Peter A. G. Crosthwaite
                              uart_event, s);
461 35548b06 Peter A. G. Crosthwaite
    }
462 35548b06 Peter A. G. Crosthwaite
463 35548b06 Peter A. G. Crosthwaite
    return 0;
464 35548b06 Peter A. G. Crosthwaite
}
465 35548b06 Peter A. G. Crosthwaite
466 35548b06 Peter A. G. Crosthwaite
static int cadence_uart_post_load(void *opaque, int version_id)
467 35548b06 Peter A. G. Crosthwaite
{
468 35548b06 Peter A. G. Crosthwaite
    UartState *s = opaque;
469 35548b06 Peter A. G. Crosthwaite
470 35548b06 Peter A. G. Crosthwaite
    uart_parameters_setup(s);
471 35548b06 Peter A. G. Crosthwaite
    uart_update_status(s);
472 35548b06 Peter A. G. Crosthwaite
    return 0;
473 35548b06 Peter A. G. Crosthwaite
}
474 35548b06 Peter A. G. Crosthwaite
475 35548b06 Peter A. G. Crosthwaite
static const VMStateDescription vmstate_cadence_uart = {
476 35548b06 Peter A. G. Crosthwaite
    .name = "cadence_uart",
477 35548b06 Peter A. G. Crosthwaite
    .version_id = 1,
478 35548b06 Peter A. G. Crosthwaite
    .minimum_version_id = 1,
479 35548b06 Peter A. G. Crosthwaite
    .minimum_version_id_old = 1,
480 35548b06 Peter A. G. Crosthwaite
    .post_load = cadence_uart_post_load,
481 35548b06 Peter A. G. Crosthwaite
    .fields = (VMStateField[]) {
482 35548b06 Peter A. G. Crosthwaite
        VMSTATE_UINT32_ARRAY(r, UartState, R_MAX),
483 35548b06 Peter A. G. Crosthwaite
        VMSTATE_UINT8_ARRAY(r_fifo, UartState, RX_FIFO_SIZE),
484 35548b06 Peter A. G. Crosthwaite
        VMSTATE_UINT32(rx_count, UartState),
485 35548b06 Peter A. G. Crosthwaite
        VMSTATE_UINT32(rx_wpos, UartState),
486 35548b06 Peter A. G. Crosthwaite
        VMSTATE_TIMER(fifo_trigger_handle, UartState),
487 35548b06 Peter A. G. Crosthwaite
        VMSTATE_TIMER(tx_time_handle, UartState),
488 35548b06 Peter A. G. Crosthwaite
        VMSTATE_END_OF_LIST()
489 35548b06 Peter A. G. Crosthwaite
    }
490 35548b06 Peter A. G. Crosthwaite
};
491 35548b06 Peter A. G. Crosthwaite
492 35548b06 Peter A. G. Crosthwaite
static void cadence_uart_class_init(ObjectClass *klass, void *data)
493 35548b06 Peter A. G. Crosthwaite
{
494 35548b06 Peter A. G. Crosthwaite
    DeviceClass *dc = DEVICE_CLASS(klass);
495 35548b06 Peter A. G. Crosthwaite
    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
496 35548b06 Peter A. G. Crosthwaite
497 35548b06 Peter A. G. Crosthwaite
    sdc->init = cadence_uart_init;
498 35548b06 Peter A. G. Crosthwaite
    dc->vmsd = &vmstate_cadence_uart;
499 35548b06 Peter A. G. Crosthwaite
}
500 35548b06 Peter A. G. Crosthwaite
501 35548b06 Peter A. G. Crosthwaite
static TypeInfo cadence_uart_info = {
502 35548b06 Peter A. G. Crosthwaite
    .name          = "cadence_uart",
503 35548b06 Peter A. G. Crosthwaite
    .parent        = TYPE_SYS_BUS_DEVICE,
504 35548b06 Peter A. G. Crosthwaite
    .instance_size = sizeof(UartState),
505 35548b06 Peter A. G. Crosthwaite
    .class_init    = cadence_uart_class_init,
506 35548b06 Peter A. G. Crosthwaite
};
507 35548b06 Peter A. G. Crosthwaite
508 35548b06 Peter A. G. Crosthwaite
static void cadence_uart_register_types(void)
509 35548b06 Peter A. G. Crosthwaite
{
510 35548b06 Peter A. G. Crosthwaite
    type_register_static(&cadence_uart_info);
511 35548b06 Peter A. G. Crosthwaite
}
512 35548b06 Peter A. G. Crosthwaite
513 35548b06 Peter A. G. Crosthwaite
type_init(cadence_uart_register_types)