Revision 4bd74661 hw/arm-misc.h

b/hw/arm-misc.h
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/* The CPU is also modeled as an interrupt controller.  */
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#define ARM_PIC_CPU_IRQ 0
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#define ARM_PIC_CPU_FIQ 1
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qemu_irq *arm_pic_init_cpu(CPUARMState *env);
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qemu_irq *arm_pic_init_cpu(ARMCPU *cpu);
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/* armv7m.c */


  		





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qemu_irq *armv7m_init(MemoryRegion *address_space_mem,


  		












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