Revision 4c4abe7c hw/usb/hcd-xhci.c

b/hw/usb/hcd-xhci.c
612 612
    return &xhci->ports[index];
613 613
}
614 614

  
615
static void xhci_irq_update(XHCIState *xhci)
615
static void xhci_intx_update(XHCIState *xhci)
616 616
{
617 617
    int level = 0;
618 618

  
619
    if (xhci->iman & IMAN_IP && xhci->iman & IMAN_IE &&
619
    if (msi_enabled(&xhci->pci_dev)) {
620
        return;
621
    }
622

  
623
    if (xhci->iman & IMAN_IP &&
624
        xhci->iman & IMAN_IE &&
620 625
        xhci->usbcmd & USBCMD_INTE) {
621 626
        level = 1;
622 627
    }
623 628

  
629
    trace_usb_xhci_irq_intx(level);
630
    qemu_set_irq(xhci->irq, level);
631
}
632

  
633
static void xhci_intr_raise(XHCIState *xhci)
634
{
635
    if (!(xhci->iman & IMAN_IP) ||
636
        !(xhci->iman & IMAN_IE)) {
637
        return;
638
    }
639

  
640
    if (!(xhci->usbcmd & USBCMD_INTE)) {
641
        return;
642
    }
643

  
624 644
    if (msi_enabled(&xhci->pci_dev)) {
625
        if (level) {
626
            trace_usb_xhci_irq_msi(0);
627
            msi_notify(&xhci->pci_dev, 0);
628
        }
629
    } else {
630
        trace_usb_xhci_irq_intx(level);
631
        qemu_set_irq(xhci->irq, level);
645
        trace_usb_xhci_irq_msi(0);
646
        msi_notify(&xhci->pci_dev, 0);
647
        return;
632 648
    }
649

  
650
    trace_usb_xhci_irq_intx(1);
651
    qemu_set_irq(xhci->irq, 1);
633 652
}
634 653

  
635 654
static inline int xhci_running(XHCIState *xhci)
......
732 751
        xhci->erdp_low |= ERDP_EHB;
733 752
        xhci->iman |= IMAN_IP;
734 753
        xhci->usbsts |= USBSTS_EINT;
735
        xhci_irq_update(xhci);
754
        xhci_intr_raise(xhci);
736 755
    }
737 756

  
738 757
    if (xhci->er_full && xhci->ev_buffer_put == xhci->ev_buffer_get) {
......
796 815
    xhci->iman |= IMAN_IP;
797 816
    xhci->usbsts |= USBSTS_EINT;
798 817

  
799
    xhci_irq_update(xhci);
818
    xhci_intr_raise(xhci);
800 819
}
801 820

  
802 821
static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
......
2479 2498
        if (val & USBCMD_HCRST) {
2480 2499
            xhci_reset(&xhci->pci_dev.qdev);
2481 2500
        }
2482
        xhci_irq_update(xhci);
2501
        xhci_intx_update(xhci);
2483 2502
        break;
2484 2503

  
2485 2504
    case 0x04: /* USBSTS */
2486 2505
        /* these bits are write-1-to-clear */
2487 2506
        xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
2488
        xhci_irq_update(xhci);
2507
        xhci_intx_update(xhci);
2489 2508
        break;
2490 2509

  
2491 2510
    case 0x14: /* DNCTRL */
......
2570 2589
        }
2571 2590
        xhci->iman &= ~IMAN_IE;
2572 2591
        xhci->iman |= val & IMAN_IE;
2573
        xhci_irq_update(xhci);
2592
        xhci_intx_update(xhci);
2574 2593
        break;
2575 2594
    case 0x24: /* IMOD */
2576 2595
        xhci->imod = val;

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