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1 | d4e8164f | bellard | /*
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2 | d4e8164f | bellard | * internal execution defines for qemu
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3 | d4e8164f | bellard | *
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4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | d4e8164f | bellard | *
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6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
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7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
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9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
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10 | d4e8164f | bellard | *
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11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
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12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d4e8164f | bellard | * Lesser General Public License for more details.
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15 | d4e8164f | bellard | *
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16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | d4e8164f | bellard | * License along with this library; if not, write to the Free Software
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18 | d4e8164f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | d4e8164f | bellard | */
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20 | d4e8164f | bellard | |
21 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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22 | b346ff46 | bellard | #define DEBUG_DISAS
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23 | b346ff46 | bellard | |
24 | 33417e70 | bellard | #ifndef glue
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25 | 33417e70 | bellard | #define xglue(x, y) x ## y |
26 | 33417e70 | bellard | #define glue(x, y) xglue(x, y)
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27 | 33417e70 | bellard | #define stringify(s) tostring(s)
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28 | 33417e70 | bellard | #define tostring(s) #s |
29 | 33417e70 | bellard | #endif
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30 | 33417e70 | bellard | |
31 | c98baaac | bellard | #if __GNUC__ < 3 |
32 | 33417e70 | bellard | #define __builtin_expect(x, n) (x)
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33 | 33417e70 | bellard | #endif
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34 | 33417e70 | bellard | |
35 | e2222c39 | bellard | #ifdef __i386__
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36 | e2222c39 | bellard | #define REGPARM(n) __attribute((regparm(n)))
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37 | e2222c39 | bellard | #else
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38 | e2222c39 | bellard | #define REGPARM(n)
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39 | e2222c39 | bellard | #endif
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40 | e2222c39 | bellard | |
41 | b346ff46 | bellard | /* is_jmp field values */
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42 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
43 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
44 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
45 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
46 | b346ff46 | bellard | |
47 | b346ff46 | bellard | struct TranslationBlock;
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48 | b346ff46 | bellard | |
49 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
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50 | b346ff46 | bellard | #define MAX_OP_PER_INSTR 32 |
51 | b346ff46 | bellard | #define OPC_BUF_SIZE 512 |
52 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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53 | b346ff46 | bellard | |
54 | b346ff46 | bellard | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3) |
55 | b346ff46 | bellard | |
56 | b346ff46 | bellard | extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
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57 | b346ff46 | bellard | extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
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58 | c27004ec | bellard | extern long gen_labels[OPC_BUF_SIZE]; |
59 | c27004ec | bellard | extern int nb_gen_labels; |
60 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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61 | c27004ec | bellard | extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
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62 | 66e85a21 | bellard | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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63 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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64 | c3278b7b | bellard | extern target_ulong gen_opc_jump_pc[2]; |
65 | 30d6cb84 | bellard | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
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66 | b346ff46 | bellard | |
67 | 9886cc16 | bellard | typedef void (GenOpFunc)(void); |
68 | 9886cc16 | bellard | typedef void (GenOpFunc1)(long); |
69 | 9886cc16 | bellard | typedef void (GenOpFunc2)(long, long); |
70 | 9886cc16 | bellard | typedef void (GenOpFunc3)(long, long, long); |
71 | 9886cc16 | bellard | |
72 | b346ff46 | bellard | #if defined(TARGET_I386)
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73 | b346ff46 | bellard | |
74 | 33417e70 | bellard | void optimize_flags_init(void); |
75 | d4e8164f | bellard | |
76 | b346ff46 | bellard | #endif
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77 | b346ff46 | bellard | |
78 | b346ff46 | bellard | extern FILE *logfile;
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79 | b346ff46 | bellard | extern int loglevel; |
80 | b346ff46 | bellard | |
81 | 69d35728 | ths | void muls64(int64_t *phigh, int64_t *plow, int64_t a, int64_t b);
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82 | 69d35728 | ths | void mulu64(uint64_t *phigh, uint64_t *plow, uint64_t a, uint64_t b);
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83 | 69d35728 | ths | |
84 | 4c3a88a2 | bellard | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
85 | 4c3a88a2 | bellard | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
86 | b346ff46 | bellard | void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf); |
87 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
88 | b346ff46 | bellard | int max_code_size, int *gen_code_size_ptr); |
89 | 66e85a21 | bellard | int cpu_restore_state(struct TranslationBlock *tb, |
90 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
91 | 58fe2f10 | bellard | void *puc);
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92 | 58fe2f10 | bellard | int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb, |
93 | 58fe2f10 | bellard | int max_code_size, int *gen_code_size_ptr); |
94 | 58fe2f10 | bellard | int cpu_restore_state_copy(struct TranslationBlock *tb, |
95 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
96 | 58fe2f10 | bellard | void *puc);
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97 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
98 | 6a00d601 | bellard | void cpu_exec_init(CPUState *env);
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99 | 53a5960a | pbrook | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
100 | 2e12669a | bellard | void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
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101 | 2e12669a | bellard | int is_cpu_write_access);
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102 | 4390df51 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end);
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103 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
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104 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
105 | 84b7b8e7 | bellard | int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
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106 | 84b7b8e7 | bellard | target_phys_addr_t paddr, int prot,
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107 | 84b7b8e7 | bellard | int is_user, int is_softmmu); |
108 | 84b7b8e7 | bellard | static inline int tlb_set_page(CPUState *env, target_ulong vaddr, |
109 | 84b7b8e7 | bellard | target_phys_addr_t paddr, int prot,
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110 | 84b7b8e7 | bellard | int is_user, int is_softmmu) |
111 | 84b7b8e7 | bellard | { |
112 | 84b7b8e7 | bellard | if (prot & PAGE_READ)
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113 | 84b7b8e7 | bellard | prot |= PAGE_EXEC; |
114 | 84b7b8e7 | bellard | return tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
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115 | 84b7b8e7 | bellard | } |
116 | d4e8164f | bellard | |
117 | d4e8164f | bellard | #define CODE_GEN_MAX_SIZE 65536 |
118 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
119 | d4e8164f | bellard | |
120 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
121 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
122 | 4390df51 | bellard | |
123 | d4e8164f | bellard | /* maximum total translate dcode allocated */
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124 | 4390df51 | bellard | |
125 | 4390df51 | bellard | /* NOTE: the translated code area cannot be too big because on some
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126 | c4c7e3e6 | bellard | archs the range of "fast" function calls is limited. Here is a
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127 | 4390df51 | bellard | summary of the ranges:
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128 | 4390df51 | bellard | |
129 | 4390df51 | bellard | i386 : signed 32 bits
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130 | 4390df51 | bellard | arm : signed 26 bits
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131 | 4390df51 | bellard | ppc : signed 24 bits
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132 | 4390df51 | bellard | sparc : signed 32 bits
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133 | 4390df51 | bellard | alpha : signed 23 bits
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134 | 4390df51 | bellard | */
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135 | 4390df51 | bellard | |
136 | 4390df51 | bellard | #if defined(__alpha__)
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137 | 4390df51 | bellard | #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) |
138 | b8076a74 | bellard | #elif defined(__ia64)
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139 | b8076a74 | bellard | #define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */ |
140 | 4390df51 | bellard | #elif defined(__powerpc__)
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141 | c4c7e3e6 | bellard | #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) |
142 | 4390df51 | bellard | #else
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143 | c98baaac | bellard | #define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024) |
144 | 4390df51 | bellard | #endif
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145 | 4390df51 | bellard | |
146 | d4e8164f | bellard | //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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147 | d4e8164f | bellard | |
148 | 4390df51 | bellard | /* estimated block size for TB allocation */
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149 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
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150 | 4390df51 | bellard | according to the host CPU */
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151 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
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152 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
153 | 4390df51 | bellard | #else
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154 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
155 | 4390df51 | bellard | #endif
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156 | 4390df51 | bellard | |
157 | 4390df51 | bellard | #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
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158 | 4390df51 | bellard | |
159 | 4390df51 | bellard | #if defined(__powerpc__)
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160 | 4390df51 | bellard | #define USE_DIRECT_JUMP
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161 | 4390df51 | bellard | #endif
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162 | 67b915a5 | bellard | #if defined(__i386__) && !defined(_WIN32)
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163 | d4e8164f | bellard | #define USE_DIRECT_JUMP
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164 | d4e8164f | bellard | #endif
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165 | d4e8164f | bellard | |
166 | d4e8164f | bellard | typedef struct TranslationBlock { |
167 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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168 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
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169 | d4e8164f | bellard | unsigned int flags; /* flags defining in which context the code was generated */ |
170 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
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171 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
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172 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
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173 | bf088061 | bellard | #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */ |
174 | bf088061 | bellard | #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ |
175 | bf088061 | bellard | #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ |
176 | 2e12669a | bellard | #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ |
177 | 58fe2f10 | bellard | |
178 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
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179 | 4390df51 | bellard | /* next matching tb for physical address. */
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180 | 4390df51 | bellard | struct TranslationBlock *phys_hash_next;
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181 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
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182 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
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183 | 4390df51 | bellard | struct TranslationBlock *page_next[2]; |
184 | 4390df51 | bellard | target_ulong page_addr[2];
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185 | 4390df51 | bellard | |
186 | d4e8164f | bellard | /* the following data are used to directly call another TB from
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187 | d4e8164f | bellard | the code of this one. */
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188 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
189 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
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190 | 4cbb86e1 | bellard | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
191 | d4e8164f | bellard | #else
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192 | 95f7652d | bellard | uint32_t tb_next[2]; /* address of jump generated code */ |
193 | d4e8164f | bellard | #endif
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194 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
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195 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
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196 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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197 | d4e8164f | bellard | jmp_first */
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198 | d4e8164f | bellard | struct TranslationBlock *jmp_next[2]; |
199 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
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200 | d4e8164f | bellard | } TranslationBlock; |
201 | d4e8164f | bellard | |
202 | b362e5e0 | pbrook | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
203 | b362e5e0 | pbrook | { |
204 | b362e5e0 | pbrook | target_ulong tmp; |
205 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
206 | b362e5e0 | pbrook | return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
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207 | b362e5e0 | pbrook | } |
208 | b362e5e0 | pbrook | |
209 | 8a40a180 | bellard | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
210 | d4e8164f | bellard | { |
211 | b362e5e0 | pbrook | target_ulong tmp; |
212 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
213 | b362e5e0 | pbrook | return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
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214 | b362e5e0 | pbrook | (tmp & TB_JMP_ADDR_MASK)); |
215 | d4e8164f | bellard | } |
216 | d4e8164f | bellard | |
217 | 4390df51 | bellard | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
218 | 4390df51 | bellard | { |
219 | 4390df51 | bellard | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
220 | 4390df51 | bellard | } |
221 | 4390df51 | bellard | |
222 | c27004ec | bellard | TranslationBlock *tb_alloc(target_ulong pc); |
223 | 0124311e | bellard | void tb_flush(CPUState *env);
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224 | 4390df51 | bellard | void tb_link_phys(TranslationBlock *tb,
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225 | 4390df51 | bellard | target_ulong phys_pc, target_ulong phys_page2); |
226 | d4e8164f | bellard | |
227 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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228 | d4e8164f | bellard | |
229 | d4e8164f | bellard | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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230 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
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231 | d4e8164f | bellard | |
232 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
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233 | 4390df51 | bellard | |
234 | 4390df51 | bellard | #if defined(__powerpc__)
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235 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
236 | d4e8164f | bellard | { |
237 | d4e8164f | bellard | uint32_t val, *ptr; |
238 | d4e8164f | bellard | |
239 | d4e8164f | bellard | /* patch the branch destination */
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240 | 4cbb86e1 | bellard | ptr = (uint32_t *)jmp_addr; |
241 | d4e8164f | bellard | val = *ptr; |
242 | 4cbb86e1 | bellard | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
243 | d4e8164f | bellard | *ptr = val; |
244 | d4e8164f | bellard | /* flush icache */
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245 | d4e8164f | bellard | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); |
246 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
247 | d4e8164f | bellard | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); |
248 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
249 | d4e8164f | bellard | asm volatile ("isync" : : : "memory"); |
250 | d4e8164f | bellard | } |
251 | 4390df51 | bellard | #elif defined(__i386__)
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252 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
253 | 4390df51 | bellard | { |
254 | 4390df51 | bellard | /* patch the branch destination */
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255 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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256 | 4390df51 | bellard | /* no need to flush icache explicitely */
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257 | 4390df51 | bellard | } |
258 | 4390df51 | bellard | #endif
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259 | d4e8164f | bellard | |
260 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target(TranslationBlock *tb, |
261 | 4cbb86e1 | bellard | int n, unsigned long addr) |
262 | 4cbb86e1 | bellard | { |
263 | 4cbb86e1 | bellard | unsigned long offset; |
264 | 4cbb86e1 | bellard | |
265 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
266 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
267 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n + 2];
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268 | 4cbb86e1 | bellard | if (offset != 0xffff) |
269 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
270 | 4cbb86e1 | bellard | } |
271 | 4cbb86e1 | bellard | |
272 | d4e8164f | bellard | #else
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273 | d4e8164f | bellard | |
274 | d4e8164f | bellard | /* set the jump target */
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275 | d4e8164f | bellard | static inline void tb_set_jmp_target(TranslationBlock *tb, |
276 | d4e8164f | bellard | int n, unsigned long addr) |
277 | d4e8164f | bellard | { |
278 | 95f7652d | bellard | tb->tb_next[n] = addr; |
279 | d4e8164f | bellard | } |
280 | d4e8164f | bellard | |
281 | d4e8164f | bellard | #endif
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282 | d4e8164f | bellard | |
283 | d4e8164f | bellard | static inline void tb_add_jump(TranslationBlock *tb, int n, |
284 | d4e8164f | bellard | TranslationBlock *tb_next) |
285 | d4e8164f | bellard | { |
286 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
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287 | cf25629d | bellard | if (!tb->jmp_next[n]) {
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288 | cf25629d | bellard | /* patch the native jump address */
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289 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
290 | cf25629d | bellard | |
291 | cf25629d | bellard | /* add in TB jmp circular list */
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292 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
293 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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294 | cf25629d | bellard | } |
295 | d4e8164f | bellard | } |
296 | d4e8164f | bellard | |
297 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
298 | a513fe19 | bellard | |
299 | d4e8164f | bellard | #ifndef offsetof
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300 | d4e8164f | bellard | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
301 | d4e8164f | bellard | #endif
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302 | d4e8164f | bellard | |
303 | d549f7d9 | bellard | #if defined(_WIN32)
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304 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
305 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".section .text\n" |
306 | d549f7d9 | bellard | #elif defined(__APPLE__)
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307 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".data\n" |
308 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".text\n" |
309 | d549f7d9 | bellard | #else
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310 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
311 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".previous\n" |
312 | d549f7d9 | bellard | #endif
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313 | d549f7d9 | bellard | |
314 | 75913b72 | bellard | #define ASM_OP_LABEL_NAME(n, opname) \
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315 | 75913b72 | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) |
316 | 75913b72 | bellard | |
317 | b346ff46 | bellard | #if defined(__powerpc__)
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318 | b346ff46 | bellard | |
319 | 4390df51 | bellard | /* we patch the jump instruction directly */
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320 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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321 | b346ff46 | bellard | do {\
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322 | d549f7d9 | bellard | asm volatile (ASM_DATA_SECTION\ |
323 | 75913b72 | bellard | ASM_OP_LABEL_NAME(n, opname) ":\n"\
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324 | 9257a9e4 | bellard | ".long 1f\n"\
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325 | d549f7d9 | bellard | ASM_PREVIOUS_SECTION \ |
326 | d549f7d9 | bellard | "b " ASM_NAME(__op_jmp) #n "\n"\ |
327 | 9257a9e4 | bellard | "1:\n");\
|
328 | 4390df51 | bellard | } while (0) |
329 | 4390df51 | bellard | |
330 | 4390df51 | bellard | #elif defined(__i386__) && defined(USE_DIRECT_JUMP)
|
331 | 4390df51 | bellard | |
332 | 4390df51 | bellard | /* we patch the jump instruction directly */
|
333 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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334 | c27004ec | bellard | do {\
|
335 | c27004ec | bellard | asm volatile (".section .data\n"\ |
336 | 75913b72 | bellard | ASM_OP_LABEL_NAME(n, opname) ":\n"\
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337 | c27004ec | bellard | ".long 1f\n"\
|
338 | c27004ec | bellard | ASM_PREVIOUS_SECTION \ |
339 | c27004ec | bellard | "jmp " ASM_NAME(__op_jmp) #n "\n"\ |
340 | c27004ec | bellard | "1:\n");\
|
341 | c27004ec | bellard | } while (0) |
342 | c27004ec | bellard | |
343 | b346ff46 | bellard | #else
|
344 | b346ff46 | bellard | |
345 | b346ff46 | bellard | /* jump to next block operations (more portable code, does not need
|
346 | b346ff46 | bellard | cache flushing, but slower because of indirect jump) */
|
347 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
|
348 | b346ff46 | bellard | do {\
|
349 | 2f62b397 | bellard | static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\ |
350 | 75913b72 | bellard | static void __attribute__((unused)) *__op_label ## n \ |
351 | 75913b72 | bellard | __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\ |
352 | b346ff46 | bellard | goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ |
353 | ae063a68 | bellard | label ## n: ;\ |
354 | ae063a68 | bellard | dummy_label ## n: ;\ |
355 | b346ff46 | bellard | } while (0) |
356 | b346ff46 | bellard | |
357 | ae063a68 | bellard | #endif
|
358 | ae063a68 | bellard | |
359 | 33417e70 | bellard | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
360 | 33417e70 | bellard | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
361 | a4193c8a | bellard | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
362 | 33417e70 | bellard | |
363 | 204a1b8d | ths | #if defined(__powerpc__)
|
364 | d4e8164f | bellard | static inline int testandset (int *p) |
365 | d4e8164f | bellard | { |
366 | d4e8164f | bellard | int ret;
|
367 | d4e8164f | bellard | __asm__ __volatile__ ( |
368 | 02e1ec9b | bellard | "0: lwarx %0,0,%1\n"
|
369 | 02e1ec9b | bellard | " xor. %0,%3,%0\n"
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370 | 02e1ec9b | bellard | " bne 1f\n"
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371 | 02e1ec9b | bellard | " stwcx. %2,0,%1\n"
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372 | 02e1ec9b | bellard | " bne- 0b\n"
|
373 | d4e8164f | bellard | "1: "
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374 | d4e8164f | bellard | : "=&r" (ret)
|
375 | d4e8164f | bellard | : "r" (p), "r" (1), "r" (0) |
376 | d4e8164f | bellard | : "cr0", "memory"); |
377 | d4e8164f | bellard | return ret;
|
378 | d4e8164f | bellard | } |
379 | 204a1b8d | ths | #elif defined(__i386__)
|
380 | d4e8164f | bellard | static inline int testandset (int *p) |
381 | d4e8164f | bellard | { |
382 | 4955a2cd | bellard | long int readval = 0; |
383 | d4e8164f | bellard | |
384 | 4955a2cd | bellard | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
|
385 | 4955a2cd | bellard | : "+m" (*p), "+a" (readval) |
386 | 4955a2cd | bellard | : "r" (1) |
387 | 4955a2cd | bellard | : "cc");
|
388 | 4955a2cd | bellard | return readval;
|
389 | d4e8164f | bellard | } |
390 | 204a1b8d | ths | #elif defined(__x86_64__)
|
391 | bc51c5c9 | bellard | static inline int testandset (int *p) |
392 | bc51c5c9 | bellard | { |
393 | 4955a2cd | bellard | long int readval = 0; |
394 | bc51c5c9 | bellard | |
395 | 4955a2cd | bellard | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
|
396 | 4955a2cd | bellard | : "+m" (*p), "+a" (readval) |
397 | 4955a2cd | bellard | : "r" (1) |
398 | 4955a2cd | bellard | : "cc");
|
399 | 4955a2cd | bellard | return readval;
|
400 | bc51c5c9 | bellard | } |
401 | 204a1b8d | ths | #elif defined(__s390__)
|
402 | d4e8164f | bellard | static inline int testandset (int *p) |
403 | d4e8164f | bellard | { |
404 | d4e8164f | bellard | int ret;
|
405 | d4e8164f | bellard | |
406 | d4e8164f | bellard | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
|
407 | d4e8164f | bellard | " jl 0b"
|
408 | d4e8164f | bellard | : "=&d" (ret)
|
409 | d4e8164f | bellard | : "r" (1), "a" (p), "0" (*p) |
410 | d4e8164f | bellard | : "cc", "memory" ); |
411 | d4e8164f | bellard | return ret;
|
412 | d4e8164f | bellard | } |
413 | 204a1b8d | ths | #elif defined(__alpha__)
|
414 | 2f87c607 | bellard | static inline int testandset (int *p) |
415 | d4e8164f | bellard | { |
416 | d4e8164f | bellard | int ret;
|
417 | d4e8164f | bellard | unsigned long one; |
418 | d4e8164f | bellard | |
419 | d4e8164f | bellard | __asm__ __volatile__ ("0: mov 1,%2\n"
|
420 | d4e8164f | bellard | " ldl_l %0,%1\n"
|
421 | d4e8164f | bellard | " stl_c %2,%1\n"
|
422 | d4e8164f | bellard | " beq %2,1f\n"
|
423 | d4e8164f | bellard | ".subsection 2\n"
|
424 | d4e8164f | bellard | "1: br 0b\n"
|
425 | d4e8164f | bellard | ".previous"
|
426 | d4e8164f | bellard | : "=r" (ret), "=m" (*p), "=r" (one) |
427 | d4e8164f | bellard | : "m" (*p));
|
428 | d4e8164f | bellard | return ret;
|
429 | d4e8164f | bellard | } |
430 | 204a1b8d | ths | #elif defined(__sparc__)
|
431 | d4e8164f | bellard | static inline int testandset (int *p) |
432 | d4e8164f | bellard | { |
433 | d4e8164f | bellard | int ret;
|
434 | d4e8164f | bellard | |
435 | d4e8164f | bellard | __asm__ __volatile__("ldstub [%1], %0"
|
436 | d4e8164f | bellard | : "=r" (ret)
|
437 | d4e8164f | bellard | : "r" (p)
|
438 | d4e8164f | bellard | : "memory");
|
439 | d4e8164f | bellard | |
440 | d4e8164f | bellard | return (ret ? 1 : 0); |
441 | d4e8164f | bellard | } |
442 | 204a1b8d | ths | #elif defined(__arm__)
|
443 | a95c6790 | bellard | static inline int testandset (int *spinlock) |
444 | a95c6790 | bellard | { |
445 | a95c6790 | bellard | register unsigned int ret; |
446 | a95c6790 | bellard | __asm__ __volatile__("swp %0, %1, [%2]"
|
447 | a95c6790 | bellard | : "=r"(ret)
|
448 | a95c6790 | bellard | : "0"(1), "r"(spinlock)); |
449 | a95c6790 | bellard | |
450 | a95c6790 | bellard | return ret;
|
451 | a95c6790 | bellard | } |
452 | 204a1b8d | ths | #elif defined(__mc68000)
|
453 | 38e584a0 | bellard | static inline int testandset (int *p) |
454 | 38e584a0 | bellard | { |
455 | 38e584a0 | bellard | char ret;
|
456 | 38e584a0 | bellard | __asm__ __volatile__("tas %1; sne %0"
|
457 | 38e584a0 | bellard | : "=r" (ret)
|
458 | 38e584a0 | bellard | : "m" (p)
|
459 | 38e584a0 | bellard | : "cc","memory"); |
460 | 4955a2cd | bellard | return ret;
|
461 | 38e584a0 | bellard | } |
462 | 204a1b8d | ths | #elif defined(__ia64)
|
463 | 38e584a0 | bellard | |
464 | b8076a74 | bellard | #include <ia64intrin.h> |
465 | b8076a74 | bellard | |
466 | b8076a74 | bellard | static inline int testandset (int *p) |
467 | b8076a74 | bellard | { |
468 | b8076a74 | bellard | return __sync_lock_test_and_set (p, 1); |
469 | b8076a74 | bellard | } |
470 | 204a1b8d | ths | #elif defined(__mips__)
|
471 | c4b89d18 | ths | static inline int testandset (int *p) |
472 | c4b89d18 | ths | { |
473 | c4b89d18 | ths | int ret;
|
474 | c4b89d18 | ths | |
475 | c4b89d18 | ths | __asm__ __volatile__ ( |
476 | c4b89d18 | ths | " .set push \n"
|
477 | c4b89d18 | ths | " .set noat \n"
|
478 | c4b89d18 | ths | " .set mips2 \n"
|
479 | c4b89d18 | ths | "1: li $1, 1 \n"
|
480 | c4b89d18 | ths | " ll %0, %1 \n"
|
481 | c4b89d18 | ths | " sc $1, %1 \n"
|
482 | 976a0d0d | ths | " beqz $1, 1b \n"
|
483 | c4b89d18 | ths | " .set pop "
|
484 | c4b89d18 | ths | : "=r" (ret), "+R" (*p) |
485 | c4b89d18 | ths | : |
486 | c4b89d18 | ths | : "memory");
|
487 | c4b89d18 | ths | |
488 | c4b89d18 | ths | return ret;
|
489 | c4b89d18 | ths | } |
490 | 204a1b8d | ths | #else
|
491 | 204a1b8d | ths | #error unimplemented CPU support
|
492 | c4b89d18 | ths | #endif
|
493 | c4b89d18 | ths | |
494 | d4e8164f | bellard | typedef int spinlock_t; |
495 | d4e8164f | bellard | |
496 | d4e8164f | bellard | #define SPIN_LOCK_UNLOCKED 0 |
497 | d4e8164f | bellard | |
498 | aebcb60e | bellard | #if defined(CONFIG_USER_ONLY)
|
499 | d4e8164f | bellard | static inline void spin_lock(spinlock_t *lock) |
500 | d4e8164f | bellard | { |
501 | d4e8164f | bellard | while (testandset(lock));
|
502 | d4e8164f | bellard | } |
503 | d4e8164f | bellard | |
504 | d4e8164f | bellard | static inline void spin_unlock(spinlock_t *lock) |
505 | d4e8164f | bellard | { |
506 | d4e8164f | bellard | *lock = 0;
|
507 | d4e8164f | bellard | } |
508 | d4e8164f | bellard | |
509 | d4e8164f | bellard | static inline int spin_trylock(spinlock_t *lock) |
510 | d4e8164f | bellard | { |
511 | d4e8164f | bellard | return !testandset(lock);
|
512 | d4e8164f | bellard | } |
513 | 3c1cf9fa | bellard | #else
|
514 | 3c1cf9fa | bellard | static inline void spin_lock(spinlock_t *lock) |
515 | 3c1cf9fa | bellard | { |
516 | 3c1cf9fa | bellard | } |
517 | 3c1cf9fa | bellard | |
518 | 3c1cf9fa | bellard | static inline void spin_unlock(spinlock_t *lock) |
519 | 3c1cf9fa | bellard | { |
520 | 3c1cf9fa | bellard | } |
521 | 3c1cf9fa | bellard | |
522 | 3c1cf9fa | bellard | static inline int spin_trylock(spinlock_t *lock) |
523 | 3c1cf9fa | bellard | { |
524 | 3c1cf9fa | bellard | return 1; |
525 | 3c1cf9fa | bellard | } |
526 | 3c1cf9fa | bellard | #endif
|
527 | d4e8164f | bellard | |
528 | d4e8164f | bellard | extern spinlock_t tb_lock;
|
529 | d4e8164f | bellard | |
530 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
531 | 6e59c1db | bellard | |
532 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
|
533 | 6e59c1db | bellard | |
534 | c27004ec | bellard | void tlb_fill(target_ulong addr, int is_write, int is_user, |
535 | 6e59c1db | bellard | void *retaddr);
|
536 | 6e59c1db | bellard | |
537 | 6e59c1db | bellard | #define ACCESS_TYPE 3 |
538 | 6e59c1db | bellard | #define MEMSUFFIX _code
|
539 | 6e59c1db | bellard | #define env cpu_single_env
|
540 | 6e59c1db | bellard | |
541 | 6e59c1db | bellard | #define DATA_SIZE 1 |
542 | 6e59c1db | bellard | #include "softmmu_header.h" |
543 | 6e59c1db | bellard | |
544 | 6e59c1db | bellard | #define DATA_SIZE 2 |
545 | 6e59c1db | bellard | #include "softmmu_header.h" |
546 | 6e59c1db | bellard | |
547 | 6e59c1db | bellard | #define DATA_SIZE 4 |
548 | 6e59c1db | bellard | #include "softmmu_header.h" |
549 | 6e59c1db | bellard | |
550 | c27004ec | bellard | #define DATA_SIZE 8 |
551 | c27004ec | bellard | #include "softmmu_header.h" |
552 | c27004ec | bellard | |
553 | 6e59c1db | bellard | #undef ACCESS_TYPE
|
554 | 6e59c1db | bellard | #undef MEMSUFFIX
|
555 | 6e59c1db | bellard | #undef env
|
556 | 6e59c1db | bellard | |
557 | 6e59c1db | bellard | #endif
|
558 | 4390df51 | bellard | |
559 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
|
560 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
561 | 4390df51 | bellard | { |
562 | 4390df51 | bellard | return addr;
|
563 | 4390df51 | bellard | } |
564 | 4390df51 | bellard | #else
|
565 | 4390df51 | bellard | /* NOTE: this function can trigger an exception */
|
566 | 1ccde1cb | bellard | /* NOTE2: the returned address is not exactly the physical address: it
|
567 | 1ccde1cb | bellard | is the offset relative to phys_ram_base */
|
568 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
569 | 4390df51 | bellard | { |
570 | c27004ec | bellard | int is_user, index, pd;
|
571 | 4390df51 | bellard | |
572 | 4390df51 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
573 | 3f5dcc34 | bellard | #if defined(TARGET_I386)
|
574 | 4390df51 | bellard | is_user = ((env->hflags & HF_CPL_MASK) == 3);
|
575 | 3f5dcc34 | bellard | #elif defined (TARGET_PPC)
|
576 | 3f5dcc34 | bellard | is_user = msr_pr; |
577 | 6af0bf9c | bellard | #elif defined (TARGET_MIPS)
|
578 | 6af0bf9c | bellard | is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM); |
579 | e95c8d51 | bellard | #elif defined (TARGET_SPARC)
|
580 | e95c8d51 | bellard | is_user = (env->psrs == 0);
|
581 | b5ff1b31 | bellard | #elif defined (TARGET_ARM)
|
582 | b5ff1b31 | bellard | is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR); |
583 | fdf9b3e8 | bellard | #elif defined (TARGET_SH4)
|
584 | fdf9b3e8 | bellard | is_user = ((env->sr & SR_MD) == 0);
|
585 | eddf68a6 | j_mayer | #elif defined (TARGET_ALPHA)
|
586 | eddf68a6 | j_mayer | is_user = ((env->ps >> 3) & 3); |
587 | 0633879f | pbrook | #elif defined (TARGET_M68K)
|
588 | 0633879f | pbrook | is_user = ((env->sr & SR_S) == 0);
|
589 | 3f5dcc34 | bellard | #else
|
590 | b5ff1b31 | bellard | #error unimplemented CPU
|
591 | 3f5dcc34 | bellard | #endif
|
592 | 84b7b8e7 | bellard | if (__builtin_expect(env->tlb_table[is_user][index].addr_code !=
|
593 | 4390df51 | bellard | (addr & TARGET_PAGE_MASK), 0)) {
|
594 | c27004ec | bellard | ldub_code(addr); |
595 | c27004ec | bellard | } |
596 | 84b7b8e7 | bellard | pd = env->tlb_table[is_user][index].addr_code & ~TARGET_PAGE_MASK; |
597 | 2a4188a3 | bellard | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
|
598 | 6c36d3fa | blueswir1 | #ifdef TARGET_SPARC
|
599 | 6c36d3fa | blueswir1 | do_unassigned_access(addr, 0, 1, 0); |
600 | 6c36d3fa | blueswir1 | #else
|
601 | 36d23958 | ths | cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
602 | 6c36d3fa | blueswir1 | #endif
|
603 | 4390df51 | bellard | } |
604 | 84b7b8e7 | bellard | return addr + env->tlb_table[is_user][index].addend - (unsigned long)phys_ram_base; |
605 | 4390df51 | bellard | } |
606 | 4390df51 | bellard | #endif
|
607 | 9df217a3 | bellard | |
608 | 9df217a3 | bellard | #ifdef USE_KQEMU
|
609 | f32fc648 | bellard | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) |
610 | f32fc648 | bellard | |
611 | 9df217a3 | bellard | int kqemu_init(CPUState *env);
|
612 | 9df217a3 | bellard | int kqemu_cpu_exec(CPUState *env);
|
613 | 9df217a3 | bellard | void kqemu_flush_page(CPUState *env, target_ulong addr);
|
614 | 9df217a3 | bellard | void kqemu_flush(CPUState *env, int global); |
615 | 4b7df22f | bellard | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
|
616 | f32fc648 | bellard | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
|
617 | a332e112 | bellard | void kqemu_cpu_interrupt(CPUState *env);
|
618 | f32fc648 | bellard | void kqemu_record_dump(void); |
619 | 9df217a3 | bellard | |
620 | 9df217a3 | bellard | static inline int kqemu_is_ok(CPUState *env) |
621 | 9df217a3 | bellard | { |
622 | 9df217a3 | bellard | return(env->kqemu_enabled &&
|
623 | 9df217a3 | bellard | (env->cr[0] & CR0_PE_MASK) &&
|
624 | f32fc648 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK) && |
625 | 9df217a3 | bellard | (env->eflags & IF_MASK) && |
626 | f32fc648 | bellard | !(env->eflags & VM_MASK) && |
627 | f32fc648 | bellard | (env->kqemu_enabled == 2 ||
|
628 | f32fc648 | bellard | ((env->hflags & HF_CPL_MASK) == 3 &&
|
629 | f32fc648 | bellard | (env->eflags & IOPL_MASK) != IOPL_MASK))); |
630 | 9df217a3 | bellard | } |
631 | 9df217a3 | bellard | |
632 | 9df217a3 | bellard | #endif |