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/*
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 *  SH4 emulation
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 * 
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 *  Copyright (c) 2005 Samuel Tardieu
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "exec.h"
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static inline void set_flag(uint32_t flag)
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{
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    env->flags |= flag;
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}
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static inline void clr_flag(uint32_t flag)
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{
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    env->flags &= ~flag;
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}
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static inline void set_t(void)
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{
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    env->sr |= SR_T;
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}
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static inline void clr_t(void)
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{
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    env->sr &= ~SR_T;
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}
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static inline void cond_t(int cond)
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{
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    if (cond)
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        set_t();
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    else
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        clr_t();
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}
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void OPPROTO op_movl_imm_T0(void)
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{
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    T0 = (uint32_t) PARAM1;
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    RETURN();
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}
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void OPPROTO op_movl_imm_T1(void)
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{
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    T0 = (uint32_t) PARAM1;
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    RETURN();
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}
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void OPPROTO op_movl_imm_T2(void)
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{
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    T0 = (uint32_t) PARAM1;
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    RETURN();
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}
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void OPPROTO op_cmp_eq_imm_T0(void)
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{
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    cond_t((int32_t) T0 == (int32_t) PARAM1);
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    RETURN();
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}
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void OPPROTO op_cmd_eq_T0_T1(void)
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{
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    cond_t(T0 == T1);
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    RETURN();
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}
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void OPPROTO op_cmd_hs_T0_T1(void)
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{
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    cond_t((uint32_t) T0 <= (uint32_t) T1);
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    RETURN();
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}
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void OPPROTO op_cmd_ge_T0_T1(void)
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{
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    cond_t((int32_t) T0 <= (int32_t) T1);
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    RETURN();
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}
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void OPPROTO op_cmd_hi_T0_T1(void)
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{
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    cond_t((uint32_t) T0 < (uint32_t) T1);
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    RETURN();
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}
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void OPPROTO op_cmd_gt_T0_T1(void)
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{
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    cond_t((int32_t) T0 < (int32_t) T1);
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    RETURN();
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}
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void OPPROTO op_not_T0(void)
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{
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    T0 = ~T0;
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    RETURN();
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}
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void OPPROTO op_bf_s(void)
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{
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    env->delayed_pc = PARAM1;
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    set_flag(DELAY_SLOT_CONDITIONAL | ((~env->sr) & SR_T));
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    RETURN();
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}
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void OPPROTO op_bt_s(void)
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{
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    env->delayed_pc = PARAM1;
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    set_flag(DELAY_SLOT_CONDITIONAL | (env->sr & SR_T));
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    RETURN();
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}
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void OPPROTO op_bra(void)
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{
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    env->delayed_pc = PARAM1;
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    set_flag(DELAY_SLOT);
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    RETURN();
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}
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void OPPROTO op_braf_T0(void)
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{
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    env->delayed_pc = PARAM1 + T0;
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    set_flag(DELAY_SLOT);
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    RETURN();
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}
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void OPPROTO op_bsr(void)
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{
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    env->pr = PARAM1;
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    env->delayed_pc = PARAM2;
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    set_flag(DELAY_SLOT);
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    RETURN();
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}
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void OPPROTO op_bsrf_T0(void)
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{
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    env->pr = PARAM1;
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    env->delayed_pc = PARAM1 + T0;
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    set_flag(DELAY_SLOT);
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    RETURN();
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}
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void OPPROTO op_jsr_T0(void)
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{
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    env->pr = PARAM1;
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    env->delayed_pc = T0;
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    set_flag(DELAY_SLOT);
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    RETURN();
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}
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void OPPROTO op_rts(void)
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{
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    env->delayed_pc = env->pr;
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    set_flag(DELAY_SLOT);
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    RETURN();
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}
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void OPPROTO op_clr_delay_slot(void)
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{
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    clr_flag(DELAY_SLOT);
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    RETURN();
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}
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void OPPROTO op_clr_delay_slot_conditional(void)
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{
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    clr_flag(DELAY_SLOT_CONDITIONAL);
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    RETURN();
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}
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void OPPROTO op_exit_tb(void)
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{
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    EXIT_TB();
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    RETURN();
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}
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void OPPROTO op_addl_imm_T0(void)
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{
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    T0 += PARAM1;
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    RETURN();
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}
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void OPPROTO op_addl_imm_T1(void)
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{
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    T1 += PARAM1;
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    RETURN();
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}
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void OPPROTO op_clrmac(void)
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{
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    env->mach = env->macl = 0;
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    RETURN();
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}
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void OPPROTO op_clrs(void)
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{
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    env->sr &= ~SR_S;
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    RETURN();
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}
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void OPPROTO op_clrt(void)
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{
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    env->sr &= ~SR_T;
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    RETURN();
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}
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void OPPROTO op_sets(void)
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{
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    env->sr |= SR_S;
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    RETURN();
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}
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void OPPROTO op_sett(void)
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{
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    env->sr |= SR_T;
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    RETURN();
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}
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void OPPROTO op_frchg(void)
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{
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    env->fpscr ^= FPSCR_FR;
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    RETURN();
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}
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void OPPROTO op_fschg(void)
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{
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    env->fpscr ^= FPSCR_SZ;
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    RETURN();
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}
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void OPPROTO op_rte(void)
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{
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    env->sr = env->ssr;
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    env->delayed_pc = env->spc;
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    set_flag(DELAY_SLOT);
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    RETURN();
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}
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void OPPROTO op_swapb_T0(void)
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{
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    T0 = (T0 & 0xffff0000) | ((T0 & 0xff) << 8) | ((T0 >> 8) & 0xff);
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    RETURN();
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}
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void OPPROTO op_swapw_T0(void)
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{
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    T0 = ((T0 & 0xffff) << 16) | ((T0 >> 16) & 0xffff);
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    RETURN();
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}
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void OPPROTO op_xtrct_T0_T1(void)
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{
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    T1 = ((T0 & 0xffff) << 16) | ((T1 >> 16) & 0xffff);
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    RETURN();
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}
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void OPPROTO op_addc_T0_T1(void)
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{
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    helper_addc_T0_T1();
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    RETURN();
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}
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void OPPROTO op_addv_T0_T1(void)
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{
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    helper_addv_T0_T1();
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    RETURN();
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}
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void OPPROTO op_cmp_eq_T0_T1(void)
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{
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    cond_t(T1 == T0);
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    RETURN();
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}
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void OPPROTO op_cmp_ge_T0_T1(void)
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{
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    cond_t((int32_t) T1 >= (int32_t) T0);
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    RETURN();
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}
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void OPPROTO op_cmp_gt_T0_T1(void)
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{
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    cond_t((int32_t) T1 > (int32_t) T0);
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    RETURN();
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}
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void OPPROTO op_cmp_hi_T0_T1(void)
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{
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    cond_t((uint32_t) T1 > (uint32_t) T0);
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    RETURN();
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}
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void OPPROTO op_cmp_hs_T0_T1(void)
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{
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    cond_t((uint32_t) T1 >= (uint32_t) T0);
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    RETURN();
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}
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void OPPROTO op_cmp_str_T0_T1(void)
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{
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    cond_t((T0 & 0x000000ff) == (T1 & 0x000000ff) ||
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           (T0 & 0x0000ff00) == (T1 & 0x0000ff00) ||
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           (T0 & 0x00ff0000) == (T1 & 0x00ff0000) ||
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           (T0 & 0xff000000) == (T1 & 0xff000000));
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    RETURN();
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}
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void OPPROTO op_tst_T0_T1(void)
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{
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    cond_t((T1 & T0) == 0);
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    RETURN();
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}
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void OPPROTO op_div0s_T0_T1(void)
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{
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    if (T1 & 0x80000000)
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        env->sr |= SR_Q;
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    else
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        env->sr &= ~SR_Q;
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    if (T0 & 0x80000000)
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        env->sr |= SR_M;
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    else
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        env->sr &= ~SR_M;
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    cond_t((T1 ^ T0) & 0x80000000);
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    RETURN();
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}
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void OPPROTO op_div0u(void)
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{
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    env->sr &= ~(SR_M | SR_Q | SR_T);
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    RETURN();
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}
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void OPPROTO op_div1_T0_T1(void)
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{
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    helper_div1_T0_T1();
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    RETURN();
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}
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void OPPROTO op_dmulsl_T0_T1(void)
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{
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    helper_dmulsl_T0_T1();
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    RETURN();
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}
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void OPPROTO op_dmulul_T0_T1(void)
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{
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    helper_dmulul_T0_T1();
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    RETURN();
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}
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void OPPROTO op_macl_T0_T1(void)
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{
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    helper_macl_T0_T1();
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    RETURN();
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}
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void OPPROTO op_macw_T0_T1(void)
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{
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    helper_macw_T0_T1();
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    RETURN();
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}
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void OPPROTO op_mull_T0_T1(void)
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{
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    env->macl = (T0 * T1) & 0xffffffff;
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    RETURN();
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}
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void OPPROTO op_mulsw_T0_T1(void)
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{
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    env->macl = (int32_t) T0 *(int32_t) T1;
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    RETURN();
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}
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void OPPROTO op_muluw_T0_T1(void)
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{
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    env->macl = (uint32_t) T0 *(uint32_t) T1;
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    RETURN();
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}
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void OPPROTO op_neg_T0(void)
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{
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    T0 = -T0;
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    RETURN();
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}
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void OPPROTO op_negc_T0(void)
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{
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    helper_negc_T0();
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    RETURN();
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}
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void OPPROTO op_shad_T0_T1(void)
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{
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    if ((T0 & 0x80000000) == 0)
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        T1 <<= (T0 & 0x1f);
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    else if ((T0 & 0x1f) == 0)
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        T1 = 0;
410 fdf9b3e8 bellard
    else
411 fdf9b3e8 bellard
        T1 = ((int32_t) T1) >> ((~T0 & 0x1f) + 1);
412 fdf9b3e8 bellard
    RETURN();
413 fdf9b3e8 bellard
}
414 fdf9b3e8 bellard
415 fdf9b3e8 bellard
void OPPROTO op_shld_T0_T1(void)
416 fdf9b3e8 bellard
{
417 fdf9b3e8 bellard
    if ((T0 & 0x80000000) == 0)
418 fdf9b3e8 bellard
        T1 <<= (T0 & 0x1f);
419 fdf9b3e8 bellard
    else if ((T0 & 0x1f) == 0)
420 fdf9b3e8 bellard
        T1 = 0;
421 fdf9b3e8 bellard
    else
422 fdf9b3e8 bellard
        T1 = ((uint32_t) T1) >> ((~T0 & 0x1f) + 1);
423 fdf9b3e8 bellard
    RETURN();
424 fdf9b3e8 bellard
}
425 fdf9b3e8 bellard
426 fdf9b3e8 bellard
void OPPROTO op_subc_T0_T1(void)
427 fdf9b3e8 bellard
{
428 fdf9b3e8 bellard
    helper_subc_T0_T1();
429 fdf9b3e8 bellard
    RETURN();
430 fdf9b3e8 bellard
}
431 fdf9b3e8 bellard
432 fdf9b3e8 bellard
void OPPROTO op_subv_T0_T1(void)
433 fdf9b3e8 bellard
{
434 fdf9b3e8 bellard
    helper_subv_T0_T1();
435 fdf9b3e8 bellard
    RETURN();
436 fdf9b3e8 bellard
}
437 fdf9b3e8 bellard
438 fdf9b3e8 bellard
void OPPROTO op_trapa(void)
439 fdf9b3e8 bellard
{
440 fdf9b3e8 bellard
    env->tra = PARAM1 * 2;
441 fdf9b3e8 bellard
    env->exception_index = 0x160;
442 fdf9b3e8 bellard
    do_raise_exception();
443 fdf9b3e8 bellard
    RETURN();
444 fdf9b3e8 bellard
}
445 fdf9b3e8 bellard
446 fdf9b3e8 bellard
void OPPROTO op_cmp_pl_T0(void)
447 fdf9b3e8 bellard
{
448 fdf9b3e8 bellard
    cond_t((int32_t) T0 > 0);
449 fdf9b3e8 bellard
    RETURN();
450 fdf9b3e8 bellard
}
451 fdf9b3e8 bellard
452 fdf9b3e8 bellard
void OPPROTO op_cmp_pz_T0(void)
453 fdf9b3e8 bellard
{
454 fdf9b3e8 bellard
    cond_t((int32_t) T0 >= 0);
455 fdf9b3e8 bellard
    RETURN();
456 fdf9b3e8 bellard
}
457 fdf9b3e8 bellard
458 fdf9b3e8 bellard
void OPPROTO op_jmp_T0(void)
459 fdf9b3e8 bellard
{
460 fdf9b3e8 bellard
    env->delayed_pc = T0;
461 fdf9b3e8 bellard
    set_flag(DELAY_SLOT);
462 fdf9b3e8 bellard
    RETURN();
463 fdf9b3e8 bellard
}
464 fdf9b3e8 bellard
465 fdf9b3e8 bellard
void OPPROTO op_movl_rN_rN(void)
466 fdf9b3e8 bellard
{
467 fdf9b3e8 bellard
    env->gregs[PARAM2] = env->gregs[PARAM1];
468 fdf9b3e8 bellard
    RETURN();
469 fdf9b3e8 bellard
}
470 fdf9b3e8 bellard
471 fdf9b3e8 bellard
void OPPROTO op_ldcl_rMplus_rN_bank(void)
472 fdf9b3e8 bellard
{
473 fdf9b3e8 bellard
    env->gregs[PARAM2] = env->gregs[PARAM1];
474 fdf9b3e8 bellard
    env->gregs[PARAM1] += 4;
475 fdf9b3e8 bellard
    RETURN();
476 fdf9b3e8 bellard
}
477 fdf9b3e8 bellard
478 eda9b09b bellard
void OPPROTO op_ldc_T0_sr(void)
479 eda9b09b bellard
{
480 eda9b09b bellard
    env->sr = T0 & 0x700083f3;
481 eda9b09b bellard
    RETURN();
482 eda9b09b bellard
}
483 eda9b09b bellard
484 eda9b09b bellard
void OPPROTO op_stc_sr_T0(void)
485 eda9b09b bellard
{
486 eda9b09b bellard
    T0 = env->sr;
487 eda9b09b bellard
    RETURN();
488 eda9b09b bellard
}
489 eda9b09b bellard
490 fdf9b3e8 bellard
#define LDSTOPS(target,load,store) \
491 fdf9b3e8 bellard
void OPPROTO op_##load##_T0_##target (void) \
492 fdf9b3e8 bellard
{ env ->target = T0;   RETURN(); \
493 fdf9b3e8 bellard
} \
494 fdf9b3e8 bellard
void OPPROTO op_##store##_##target##_T0 (void) \
495 fdf9b3e8 bellard
{ T0 = env->target;   RETURN(); \
496 fdf9b3e8 bellard
} \
497 fdf9b3e8 bellard
498 fdf9b3e8 bellard
    LDSTOPS(gbr, ldc, stc)
499 fdf9b3e8 bellard
    LDSTOPS(vbr, ldc, stc)
500 fdf9b3e8 bellard
    LDSTOPS(ssr, ldc, stc)
501 fdf9b3e8 bellard
    LDSTOPS(spc, ldc, stc)
502 fdf9b3e8 bellard
    LDSTOPS(sgr, ldc, stc)
503 fdf9b3e8 bellard
    LDSTOPS(dbr, ldc, stc)
504 fdf9b3e8 bellard
    LDSTOPS(mach, lds, sts)
505 fdf9b3e8 bellard
    LDSTOPS(macl, lds, sts)
506 fdf9b3e8 bellard
    LDSTOPS(pr, lds, sts)
507 eda9b09b bellard
    LDSTOPS(fpul, lds, sts)
508 eda9b09b bellard
509 eda9b09b bellard
void OPPROTO op_lds_T0_fpscr(void)
510 eda9b09b bellard
{
511 eda9b09b bellard
    env->fpscr = T0 & 0x003fffff;
512 eda9b09b bellard
    RETURN();
513 eda9b09b bellard
}
514 eda9b09b bellard
515 eda9b09b bellard
void OPPROTO op_sts_fpscr_T0(void)
516 eda9b09b bellard
{
517 eda9b09b bellard
    T0 = env->fpscr & 0x003fffff;
518 eda9b09b bellard
    RETURN();
519 eda9b09b bellard
}
520 fdf9b3e8 bellard
521 fdf9b3e8 bellard
void OPPROTO op_movt_rN(void)
522 fdf9b3e8 bellard
{
523 fdf9b3e8 bellard
    env->gregs[PARAM1] = env->sr & SR_T;
524 fdf9b3e8 bellard
    RETURN();
525 fdf9b3e8 bellard
}
526 fdf9b3e8 bellard
527 fdf9b3e8 bellard
void OPPROTO op_rotcl_Rn(void)
528 fdf9b3e8 bellard
{
529 fdf9b3e8 bellard
    helper_rotcl(&env->gregs[PARAM1]);
530 fdf9b3e8 bellard
    RETURN();
531 fdf9b3e8 bellard
}
532 fdf9b3e8 bellard
533 fdf9b3e8 bellard
void OPPROTO op_rotcr_Rn(void)
534 fdf9b3e8 bellard
{
535 fdf9b3e8 bellard
    helper_rotcr(&env->gregs[PARAM1]);
536 fdf9b3e8 bellard
    RETURN();
537 fdf9b3e8 bellard
}
538 fdf9b3e8 bellard
539 fdf9b3e8 bellard
void OPPROTO op_rotl_Rn(void)
540 fdf9b3e8 bellard
{
541 fdf9b3e8 bellard
    cond_t(env->gregs[PARAM1] & 0x80000000);
542 fdf9b3e8 bellard
    env->gregs[PARAM1] = (env->gregs[PARAM1] << 1) | (env->sr & SR_T);
543 fdf9b3e8 bellard
    RETURN();
544 fdf9b3e8 bellard
}
545 fdf9b3e8 bellard
546 fdf9b3e8 bellard
void OPPROTO op_rotr_Rn(void)
547 fdf9b3e8 bellard
{
548 fdf9b3e8 bellard
    cond_t(env->gregs[PARAM1] & 1);
549 fdf9b3e8 bellard
    env->gregs[PARAM1] = (env->gregs[PARAM1] >> 1) |
550 fdf9b3e8 bellard
        ((env->sr & SR_T) ? 0x80000000 : 0);
551 fdf9b3e8 bellard
    RETURN();
552 fdf9b3e8 bellard
}
553 fdf9b3e8 bellard
554 fdf9b3e8 bellard
void OPPROTO op_shal_Rn(void)
555 fdf9b3e8 bellard
{
556 fdf9b3e8 bellard
    cond_t(env->gregs[PARAM1] & 0x80000000);
557 fdf9b3e8 bellard
    env->gregs[PARAM1] <<= 1;
558 fdf9b3e8 bellard
    RETURN();
559 fdf9b3e8 bellard
}
560 fdf9b3e8 bellard
561 fdf9b3e8 bellard
void OPPROTO op_shar_Rn(void)
562 fdf9b3e8 bellard
{
563 fdf9b3e8 bellard
    cond_t(env->gregs[PARAM1] & 1);
564 a5d251bd ths
    env->gregs[PARAM1] >>= 1;
565 fdf9b3e8 bellard
    RETURN();
566 fdf9b3e8 bellard
}
567 fdf9b3e8 bellard
568 fdf9b3e8 bellard
void OPPROTO op_shlr_Rn(void)
569 fdf9b3e8 bellard
{
570 fdf9b3e8 bellard
    cond_t(env->gregs[PARAM1] & 1);
571 a5d251bd ths
    env->gregs[PARAM1] >>= 1;
572 fdf9b3e8 bellard
    RETURN();
573 fdf9b3e8 bellard
}
574 fdf9b3e8 bellard
575 fdf9b3e8 bellard
void OPPROTO op_shll2_Rn(void)
576 fdf9b3e8 bellard
{
577 fdf9b3e8 bellard
    env->gregs[PARAM1] <<= 2;
578 fdf9b3e8 bellard
    RETURN();
579 fdf9b3e8 bellard
}
580 fdf9b3e8 bellard
581 fdf9b3e8 bellard
void OPPROTO op_shll8_Rn(void)
582 fdf9b3e8 bellard
{
583 fdf9b3e8 bellard
    env->gregs[PARAM1] <<= 8;
584 fdf9b3e8 bellard
    RETURN();
585 fdf9b3e8 bellard
}
586 fdf9b3e8 bellard
587 fdf9b3e8 bellard
void OPPROTO op_shll16_Rn(void)
588 fdf9b3e8 bellard
{
589 fdf9b3e8 bellard
    env->gregs[PARAM1] <<= 16;
590 fdf9b3e8 bellard
    RETURN();
591 fdf9b3e8 bellard
}
592 fdf9b3e8 bellard
593 fdf9b3e8 bellard
void OPPROTO op_shlr2_Rn(void)
594 fdf9b3e8 bellard
{
595 a5d251bd ths
    env->gregs[PARAM1] >>= 2;
596 fdf9b3e8 bellard
    RETURN();
597 fdf9b3e8 bellard
}
598 fdf9b3e8 bellard
599 fdf9b3e8 bellard
void OPPROTO op_shlr8_Rn(void)
600 fdf9b3e8 bellard
{
601 a5d251bd ths
    env->gregs[PARAM1] >>= 8;
602 fdf9b3e8 bellard
    RETURN();
603 fdf9b3e8 bellard
}
604 fdf9b3e8 bellard
605 fdf9b3e8 bellard
void OPPROTO op_shlr16_Rn(void)
606 fdf9b3e8 bellard
{
607 a5d251bd ths
    env->gregs[PARAM1] >>= 16;
608 fdf9b3e8 bellard
    RETURN();
609 fdf9b3e8 bellard
}
610 fdf9b3e8 bellard
611 fdf9b3e8 bellard
void OPPROTO op_tasb_rN(void)
612 fdf9b3e8 bellard
{
613 fdf9b3e8 bellard
    cond_t(*(int8_t *) env->gregs[PARAM1] == 0);
614 fdf9b3e8 bellard
    *(int8_t *) env->gregs[PARAM1] |= 0x80;
615 fdf9b3e8 bellard
    RETURN();
616 fdf9b3e8 bellard
}
617 fdf9b3e8 bellard
618 fdf9b3e8 bellard
void OPPROTO op_movl_T0_rN(void)
619 fdf9b3e8 bellard
{
620 fdf9b3e8 bellard
    env->gregs[PARAM1] = T0;
621 fdf9b3e8 bellard
    RETURN();
622 fdf9b3e8 bellard
}
623 fdf9b3e8 bellard
624 fdf9b3e8 bellard
void OPPROTO op_movl_T1_rN(void)
625 fdf9b3e8 bellard
{
626 fdf9b3e8 bellard
    env->gregs[PARAM1] = T1;
627 fdf9b3e8 bellard
    RETURN();
628 fdf9b3e8 bellard
}
629 fdf9b3e8 bellard
630 fdf9b3e8 bellard
void OPPROTO op_movb_rN_T0(void)
631 fdf9b3e8 bellard
{
632 fdf9b3e8 bellard
    T0 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
633 fdf9b3e8 bellard
    RETURN();
634 fdf9b3e8 bellard
}
635 fdf9b3e8 bellard
636 fdf9b3e8 bellard
void OPPROTO op_movub_rN_T0(void)
637 fdf9b3e8 bellard
{
638 fdf9b3e8 bellard
    T0 = env->gregs[PARAM1] & 0xff;
639 fdf9b3e8 bellard
    RETURN();
640 fdf9b3e8 bellard
}
641 fdf9b3e8 bellard
642 fdf9b3e8 bellard
void OPPROTO op_movw_rN_T0(void)
643 fdf9b3e8 bellard
{
644 fdf9b3e8 bellard
    T0 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
645 fdf9b3e8 bellard
    RETURN();
646 fdf9b3e8 bellard
}
647 fdf9b3e8 bellard
648 fdf9b3e8 bellard
void OPPROTO op_movuw_rN_T0(void)
649 fdf9b3e8 bellard
{
650 fdf9b3e8 bellard
    T0 = env->gregs[PARAM1] & 0xffff;
651 fdf9b3e8 bellard
    RETURN();
652 fdf9b3e8 bellard
}
653 fdf9b3e8 bellard
654 fdf9b3e8 bellard
void OPPROTO op_movl_rN_T0(void)
655 fdf9b3e8 bellard
{
656 fdf9b3e8 bellard
    T0 = env->gregs[PARAM1];
657 fdf9b3e8 bellard
    RETURN();
658 fdf9b3e8 bellard
}
659 fdf9b3e8 bellard
660 fdf9b3e8 bellard
void OPPROTO op_movb_rN_T1(void)
661 fdf9b3e8 bellard
{
662 fdf9b3e8 bellard
    T1 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
663 fdf9b3e8 bellard
    RETURN();
664 fdf9b3e8 bellard
}
665 fdf9b3e8 bellard
666 fdf9b3e8 bellard
void OPPROTO op_movub_rN_T1(void)
667 fdf9b3e8 bellard
{
668 fdf9b3e8 bellard
    T1 = env->gregs[PARAM1] & 0xff;
669 fdf9b3e8 bellard
    RETURN();
670 fdf9b3e8 bellard
}
671 fdf9b3e8 bellard
672 fdf9b3e8 bellard
void OPPROTO op_movw_rN_T1(void)
673 fdf9b3e8 bellard
{
674 fdf9b3e8 bellard
    T1 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
675 fdf9b3e8 bellard
    RETURN();
676 fdf9b3e8 bellard
}
677 fdf9b3e8 bellard
678 fdf9b3e8 bellard
void OPPROTO op_movuw_rN_T1(void)
679 fdf9b3e8 bellard
{
680 fdf9b3e8 bellard
    T1 = env->gregs[PARAM1] & 0xffff;
681 fdf9b3e8 bellard
    RETURN();
682 fdf9b3e8 bellard
}
683 fdf9b3e8 bellard
684 fdf9b3e8 bellard
void OPPROTO op_movl_rN_T1(void)
685 fdf9b3e8 bellard
{
686 fdf9b3e8 bellard
    T1 = env->gregs[PARAM1];
687 fdf9b3e8 bellard
    RETURN();
688 fdf9b3e8 bellard
}
689 fdf9b3e8 bellard
690 fdf9b3e8 bellard
void OPPROTO op_movl_imm_rN(void)
691 fdf9b3e8 bellard
{
692 fdf9b3e8 bellard
    env->gregs[PARAM2] = PARAM1;
693 fdf9b3e8 bellard
    RETURN();
694 fdf9b3e8 bellard
}
695 fdf9b3e8 bellard
696 eda9b09b bellard
void OPPROTO op_fmov_frN_FT0(void)
697 eda9b09b bellard
{
698 eda9b09b bellard
    FT0 = *(float32 *)&env->fregs[PARAM1];
699 eda9b09b bellard
    RETURN();
700 eda9b09b bellard
}
701 eda9b09b bellard
702 eda9b09b bellard
void OPPROTO op_fmov_drN_DT0(void)
703 eda9b09b bellard
{
704 eda9b09b bellard
    DT0 = *(float64 *)&env->fregs[PARAM1];
705 eda9b09b bellard
    RETURN();
706 eda9b09b bellard
}
707 eda9b09b bellard
708 eda9b09b bellard
void OPPROTO op_fmov_FT0_frN(void)
709 eda9b09b bellard
{
710 eda9b09b bellard
    *(float32 *)&env->fregs[PARAM1] = FT0;
711 eda9b09b bellard
    RETURN();
712 eda9b09b bellard
}
713 eda9b09b bellard
714 eda9b09b bellard
void OPPROTO op_fmov_DT0_drN(void)
715 eda9b09b bellard
{
716 eda9b09b bellard
    *(float64 *)&env->fregs[PARAM1] = DT0;
717 eda9b09b bellard
    RETURN();
718 eda9b09b bellard
}
719 eda9b09b bellard
720 fdf9b3e8 bellard
void OPPROTO op_dec1_rN(void)
721 fdf9b3e8 bellard
{
722 fdf9b3e8 bellard
    env->gregs[PARAM1] -= 1;
723 fdf9b3e8 bellard
    RETURN();
724 fdf9b3e8 bellard
}
725 fdf9b3e8 bellard
726 fdf9b3e8 bellard
void OPPROTO op_dec2_rN(void)
727 fdf9b3e8 bellard
{
728 fdf9b3e8 bellard
    env->gregs[PARAM1] -= 2;
729 fdf9b3e8 bellard
    RETURN();
730 fdf9b3e8 bellard
}
731 fdf9b3e8 bellard
732 fdf9b3e8 bellard
void OPPROTO op_dec4_rN(void)
733 fdf9b3e8 bellard
{
734 fdf9b3e8 bellard
    env->gregs[PARAM1] -= 4;
735 fdf9b3e8 bellard
    RETURN();
736 fdf9b3e8 bellard
}
737 fdf9b3e8 bellard
738 eda9b09b bellard
void OPPROTO op_dec8_rN(void)
739 eda9b09b bellard
{
740 0a618140 ths
    env->gregs[PARAM1] -= 8;
741 eda9b09b bellard
    RETURN();
742 eda9b09b bellard
}
743 eda9b09b bellard
744 fdf9b3e8 bellard
void OPPROTO op_inc1_rN(void)
745 fdf9b3e8 bellard
{
746 fdf9b3e8 bellard
    env->gregs[PARAM1] += 1;
747 fdf9b3e8 bellard
    RETURN();
748 fdf9b3e8 bellard
}
749 fdf9b3e8 bellard
750 fdf9b3e8 bellard
void OPPROTO op_inc2_rN(void)
751 fdf9b3e8 bellard
{
752 fdf9b3e8 bellard
    env->gregs[PARAM1] += 2;
753 fdf9b3e8 bellard
    RETURN();
754 fdf9b3e8 bellard
}
755 fdf9b3e8 bellard
756 fdf9b3e8 bellard
void OPPROTO op_inc4_rN(void)
757 fdf9b3e8 bellard
{
758 fdf9b3e8 bellard
    env->gregs[PARAM1] += 4;
759 fdf9b3e8 bellard
    RETURN();
760 fdf9b3e8 bellard
}
761 fdf9b3e8 bellard
762 eda9b09b bellard
void OPPROTO op_inc8_rN(void)
763 eda9b09b bellard
{
764 0a618140 ths
    env->gregs[PARAM1] += 8;
765 eda9b09b bellard
    RETURN();
766 eda9b09b bellard
}
767 eda9b09b bellard
768 fdf9b3e8 bellard
void OPPROTO op_add_T0_rN(void)
769 fdf9b3e8 bellard
{
770 fdf9b3e8 bellard
    env->gregs[PARAM1] += T0;
771 fdf9b3e8 bellard
    RETURN();
772 fdf9b3e8 bellard
}
773 fdf9b3e8 bellard
774 fdf9b3e8 bellard
void OPPROTO op_sub_T0_rN(void)
775 fdf9b3e8 bellard
{
776 fdf9b3e8 bellard
    env->gregs[PARAM1] -= T0;
777 fdf9b3e8 bellard
    RETURN();
778 fdf9b3e8 bellard
}
779 fdf9b3e8 bellard
780 fdf9b3e8 bellard
void OPPROTO op_and_T0_rN(void)
781 fdf9b3e8 bellard
{
782 fdf9b3e8 bellard
    env->gregs[PARAM1] &= T0;
783 fdf9b3e8 bellard
    RETURN();
784 fdf9b3e8 bellard
}
785 fdf9b3e8 bellard
786 fdf9b3e8 bellard
void OPPROTO op_or_T0_rN(void)
787 fdf9b3e8 bellard
{
788 fdf9b3e8 bellard
    env->gregs[PARAM1] |= T0;
789 fdf9b3e8 bellard
    RETURN();
790 fdf9b3e8 bellard
}
791 fdf9b3e8 bellard
792 fdf9b3e8 bellard
void OPPROTO op_xor_T0_rN(void)
793 fdf9b3e8 bellard
{
794 fdf9b3e8 bellard
    env->gregs[PARAM1] ^= T0;
795 fdf9b3e8 bellard
    RETURN();
796 fdf9b3e8 bellard
}
797 fdf9b3e8 bellard
798 fdf9b3e8 bellard
void OPPROTO op_add_rN_T0(void)
799 fdf9b3e8 bellard
{
800 fdf9b3e8 bellard
    T0 += env->gregs[PARAM1];
801 fdf9b3e8 bellard
    RETURN();
802 fdf9b3e8 bellard
}
803 fdf9b3e8 bellard
804 fdf9b3e8 bellard
void OPPROTO op_add_rN_T1(void)
805 fdf9b3e8 bellard
{
806 fdf9b3e8 bellard
    T1 += env->gregs[PARAM1];
807 fdf9b3e8 bellard
    RETURN();
808 fdf9b3e8 bellard
}
809 fdf9b3e8 bellard
810 fdf9b3e8 bellard
void OPPROTO op_add_imm_rN(void)
811 fdf9b3e8 bellard
{
812 fdf9b3e8 bellard
    env->gregs[PARAM2] += PARAM1;
813 fdf9b3e8 bellard
    RETURN();
814 fdf9b3e8 bellard
}
815 fdf9b3e8 bellard
816 fdf9b3e8 bellard
void OPPROTO op_and_imm_rN(void)
817 fdf9b3e8 bellard
{
818 fdf9b3e8 bellard
    env->gregs[PARAM2] &= PARAM1;
819 fdf9b3e8 bellard
    RETURN();
820 fdf9b3e8 bellard
}
821 fdf9b3e8 bellard
822 fdf9b3e8 bellard
void OPPROTO op_or_imm_rN(void)
823 fdf9b3e8 bellard
{
824 fdf9b3e8 bellard
    env->gregs[PARAM2] |= PARAM1;
825 fdf9b3e8 bellard
    RETURN();
826 fdf9b3e8 bellard
}
827 fdf9b3e8 bellard
828 fdf9b3e8 bellard
void OPPROTO op_xor_imm_rN(void)
829 fdf9b3e8 bellard
{
830 fdf9b3e8 bellard
    env->gregs[PARAM2] ^= PARAM1;
831 fdf9b3e8 bellard
    RETURN();
832 fdf9b3e8 bellard
}
833 fdf9b3e8 bellard
834 fdf9b3e8 bellard
void OPPROTO op_dt_rN(void)
835 fdf9b3e8 bellard
{
836 fdf9b3e8 bellard
    cond_t((--env->gregs[PARAM1]) == 0);
837 fdf9b3e8 bellard
    RETURN();
838 fdf9b3e8 bellard
}
839 fdf9b3e8 bellard
840 fdf9b3e8 bellard
void OPPROTO op_tst_imm_rN(void)
841 fdf9b3e8 bellard
{
842 fdf9b3e8 bellard
    cond_t((env->gregs[PARAM2] & PARAM1) == 0);
843 fdf9b3e8 bellard
    RETURN();
844 fdf9b3e8 bellard
}
845 fdf9b3e8 bellard
846 fdf9b3e8 bellard
void OPPROTO op_movl_T0_T1(void)
847 fdf9b3e8 bellard
{
848 fdf9b3e8 bellard
    T1 = T0;
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    RETURN();
850 fdf9b3e8 bellard
}
851 fdf9b3e8 bellard
852 eda9b09b bellard
void OPPROTO op_movl_fpul_FT0(void)
853 eda9b09b bellard
{
854 eda9b09b bellard
    FT0 = *(float32 *)&env->fpul;
855 eda9b09b bellard
    RETURN();
856 eda9b09b bellard
}
857 eda9b09b bellard
858 eda9b09b bellard
void OPPROTO op_movl_FT0_fpul(void)
859 eda9b09b bellard
{
860 eda9b09b bellard
    *(float32 *)&env->fpul = FT0;
861 eda9b09b bellard
    RETURN();
862 eda9b09b bellard
}
863 eda9b09b bellard
864 fdf9b3e8 bellard
void OPPROTO op_goto_tb0(void)
865 fdf9b3e8 bellard
{
866 fdf9b3e8 bellard
    GOTO_TB(op_goto_tb0, PARAM1, 0);
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    RETURN();
868 fdf9b3e8 bellard
}
869 fdf9b3e8 bellard
870 fdf9b3e8 bellard
void OPPROTO op_goto_tb1(void)
871 fdf9b3e8 bellard
{
872 fdf9b3e8 bellard
    GOTO_TB(op_goto_tb1, PARAM1, 1);
873 fdf9b3e8 bellard
    RETURN();
874 fdf9b3e8 bellard
}
875 fdf9b3e8 bellard
876 fdf9b3e8 bellard
void OPPROTO op_movl_imm_PC(void)
877 fdf9b3e8 bellard
{
878 fdf9b3e8 bellard
    env->pc = PARAM1;
879 fdf9b3e8 bellard
    RETURN();
880 fdf9b3e8 bellard
}
881 fdf9b3e8 bellard
882 fdf9b3e8 bellard
void OPPROTO op_jT(void)
883 fdf9b3e8 bellard
{
884 fdf9b3e8 bellard
    if (env->sr & SR_T)
885 fdf9b3e8 bellard
        GOTO_LABEL_PARAM(1);
886 fdf9b3e8 bellard
    RETURN();
887 fdf9b3e8 bellard
}
888 fdf9b3e8 bellard
889 9c2a9ea1 pbrook
void OPPROTO op_jdelayed(void)
890 fdf9b3e8 bellard
{
891 9c2a9ea1 pbrook
    uint32_t flags;
892 9c2a9ea1 pbrook
    flags = env->flags;
893 9c2a9ea1 pbrook
    env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
894 9c2a9ea1 pbrook
    if (flags & DELAY_SLOT)
895 fdf9b3e8 bellard
        GOTO_LABEL_PARAM(1);
896 fdf9b3e8 bellard
    RETURN();
897 fdf9b3e8 bellard
}
898 fdf9b3e8 bellard
899 fdf9b3e8 bellard
void OPPROTO op_movl_delayed_pc_PC(void)
900 fdf9b3e8 bellard
{
901 fdf9b3e8 bellard
    env->pc = env->delayed_pc;
902 fdf9b3e8 bellard
    RETURN();
903 fdf9b3e8 bellard
}
904 fdf9b3e8 bellard
905 fdf9b3e8 bellard
void OPPROTO op_addl_GBR_T0(void)
906 fdf9b3e8 bellard
{
907 fdf9b3e8 bellard
    T0 += env->gbr;
908 fdf9b3e8 bellard
    RETURN();
909 fdf9b3e8 bellard
}
910 fdf9b3e8 bellard
911 fdf9b3e8 bellard
void OPPROTO op_and_imm_T0(void)
912 fdf9b3e8 bellard
{
913 fdf9b3e8 bellard
    T0 &= PARAM1;
914 fdf9b3e8 bellard
    RETURN();
915 fdf9b3e8 bellard
}
916 fdf9b3e8 bellard
917 fdf9b3e8 bellard
void OPPROTO op_or_imm_T0(void)
918 fdf9b3e8 bellard
{
919 fdf9b3e8 bellard
    T0 |= PARAM1;
920 fdf9b3e8 bellard
    RETURN();
921 fdf9b3e8 bellard
}
922 fdf9b3e8 bellard
923 fdf9b3e8 bellard
void OPPROTO op_xor_imm_T0(void)
924 fdf9b3e8 bellard
{
925 fdf9b3e8 bellard
    T0 ^= PARAM1;
926 fdf9b3e8 bellard
    RETURN();
927 fdf9b3e8 bellard
}
928 fdf9b3e8 bellard
929 fdf9b3e8 bellard
void OPPROTO op_tst_imm_T0(void)
930 fdf9b3e8 bellard
{
931 fdf9b3e8 bellard
    cond_t((T0 & PARAM1) == 0);
932 fdf9b3e8 bellard
    RETURN();
933 fdf9b3e8 bellard
}
934 fdf9b3e8 bellard
935 fdf9b3e8 bellard
void OPPROTO op_raise_illegal_instruction(void)
936 fdf9b3e8 bellard
{
937 fdf9b3e8 bellard
    env->exception_index = 0x180;
938 fdf9b3e8 bellard
    do_raise_exception();
939 fdf9b3e8 bellard
    RETURN();
940 fdf9b3e8 bellard
}
941 fdf9b3e8 bellard
942 fdf9b3e8 bellard
void OPPROTO op_raise_slot_illegal_instruction(void)
943 fdf9b3e8 bellard
{
944 fdf9b3e8 bellard
    env->exception_index = 0x1a0;
945 fdf9b3e8 bellard
    do_raise_exception();
946 fdf9b3e8 bellard
    RETURN();
947 fdf9b3e8 bellard
}
948 fdf9b3e8 bellard
949 fdf9b3e8 bellard
void OPPROTO op_debug(void)
950 fdf9b3e8 bellard
{
951 fdf9b3e8 bellard
    env->exception_index = EXCP_DEBUG;
952 fdf9b3e8 bellard
    cpu_loop_exit();
953 fdf9b3e8 bellard
}
954 fdf9b3e8 bellard
955 fdf9b3e8 bellard
/* Load and store */
956 fdf9b3e8 bellard
#define MEMSUFFIX _raw
957 fdf9b3e8 bellard
#include "op_mem.c"
958 fdf9b3e8 bellard
#undef MEMSUFFIX
959 fdf9b3e8 bellard
#if !defined(CONFIG_USER_ONLY)
960 fdf9b3e8 bellard
#define MEMSUFFIX _user
961 fdf9b3e8 bellard
#include "op_mem.c"
962 fdf9b3e8 bellard
#undef MEMSUFFIX
963 fdf9b3e8 bellard
964 fdf9b3e8 bellard
#define MEMSUFFIX _kernel
965 fdf9b3e8 bellard
#include "op_mem.c"
966 fdf9b3e8 bellard
#undef MEMSUFFIX
967 fdf9b3e8 bellard
#endif