Revision 4cc35614 target-arm/cpu.c

b/target-arm/cpu.c
94 94 
        /* Userspace expects access to CTL_EL0 and the cache ops */
95 95 
        env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI;
96 96 
#else
97 
        env->pstate = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F
98 
            | PSTATE_MODE_EL1h;
97 
        env->pstate = PSTATE_MODE_EL1h;
99 98 
#endif
100 99 
    }
101 100 

  		





  ......




  110
  109
  
    
    }


  		





  111
  110
  
    
#else


  		





  112
  111
  
    
    /* SVC mode with interrupts disabled.  */


  		





  113
  
  
    
    env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;


  		





  
  112
  
    
    env->uncached_cpsr = ARM_CPU_MODE_SVC;


  		





  
  113
  
    
    env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;


  		





  114
  114
  
    
    /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is


  		





  115
  115
  
    
       clear at reset.  Initial SP and PC are loaded from ROM.  */


  		





  116
  116
  
    
    if (IS_M(env)) {


  		





  117
  117
  
    
        uint32_t pc;


  		





  118
  118
  
    
        uint8_t *rom;


  		





  119
  
  
    
        env->uncached_cpsr &= ~CPSR_I;


  		





  
  119
  
    
        env->daif &= ~PSTATE_I;


  		





  120
  120
  
    
        rom = rom_ptr(0);


  		





  121
  121
  
    
        if (rom) {


  		





  122
  122
  
    
            /* We should really use ldl_phys here, in case the guest


  		












Also available in:
  Unified diff