Revision 4cc35614 target-arm/helper.c
| b/target-arm/helper.c | ||
|---|---|---|
| 2475 | 2475 |
(env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
| 2476 | 2476 |
| (env->thumb << 5) | ((env->condexec_bits & 3) << 25) |
| 2477 | 2477 |
| ((env->condexec_bits & 0xfc) << 8) |
| 2478 |
| (env->GE << 16); |
|
| 2478 |
| (env->GE << 16) | env->daif;
|
|
| 2479 | 2479 |
} |
| 2480 | 2480 |
|
| 2481 | 2481 |
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) |
| ... | ... | |
| 2502 | 2502 |
env->GE = (val >> 16) & 0xf; |
| 2503 | 2503 |
} |
| 2504 | 2504 |
|
| 2505 |
env->daif &= ~(CPSR_AIF & mask); |
|
| 2506 |
env->daif |= val & CPSR_AIF & mask; |
|
| 2507 |
|
|
| 2505 | 2508 |
if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
|
| 2506 | 2509 |
if (bad_mode_switch(env, val & CPSR_M)) {
|
| 2507 | 2510 |
/* Attempt to switch to an invalid mode: this is UNPREDICTABLE. |
| ... | ... | |
| 2963 | 2966 |
env->condexec_bits = 0; |
| 2964 | 2967 |
/* Switch to the new mode, and to the correct instruction set. */ |
| 2965 | 2968 |
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
| 2966 |
env->uncached_cpsr |= mask;
|
|
| 2969 |
env->daif |= mask;
|
|
| 2967 | 2970 |
/* this is a lie, as the was no c1_sys on V4T/V5, but who cares |
| 2968 | 2971 |
* and we should just guard the thumb mode on V4 */ |
| 2969 | 2972 |
if (arm_feature(env, ARM_FEATURE_V4T)) {
|
| ... | ... | |
| 3636 | 3639 |
case 9: /* PSP */ |
| 3637 | 3640 |
return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; |
| 3638 | 3641 |
case 16: /* PRIMASK */ |
| 3639 |
return (env->uncached_cpsr & CPSR_I) != 0;
|
|
| 3642 |
return (env->daif & PSTATE_I) != 0;
|
|
| 3640 | 3643 |
case 17: /* BASEPRI */ |
| 3641 | 3644 |
case 18: /* BASEPRI_MAX */ |
| 3642 | 3645 |
return env->v7m.basepri; |
| 3643 | 3646 |
case 19: /* FAULTMASK */ |
| 3644 |
return (env->uncached_cpsr & CPSR_F) != 0;
|
|
| 3647 |
return (env->daif & PSTATE_F) != 0;
|
|
| 3645 | 3648 |
case 20: /* CONTROL */ |
| 3646 | 3649 |
return env->v7m.control; |
| 3647 | 3650 |
default: |
| ... | ... | |
| 3688 | 3691 |
env->v7m.other_sp = val; |
| 3689 | 3692 |
break; |
| 3690 | 3693 |
case 16: /* PRIMASK */ |
| 3691 |
if (val & 1) |
|
| 3692 |
env->uncached_cpsr |= CPSR_I; |
|
| 3693 |
else |
|
| 3694 |
env->uncached_cpsr &= ~CPSR_I; |
|
| 3694 |
if (val & 1) {
|
|
| 3695 |
env->daif |= PSTATE_I; |
|
| 3696 |
} else {
|
|
| 3697 |
env->daif &= ~PSTATE_I; |
|
| 3698 |
} |
|
| 3695 | 3699 |
break; |
| 3696 | 3700 |
case 17: /* BASEPRI */ |
| 3697 | 3701 |
env->v7m.basepri = val & 0xff; |
| ... | ... | |
| 3702 | 3706 |
env->v7m.basepri = val; |
| 3703 | 3707 |
break; |
| 3704 | 3708 |
case 19: /* FAULTMASK */ |
| 3705 |
if (val & 1) |
|
| 3706 |
env->uncached_cpsr |= CPSR_F; |
|
| 3707 |
else |
|
| 3708 |
env->uncached_cpsr &= ~CPSR_F; |
|
| 3709 |
if (val & 1) {
|
|
| 3710 |
env->daif |= PSTATE_F; |
|
| 3711 |
} else {
|
|
| 3712 |
env->daif &= ~PSTATE_F; |
|
| 3713 |
} |
|
| 3709 | 3714 |
break; |
| 3710 | 3715 |
case 20: /* CONTROL */ |
| 3711 | 3716 |
env->v7m.control = val & 3; |
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