Revision 4d2c2b77
| b/target-sparc/cpu.h | ||
|---|---|---|
| 403 | 403 |
uint32_t mmuregs[32]; |
| 404 | 404 |
uint64_t mxccdata[4]; |
| 405 | 405 |
uint64_t mxccregs[8]; |
| 406 |
uint32_t mmubpctrv, mmubpctrc, mmubpctrs; |
|
| 407 |
uint64_t mmubpaction; |
|
| 406 | 408 |
uint64_t mmubpregs[4]; |
| 407 | 409 |
uint64_t prom_addr; |
| 408 | 410 |
#endif |
| ... | ... | |
| 521 | 523 |
#define cpu_signal_handler cpu_sparc_signal_handler |
| 522 | 524 |
#define cpu_list sparc_cpu_list |
| 523 | 525 |
|
| 524 |
#define CPU_SAVE_VERSION 6
|
|
| 526 |
#define CPU_SAVE_VERSION 7
|
|
| 525 | 527 |
|
| 526 | 528 |
/* MMU modes definitions */ |
| 527 | 529 |
#if defined (TARGET_SPARC64) |
| b/target-sparc/machine.c | ||
|---|---|---|
| 45 | 45 |
/* MMU */ |
| 46 | 46 |
for (i = 0; i < 32; i++) |
| 47 | 47 |
qemu_put_be32s(f, &env->mmuregs[i]); |
| 48 |
for (i = 0; i < 4; i++) {
|
|
| 49 |
qemu_put_be64s(f, &env->mxccdata[i]); |
|
| 50 |
} |
|
| 51 |
for (i = 0; i < 8; i++) {
|
|
| 52 |
qemu_put_be64s(f, &env->mxccregs[i]); |
|
| 53 |
} |
|
| 54 |
qemu_put_be32s(f, &env->mmubpctrv); |
|
| 55 |
qemu_put_be32s(f, &env->mmubpctrc); |
|
| 56 |
qemu_put_be32s(f, &env->mmubpctrs); |
|
| 57 |
qemu_put_be64s(f, &env->mmubpaction); |
|
| 58 |
for (i = 0; i < 4; i++) {
|
|
| 59 |
qemu_put_be64s(f, &env->mmubpregs[i]); |
|
| 60 |
} |
|
| 48 | 61 |
#else |
| 49 | 62 |
qemu_put_be64s(f, &env->lsu); |
| 50 | 63 |
for (i = 0; i < 16; i++) {
|
| ... | ... | |
| 141 | 154 |
/* MMU */ |
| 142 | 155 |
for (i = 0; i < 32; i++) |
| 143 | 156 |
qemu_get_be32s(f, &env->mmuregs[i]); |
| 157 |
for (i = 0; i < 4; i++) {
|
|
| 158 |
qemu_get_be64s(f, &env->mxccdata[i]); |
|
| 159 |
} |
|
| 160 |
for (i = 0; i < 8; i++) {
|
|
| 161 |
qemu_get_be64s(f, &env->mxccregs[i]); |
|
| 162 |
} |
|
| 163 |
qemu_get_be32s(f, &env->mmubpctrv); |
|
| 164 |
qemu_get_be32s(f, &env->mmubpctrc); |
|
| 165 |
qemu_get_be32s(f, &env->mmubpctrs); |
|
| 166 |
qemu_get_be64s(f, &env->mmubpaction); |
|
| 167 |
for (i = 0; i < 4; i++) {
|
|
| 168 |
qemu_get_be64s(f, &env->mmubpregs[i]); |
|
| 169 |
} |
|
| 144 | 170 |
#else |
| 145 | 171 |
qemu_get_be64s(f, &env->lsu); |
| 146 | 172 |
for (i = 0; i < 16; i++) {
|
| b/target-sparc/op_helper.c | ||
|---|---|---|
| 1940 | 1940 |
case 0x31: // Turbosparc RAM snoop |
| 1941 | 1941 |
case 0x32: // Turbosparc page table descriptor diagnostic |
| 1942 | 1942 |
case 0x39: /* data cache diagnostic register */ |
| 1943 |
case 0x4c: /* SuperSPARC MMU Breakpoint Action register */ |
|
| 1944 | 1943 |
ret = 0; |
| 1945 | 1944 |
break; |
| 1946 | 1945 |
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */ |
| ... | ... | |
| 1966 | 1965 |
ret); |
| 1967 | 1966 |
} |
| 1968 | 1967 |
break; |
| 1968 |
case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ |
|
| 1969 |
ret = env->mmubpctrv; |
|
| 1970 |
break; |
|
| 1971 |
case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ |
|
| 1972 |
ret = env->mmubpctrc; |
|
| 1973 |
break; |
|
| 1974 |
case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ |
|
| 1975 |
ret = env->mmubpctrs; |
|
| 1976 |
break; |
|
| 1977 |
case 0x4c: /* SuperSPARC MMU Breakpoint Action */ |
|
| 1978 |
ret = env->mmubpaction; |
|
| 1979 |
break; |
|
| 1969 | 1980 |
case 8: /* User code access, XXX */ |
| 1970 | 1981 |
default: |
| 1971 | 1982 |
do_unassigned_access(addr, 0, 0, asi, size); |
| ... | ... | |
| 2304 | 2315 |
// descriptor diagnostic |
| 2305 | 2316 |
case 0x36: /* I-cache flash clear */ |
| 2306 | 2317 |
case 0x37: /* D-cache flash clear */ |
| 2307 |
case 0x4c: /* breakpoint action */ |
|
| 2308 | 2318 |
break; |
| 2309 | 2319 |
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/ |
| 2310 | 2320 |
{
|
| ... | ... | |
| 2328 | 2338 |
env->mmuregs[reg]); |
| 2329 | 2339 |
} |
| 2330 | 2340 |
break; |
| 2341 |
case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ |
|
| 2342 |
env->mmubpctrv = val & 0xffffffff; |
|
| 2343 |
break; |
|
| 2344 |
case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ |
|
| 2345 |
env->mmubpctrc = val & 0x3; |
|
| 2346 |
break; |
|
| 2347 |
case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ |
|
| 2348 |
env->mmubpctrs = val & 0x3; |
|
| 2349 |
break; |
|
| 2350 |
case 0x4c: /* SuperSPARC MMU Breakpoint Action */ |
|
| 2351 |
env->mmubpaction = val & 0x1fff; |
|
| 2352 |
break; |
|
| 2331 | 2353 |
case 8: /* User code access, XXX */ |
| 2332 | 2354 |
case 9: /* Supervisor code access, XXX */ |
| 2333 | 2355 |
default: |
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