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1 | 2328826b | Max Filippov | /*
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2 | 2328826b | Max Filippov | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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3 | 2328826b | Max Filippov | * All rights reserved.
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4 | 2328826b | Max Filippov | *
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5 | 2328826b | Max Filippov | * Redistribution and use in source and binary forms, with or without
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6 | 2328826b | Max Filippov | * modification, are permitted provided that the following conditions are met:
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7 | 2328826b | Max Filippov | * * Redistributions of source code must retain the above copyright
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8 | 2328826b | Max Filippov | * notice, this list of conditions and the following disclaimer.
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9 | 2328826b | Max Filippov | * * Redistributions in binary form must reproduce the above copyright
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10 | 2328826b | Max Filippov | * notice, this list of conditions and the following disclaimer in the
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11 | 2328826b | Max Filippov | * documentation and/or other materials provided with the distribution.
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12 | 2328826b | Max Filippov | * * Neither the name of the Open Source and Linux Lab nor the
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13 | 2328826b | Max Filippov | * names of its contributors may be used to endorse or promote products
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14 | 2328826b | Max Filippov | * derived from this software without specific prior written permission.
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15 | 2328826b | Max Filippov | *
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16 | 2328826b | Max Filippov | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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17 | 2328826b | Max Filippov | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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18 | 2328826b | Max Filippov | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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19 | 2328826b | Max Filippov | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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20 | 2328826b | Max Filippov | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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21 | 2328826b | Max Filippov | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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22 | 2328826b | Max Filippov | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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23 | 2328826b | Max Filippov | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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24 | 2328826b | Max Filippov | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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25 | 2328826b | Max Filippov | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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26 | 2328826b | Max Filippov | */
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27 | 2328826b | Max Filippov | |
28 | 2328826b | Max Filippov | #ifndef CPU_XTENSA_H
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29 | 2328826b | Max Filippov | #define CPU_XTENSA_H
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30 | 2328826b | Max Filippov | |
31 | 2328826b | Max Filippov | #define TARGET_LONG_BITS 32 |
32 | 2328826b | Max Filippov | #define ELF_MACHINE EM_XTENSA
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33 | 2328826b | Max Filippov | |
34 | 2328826b | Max Filippov | #define CPUState struct CPUXtensaState |
35 | 2328826b | Max Filippov | |
36 | 2328826b | Max Filippov | #include "config.h" |
37 | 2328826b | Max Filippov | #include "qemu-common.h" |
38 | 2328826b | Max Filippov | #include "cpu-defs.h" |
39 | 2328826b | Max Filippov | |
40 | 2328826b | Max Filippov | #define TARGET_HAS_ICE 1 |
41 | 2328826b | Max Filippov | |
42 | 2328826b | Max Filippov | #define NB_MMU_MODES 4 |
43 | 2328826b | Max Filippov | |
44 | 2328826b | Max Filippov | #define TARGET_PHYS_ADDR_SPACE_BITS 32 |
45 | 2328826b | Max Filippov | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
46 | 2328826b | Max Filippov | #define TARGET_PAGE_BITS 12 |
47 | 2328826b | Max Filippov | |
48 | dedc5eae | Max Filippov | enum {
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49 | dedc5eae | Max Filippov | /* Additional instructions */
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50 | dedc5eae | Max Filippov | XTENSA_OPTION_CODE_DENSITY, |
51 | dedc5eae | Max Filippov | XTENSA_OPTION_LOOP, |
52 | dedc5eae | Max Filippov | XTENSA_OPTION_EXTENDED_L32R, |
53 | dedc5eae | Max Filippov | XTENSA_OPTION_16_BIT_IMUL, |
54 | dedc5eae | Max Filippov | XTENSA_OPTION_32_BIT_IMUL, |
55 | dedc5eae | Max Filippov | XTENSA_OPTION_32_BIT_IDIV, |
56 | dedc5eae | Max Filippov | XTENSA_OPTION_MAC16, |
57 | dedc5eae | Max Filippov | XTENSA_OPTION_MISC_OP, |
58 | dedc5eae | Max Filippov | XTENSA_OPTION_COPROCESSOR, |
59 | dedc5eae | Max Filippov | XTENSA_OPTION_BOOLEAN, |
60 | dedc5eae | Max Filippov | XTENSA_OPTION_FP_COPROCESSOR, |
61 | dedc5eae | Max Filippov | XTENSA_OPTION_MP_SYNCHRO, |
62 | dedc5eae | Max Filippov | XTENSA_OPTION_CONDITIONAL_STORE, |
63 | dedc5eae | Max Filippov | |
64 | dedc5eae | Max Filippov | /* Interrupts and exceptions */
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65 | dedc5eae | Max Filippov | XTENSA_OPTION_EXCEPTION, |
66 | dedc5eae | Max Filippov | XTENSA_OPTION_RELOCATABLE_VECTOR, |
67 | dedc5eae | Max Filippov | XTENSA_OPTION_UNALIGNED_EXCEPTION, |
68 | dedc5eae | Max Filippov | XTENSA_OPTION_INTERRUPT, |
69 | dedc5eae | Max Filippov | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
70 | dedc5eae | Max Filippov | XTENSA_OPTION_TIMER_INTERRUPT, |
71 | dedc5eae | Max Filippov | |
72 | dedc5eae | Max Filippov | /* Local memory */
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73 | dedc5eae | Max Filippov | XTENSA_OPTION_ICACHE, |
74 | dedc5eae | Max Filippov | XTENSA_OPTION_ICACHE_TEST, |
75 | dedc5eae | Max Filippov | XTENSA_OPTION_ICACHE_INDEX_LOCK, |
76 | dedc5eae | Max Filippov | XTENSA_OPTION_DCACHE, |
77 | dedc5eae | Max Filippov | XTENSA_OPTION_DCACHE_TEST, |
78 | dedc5eae | Max Filippov | XTENSA_OPTION_DCACHE_INDEX_LOCK, |
79 | dedc5eae | Max Filippov | XTENSA_OPTION_IRAM, |
80 | dedc5eae | Max Filippov | XTENSA_OPTION_IROM, |
81 | dedc5eae | Max Filippov | XTENSA_OPTION_DRAM, |
82 | dedc5eae | Max Filippov | XTENSA_OPTION_DROM, |
83 | dedc5eae | Max Filippov | XTENSA_OPTION_XLMI, |
84 | dedc5eae | Max Filippov | XTENSA_OPTION_HW_ALIGNMENT, |
85 | dedc5eae | Max Filippov | XTENSA_OPTION_MEMORY_ECC_PARITY, |
86 | dedc5eae | Max Filippov | |
87 | dedc5eae | Max Filippov | /* Memory protection and translation */
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88 | dedc5eae | Max Filippov | XTENSA_OPTION_REGION_PROTECTION, |
89 | dedc5eae | Max Filippov | XTENSA_OPTION_REGION_TRANSLATION, |
90 | dedc5eae | Max Filippov | XTENSA_OPTION_MMU, |
91 | dedc5eae | Max Filippov | |
92 | dedc5eae | Max Filippov | /* Other */
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93 | dedc5eae | Max Filippov | XTENSA_OPTION_WINDOWED_REGISTER, |
94 | dedc5eae | Max Filippov | XTENSA_OPTION_PROCESSOR_INTERFACE, |
95 | dedc5eae | Max Filippov | XTENSA_OPTION_MISC_SR, |
96 | dedc5eae | Max Filippov | XTENSA_OPTION_THREAD_POINTER, |
97 | dedc5eae | Max Filippov | XTENSA_OPTION_PROCESSOR_ID, |
98 | dedc5eae | Max Filippov | XTENSA_OPTION_DEBUG, |
99 | dedc5eae | Max Filippov | XTENSA_OPTION_TRACE_PORT, |
100 | dedc5eae | Max Filippov | }; |
101 | dedc5eae | Max Filippov | |
102 | 2af3da91 | Max Filippov | enum {
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103 | 2af3da91 | Max Filippov | THREADPTR = 231,
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104 | 2af3da91 | Max Filippov | FCR = 232,
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105 | 2af3da91 | Max Filippov | FSR = 233,
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106 | 2af3da91 | Max Filippov | }; |
107 | 2af3da91 | Max Filippov | |
108 | 3580ecad | Max Filippov | enum {
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109 | 797d780b | Max Filippov | LBEG = 0,
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110 | 797d780b | Max Filippov | LEND = 1,
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111 | 797d780b | Max Filippov | LCOUNT = 2,
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112 | 3580ecad | Max Filippov | SAR = 3,
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113 | 4dd85b6b | Max Filippov | BR = 4,
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114 | 6ad6dbf7 | Max Filippov | LITBASE = 5,
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115 | 809377aa | Max Filippov | SCOMPARE1 = 12,
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116 | 553e44f9 | Max Filippov | WINDOW_BASE = 72,
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117 | 553e44f9 | Max Filippov | WINDOW_START = 73,
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118 | b67ea0cd | Max Filippov | PTEVADDR = 83,
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119 | b67ea0cd | Max Filippov | RASID = 90,
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120 | b67ea0cd | Max Filippov | ITLBCFG = 91,
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121 | b67ea0cd | Max Filippov | DTLBCFG = 92,
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122 | 40643d7c | Max Filippov | EPC1 = 177,
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123 | 40643d7c | Max Filippov | DEPC = 192,
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124 | b994e91b | Max Filippov | EPS2 = 194,
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125 | 40643d7c | Max Filippov | EXCSAVE1 = 209,
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126 | f3df4c04 | Max Filippov | CPENABLE = 224,
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127 | b994e91b | Max Filippov | INTSET = 226,
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128 | b994e91b | Max Filippov | INTCLEAR = 227,
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129 | b994e91b | Max Filippov | INTENABLE = 228,
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130 | f0a548b9 | Max Filippov | PS = 230,
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131 | 97836cee | Max Filippov | VECBASE = 231,
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132 | 40643d7c | Max Filippov | EXCCAUSE = 232,
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133 | b994e91b | Max Filippov | CCOUNT = 234,
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134 | f3df4c04 | Max Filippov | PRID = 235,
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135 | 40643d7c | Max Filippov | EXCVADDR = 238,
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136 | b994e91b | Max Filippov | CCOMPARE = 240,
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137 | 3580ecad | Max Filippov | }; |
138 | 3580ecad | Max Filippov | |
139 | f0a548b9 | Max Filippov | #define PS_INTLEVEL 0xf |
140 | f0a548b9 | Max Filippov | #define PS_INTLEVEL_SHIFT 0 |
141 | f0a548b9 | Max Filippov | |
142 | f0a548b9 | Max Filippov | #define PS_EXCM 0x10 |
143 | f0a548b9 | Max Filippov | #define PS_UM 0x20 |
144 | f0a548b9 | Max Filippov | |
145 | f0a548b9 | Max Filippov | #define PS_RING 0xc0 |
146 | f0a548b9 | Max Filippov | #define PS_RING_SHIFT 6 |
147 | f0a548b9 | Max Filippov | |
148 | f0a548b9 | Max Filippov | #define PS_OWB 0xf00 |
149 | f0a548b9 | Max Filippov | #define PS_OWB_SHIFT 8 |
150 | f0a548b9 | Max Filippov | |
151 | f0a548b9 | Max Filippov | #define PS_CALLINC 0x30000 |
152 | f0a548b9 | Max Filippov | #define PS_CALLINC_SHIFT 16 |
153 | f0a548b9 | Max Filippov | #define PS_CALLINC_LEN 2 |
154 | f0a548b9 | Max Filippov | |
155 | f0a548b9 | Max Filippov | #define PS_WOE 0x40000 |
156 | f0a548b9 | Max Filippov | |
157 | 553e44f9 | Max Filippov | #define MAX_NAREG 64 |
158 | b994e91b | Max Filippov | #define MAX_NINTERRUPT 32 |
159 | b994e91b | Max Filippov | #define MAX_NLEVEL 6 |
160 | b994e91b | Max Filippov | #define MAX_NNMI 1 |
161 | b994e91b | Max Filippov | #define MAX_NCCOMPARE 3 |
162 | b67ea0cd | Max Filippov | #define MAX_TLB_WAY_SIZE 8 |
163 | b67ea0cd | Max Filippov | |
164 | b67ea0cd | Max Filippov | #define REGION_PAGE_MASK 0xe0000000 |
165 | 553e44f9 | Max Filippov | |
166 | 40643d7c | Max Filippov | enum {
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167 | 40643d7c | Max Filippov | /* Static vectors */
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168 | 40643d7c | Max Filippov | EXC_RESET, |
169 | 40643d7c | Max Filippov | EXC_MEMORY_ERROR, |
170 | 40643d7c | Max Filippov | |
171 | 40643d7c | Max Filippov | /* Dynamic vectors */
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172 | 40643d7c | Max Filippov | EXC_WINDOW_OVERFLOW4, |
173 | 40643d7c | Max Filippov | EXC_WINDOW_UNDERFLOW4, |
174 | 40643d7c | Max Filippov | EXC_WINDOW_OVERFLOW8, |
175 | 40643d7c | Max Filippov | EXC_WINDOW_UNDERFLOW8, |
176 | 40643d7c | Max Filippov | EXC_WINDOW_OVERFLOW12, |
177 | 40643d7c | Max Filippov | EXC_WINDOW_UNDERFLOW12, |
178 | 40643d7c | Max Filippov | EXC_IRQ, |
179 | 40643d7c | Max Filippov | EXC_KERNEL, |
180 | 40643d7c | Max Filippov | EXC_USER, |
181 | 40643d7c | Max Filippov | EXC_DOUBLE, |
182 | 40643d7c | Max Filippov | EXC_MAX |
183 | 40643d7c | Max Filippov | }; |
184 | 40643d7c | Max Filippov | |
185 | 40643d7c | Max Filippov | enum {
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186 | 40643d7c | Max Filippov | ILLEGAL_INSTRUCTION_CAUSE = 0,
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187 | 40643d7c | Max Filippov | SYSCALL_CAUSE, |
188 | 40643d7c | Max Filippov | INSTRUCTION_FETCH_ERROR_CAUSE, |
189 | 40643d7c | Max Filippov | LOAD_STORE_ERROR_CAUSE, |
190 | 40643d7c | Max Filippov | LEVEL1_INTERRUPT_CAUSE, |
191 | 40643d7c | Max Filippov | ALLOCA_CAUSE, |
192 | 40643d7c | Max Filippov | INTEGER_DIVIDE_BY_ZERO_CAUSE, |
193 | 40643d7c | Max Filippov | PRIVILEGED_CAUSE = 8,
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194 | 40643d7c | Max Filippov | LOAD_STORE_ALIGNMENT_CAUSE, |
195 | 40643d7c | Max Filippov | |
196 | 40643d7c | Max Filippov | INSTR_PIF_DATA_ERROR_CAUSE = 12,
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197 | 40643d7c | Max Filippov | LOAD_STORE_PIF_DATA_ERROR_CAUSE, |
198 | 40643d7c | Max Filippov | INSTR_PIF_ADDR_ERROR_CAUSE, |
199 | 40643d7c | Max Filippov | LOAD_STORE_PIF_ADDR_ERROR_CAUSE, |
200 | 40643d7c | Max Filippov | |
201 | 40643d7c | Max Filippov | INST_TLB_MISS_CAUSE, |
202 | 40643d7c | Max Filippov | INST_TLB_MULTI_HIT_CAUSE, |
203 | 40643d7c | Max Filippov | INST_FETCH_PRIVILEGE_CAUSE, |
204 | 40643d7c | Max Filippov | INST_FETCH_PROHIBITED_CAUSE = 20,
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205 | 40643d7c | Max Filippov | LOAD_STORE_TLB_MISS_CAUSE = 24,
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206 | 40643d7c | Max Filippov | LOAD_STORE_TLB_MULTI_HIT_CAUSE, |
207 | 40643d7c | Max Filippov | LOAD_STORE_PRIVILEGE_CAUSE, |
208 | 40643d7c | Max Filippov | LOAD_PROHIBITED_CAUSE = 28,
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209 | 40643d7c | Max Filippov | STORE_PROHIBITED_CAUSE, |
210 | 40643d7c | Max Filippov | |
211 | 40643d7c | Max Filippov | COPROCESSOR0_DISABLED = 32,
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212 | 40643d7c | Max Filippov | }; |
213 | 40643d7c | Max Filippov | |
214 | b994e91b | Max Filippov | typedef enum { |
215 | b994e91b | Max Filippov | INTTYPE_LEVEL, |
216 | b994e91b | Max Filippov | INTTYPE_EDGE, |
217 | b994e91b | Max Filippov | INTTYPE_NMI, |
218 | b994e91b | Max Filippov | INTTYPE_SOFTWARE, |
219 | b994e91b | Max Filippov | INTTYPE_TIMER, |
220 | b994e91b | Max Filippov | INTTYPE_DEBUG, |
221 | b994e91b | Max Filippov | INTTYPE_WRITE_ERR, |
222 | b994e91b | Max Filippov | INTTYPE_MAX |
223 | b994e91b | Max Filippov | } interrupt_type; |
224 | b994e91b | Max Filippov | |
225 | b67ea0cd | Max Filippov | typedef struct xtensa_tlb_entry { |
226 | b67ea0cd | Max Filippov | uint32_t vaddr; |
227 | b67ea0cd | Max Filippov | uint32_t paddr; |
228 | b67ea0cd | Max Filippov | uint8_t asid; |
229 | b67ea0cd | Max Filippov | uint8_t attr; |
230 | b67ea0cd | Max Filippov | bool variable;
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231 | b67ea0cd | Max Filippov | } xtensa_tlb_entry; |
232 | b67ea0cd | Max Filippov | |
233 | b67ea0cd | Max Filippov | typedef struct xtensa_tlb { |
234 | b67ea0cd | Max Filippov | unsigned nways;
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235 | b67ea0cd | Max Filippov | const unsigned way_size[10]; |
236 | b67ea0cd | Max Filippov | bool varway56;
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237 | b67ea0cd | Max Filippov | unsigned nrefillentries;
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238 | b67ea0cd | Max Filippov | } xtensa_tlb; |
239 | b67ea0cd | Max Filippov | |
240 | ccfcaba6 | Max Filippov | typedef struct XtensaGdbReg { |
241 | ccfcaba6 | Max Filippov | int targno;
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242 | ccfcaba6 | Max Filippov | int type;
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243 | ccfcaba6 | Max Filippov | int group;
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244 | ccfcaba6 | Max Filippov | } XtensaGdbReg; |
245 | ccfcaba6 | Max Filippov | |
246 | ccfcaba6 | Max Filippov | typedef struct XtensaGdbRegmap { |
247 | ccfcaba6 | Max Filippov | int num_regs;
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248 | ccfcaba6 | Max Filippov | int num_core_regs;
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249 | ccfcaba6 | Max Filippov | /* PC + a + ar + sr + ur */
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250 | ccfcaba6 | Max Filippov | XtensaGdbReg reg[1 + 16 + 64 + 256 + 256]; |
251 | ccfcaba6 | Max Filippov | } XtensaGdbRegmap; |
252 | ccfcaba6 | Max Filippov | |
253 | dedc5eae | Max Filippov | typedef struct XtensaConfig { |
254 | dedc5eae | Max Filippov | const char *name; |
255 | dedc5eae | Max Filippov | uint64_t options; |
256 | ccfcaba6 | Max Filippov | XtensaGdbRegmap gdb_regmap; |
257 | 553e44f9 | Max Filippov | unsigned nareg;
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258 | 40643d7c | Max Filippov | int excm_level;
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259 | 40643d7c | Max Filippov | int ndepc;
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260 | 97836cee | Max Filippov | uint32_t vecbase; |
261 | 40643d7c | Max Filippov | uint32_t exception_vector[EXC_MAX]; |
262 | b994e91b | Max Filippov | unsigned ninterrupt;
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263 | b994e91b | Max Filippov | unsigned nlevel;
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264 | b994e91b | Max Filippov | uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
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265 | b994e91b | Max Filippov | uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
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266 | b994e91b | Max Filippov | uint32_t inttype_mask[INTTYPE_MAX]; |
267 | b994e91b | Max Filippov | struct {
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268 | b994e91b | Max Filippov | uint32_t level; |
269 | b994e91b | Max Filippov | interrupt_type inttype; |
270 | b994e91b | Max Filippov | } interrupt[MAX_NINTERRUPT]; |
271 | b994e91b | Max Filippov | unsigned nccompare;
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272 | b994e91b | Max Filippov | uint32_t timerint[MAX_NCCOMPARE]; |
273 | b994e91b | Max Filippov | uint32_t clock_freq_khz; |
274 | b67ea0cd | Max Filippov | |
275 | b67ea0cd | Max Filippov | xtensa_tlb itlb; |
276 | b67ea0cd | Max Filippov | xtensa_tlb dtlb; |
277 | dedc5eae | Max Filippov | } XtensaConfig; |
278 | dedc5eae | Max Filippov | |
279 | 2328826b | Max Filippov | typedef struct CPUXtensaState { |
280 | dedc5eae | Max Filippov | const XtensaConfig *config;
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281 | 2328826b | Max Filippov | uint32_t regs[16];
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282 | 2328826b | Max Filippov | uint32_t pc; |
283 | 2328826b | Max Filippov | uint32_t sregs[256];
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284 | 2af3da91 | Max Filippov | uint32_t uregs[256];
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285 | 553e44f9 | Max Filippov | uint32_t phys_regs[MAX_NAREG]; |
286 | 2328826b | Max Filippov | |
287 | b67ea0cd | Max Filippov | xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
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288 | b67ea0cd | Max Filippov | xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
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289 | b67ea0cd | Max Filippov | unsigned autorefill_idx;
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290 | b67ea0cd | Max Filippov | |
291 | b994e91b | Max Filippov | int pending_irq_level; /* level of last raised IRQ */ |
292 | b994e91b | Max Filippov | void **irq_inputs;
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293 | b994e91b | Max Filippov | QEMUTimer *ccompare_timer; |
294 | b994e91b | Max Filippov | uint32_t wake_ccount; |
295 | b994e91b | Max Filippov | int64_t halt_clock; |
296 | b994e91b | Max Filippov | |
297 | 40643d7c | Max Filippov | int exception_taken;
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298 | 40643d7c | Max Filippov | |
299 | 2328826b | Max Filippov | CPU_COMMON |
300 | 2328826b | Max Filippov | } CPUXtensaState; |
301 | 2328826b | Max Filippov | |
302 | 2328826b | Max Filippov | #define cpu_init cpu_xtensa_init
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303 | 2328826b | Max Filippov | #define cpu_exec cpu_xtensa_exec
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304 | 2328826b | Max Filippov | #define cpu_gen_code cpu_xtensa_gen_code
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305 | 2328826b | Max Filippov | #define cpu_signal_handler cpu_xtensa_signal_handler
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306 | 2328826b | Max Filippov | #define cpu_list xtensa_cpu_list
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307 | 2328826b | Max Filippov | |
308 | 2328826b | Max Filippov | CPUXtensaState *cpu_xtensa_init(const char *cpu_model); |
309 | 2328826b | Max Filippov | void xtensa_translate_init(void); |
310 | 2328826b | Max Filippov | int cpu_xtensa_exec(CPUXtensaState *s);
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311 | 2328826b | Max Filippov | void do_interrupt(CPUXtensaState *s);
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312 | b994e91b | Max Filippov | void check_interrupts(CPUXtensaState *s);
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313 | b994e91b | Max Filippov | void xtensa_irq_init(CPUState *env);
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314 | b994e91b | Max Filippov | void xtensa_advance_ccount(CPUState *env, uint32_t d);
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315 | b994e91b | Max Filippov | void xtensa_timer_irq(CPUState *env, uint32_t id, uint32_t active);
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316 | 2328826b | Max Filippov | int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); |
317 | 2328826b | Max Filippov | void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
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318 | 553e44f9 | Max Filippov | void xtensa_sync_window_from_phys(CPUState *env);
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319 | 553e44f9 | Max Filippov | void xtensa_sync_phys_from_window(CPUState *env);
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320 | b67ea0cd | Max Filippov | uint32_t xtensa_tlb_get_addr_mask(const CPUState *env, bool dtlb, uint32_t way); |
321 | b67ea0cd | Max Filippov | void split_tlb_entry_spec_way(const CPUState *env, uint32_t v, bool dtlb, |
322 | b67ea0cd | Max Filippov | uint32_t *vpn, uint32_t wi, uint32_t *ei); |
323 | b67ea0cd | Max Filippov | int xtensa_tlb_lookup(const CPUState *env, uint32_t addr, bool dtlb, |
324 | b67ea0cd | Max Filippov | uint32_t *pwi, uint32_t *pei, uint8_t *pring); |
325 | b67ea0cd | Max Filippov | void xtensa_tlb_set_entry(CPUState *env, bool dtlb, |
326 | b67ea0cd | Max Filippov | unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); |
327 | b67ea0cd | Max Filippov | int xtensa_get_physical_addr(CPUState *env,
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328 | b67ea0cd | Max Filippov | uint32_t vaddr, int is_write, int mmu_idx, |
329 | b67ea0cd | Max Filippov | uint32_t *paddr, uint32_t *page_size, unsigned *access);
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330 | b67ea0cd | Max Filippov | |
331 | 2328826b | Max Filippov | |
332 | dedc5eae | Max Filippov | #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) |
333 | dedc5eae | Max Filippov | |
334 | b67ea0cd | Max Filippov | static inline bool xtensa_option_bits_enabled(const XtensaConfig *config, |
335 | b67ea0cd | Max Filippov | uint64_t opt) |
336 | b67ea0cd | Max Filippov | { |
337 | b67ea0cd | Max Filippov | return (config->options & opt) != 0; |
338 | b67ea0cd | Max Filippov | } |
339 | b67ea0cd | Max Filippov | |
340 | dedc5eae | Max Filippov | static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt) |
341 | dedc5eae | Max Filippov | { |
342 | b67ea0cd | Max Filippov | return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
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343 | dedc5eae | Max Filippov | } |
344 | dedc5eae | Max Filippov | |
345 | 40643d7c | Max Filippov | static inline int xtensa_get_cintlevel(const CPUState *env) |
346 | 40643d7c | Max Filippov | { |
347 | 40643d7c | Max Filippov | int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
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348 | 40643d7c | Max Filippov | if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
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349 | 40643d7c | Max Filippov | level = env->config->excm_level; |
350 | 40643d7c | Max Filippov | } |
351 | 40643d7c | Max Filippov | return level;
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352 | 40643d7c | Max Filippov | } |
353 | 40643d7c | Max Filippov | |
354 | f0a548b9 | Max Filippov | static inline int xtensa_get_ring(const CPUState *env) |
355 | f0a548b9 | Max Filippov | { |
356 | f0a548b9 | Max Filippov | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
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357 | f0a548b9 | Max Filippov | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
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358 | f0a548b9 | Max Filippov | } else {
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359 | f0a548b9 | Max Filippov | return 0; |
360 | f0a548b9 | Max Filippov | } |
361 | f0a548b9 | Max Filippov | } |
362 | f0a548b9 | Max Filippov | |
363 | f0a548b9 | Max Filippov | static inline int xtensa_get_cring(const CPUState *env) |
364 | f0a548b9 | Max Filippov | { |
365 | f0a548b9 | Max Filippov | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
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366 | f0a548b9 | Max Filippov | (env->sregs[PS] & PS_EXCM) == 0) {
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367 | f0a548b9 | Max Filippov | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
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368 | f0a548b9 | Max Filippov | } else {
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369 | f0a548b9 | Max Filippov | return 0; |
370 | f0a548b9 | Max Filippov | } |
371 | f0a548b9 | Max Filippov | } |
372 | f0a548b9 | Max Filippov | |
373 | b67ea0cd | Max Filippov | static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUState *env, |
374 | b67ea0cd | Max Filippov | bool dtlb, unsigned wi, unsigned ei) |
375 | b67ea0cd | Max Filippov | { |
376 | b67ea0cd | Max Filippov | return dtlb ?
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377 | b67ea0cd | Max Filippov | env->dtlb[wi] + ei : |
378 | b67ea0cd | Max Filippov | env->itlb[wi] + ei; |
379 | b67ea0cd | Max Filippov | } |
380 | b67ea0cd | Max Filippov | |
381 | f0a548b9 | Max Filippov | /* MMU modes definitions */
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382 | f0a548b9 | Max Filippov | #define MMU_MODE0_SUFFIX _ring0
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383 | f0a548b9 | Max Filippov | #define MMU_MODE1_SUFFIX _ring1
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384 | f0a548b9 | Max Filippov | #define MMU_MODE2_SUFFIX _ring2
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385 | f0a548b9 | Max Filippov | #define MMU_MODE3_SUFFIX _ring3
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386 | f0a548b9 | Max Filippov | |
387 | 2328826b | Max Filippov | static inline int cpu_mmu_index(CPUState *env) |
388 | 2328826b | Max Filippov | { |
389 | f0a548b9 | Max Filippov | return xtensa_get_cring(env);
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390 | 2328826b | Max Filippov | } |
391 | 2328826b | Max Filippov | |
392 | f0a548b9 | Max Filippov | #define XTENSA_TBFLAG_RING_MASK 0x3 |
393 | f0a548b9 | Max Filippov | #define XTENSA_TBFLAG_EXCM 0x4 |
394 | 6ad6dbf7 | Max Filippov | #define XTENSA_TBFLAG_LITBASE 0x8 |
395 | f0a548b9 | Max Filippov | |
396 | 2328826b | Max Filippov | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
397 | 2328826b | Max Filippov | target_ulong *cs_base, int *flags)
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398 | 2328826b | Max Filippov | { |
399 | 2328826b | Max Filippov | *pc = env->pc; |
400 | 2328826b | Max Filippov | *cs_base = 0;
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401 | 2328826b | Max Filippov | *flags = 0;
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402 | f0a548b9 | Max Filippov | *flags |= xtensa_get_ring(env); |
403 | f0a548b9 | Max Filippov | if (env->sregs[PS] & PS_EXCM) {
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404 | f0a548b9 | Max Filippov | *flags |= XTENSA_TBFLAG_EXCM; |
405 | f0a548b9 | Max Filippov | } |
406 | 6ad6dbf7 | Max Filippov | if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
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407 | 6ad6dbf7 | Max Filippov | (env->sregs[LITBASE] & 1)) {
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408 | 6ad6dbf7 | Max Filippov | *flags |= XTENSA_TBFLAG_LITBASE; |
409 | 6ad6dbf7 | Max Filippov | } |
410 | 2328826b | Max Filippov | } |
411 | 2328826b | Max Filippov | |
412 | 2328826b | Max Filippov | #include "cpu-all.h" |
413 | 2328826b | Max Filippov | #include "exec-all.h" |
414 | 2328826b | Max Filippov | |
415 | 2328826b | Max Filippov | static inline int cpu_has_work(CPUState *env) |
416 | 2328826b | Max Filippov | { |
417 | b994e91b | Max Filippov | return env->pending_irq_level;
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418 | 2328826b | Max Filippov | } |
419 | 2328826b | Max Filippov | |
420 | 2328826b | Max Filippov | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
421 | 2328826b | Max Filippov | { |
422 | 2328826b | Max Filippov | env->pc = tb->pc; |
423 | 2328826b | Max Filippov | } |
424 | 2328826b | Max Filippov | |
425 | 2328826b | Max Filippov | #endif |