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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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/* define it to use liveness analysis (better code) */
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#define USE_LIVENESS_ANALYSIS
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#include "config.h"
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#ifndef CONFIG_DEBUG_TCG
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/* define it to suppress various consistency checks (faster) */
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#define NDEBUG
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#endif
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#ifdef _WIN32
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#include <malloc.h>
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#endif
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#ifdef _AIX
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#include <alloca.h>
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#endif
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#include "qemu-common.h"
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#include "cache-utils.h"
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#include "host-utils.h"
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/* Note: the long term plan is to reduce the dependancies on the QEMU
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   CPU definitions. Currently they are used for qemu_ld/st
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   instructions */
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#define NO_CPU_IO_DEFS
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#include "cpu.h"
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#include "exec-all.h"
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#include "tcg-op.h"
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#include "elf.h"
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#if defined(CONFIG_USE_GUEST_BASE) && !defined(TCG_TARGET_HAS_GUEST_BASE)
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#error GUEST_BASE not supported on this host.
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#endif
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static void patch_reloc(uint8_t *code_ptr, int type, 
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                        tcg_target_long value, tcg_target_long addend);
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static TCGOpDef tcg_op_defs[] = {
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#define DEF(s, n, copy_size) { #s, 0, 0, n, n, 0, copy_size },
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#define DEF2(s, oargs, iargs, cargs, flags) { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags, 0 },
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#include "tcg-opc.h"
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#undef DEF
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#undef DEF2
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};
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static TCGRegSet tcg_target_available_regs[2];
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static TCGRegSet tcg_target_call_clobber_regs;
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/* XXX: move that inside the context */
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uint16_t *gen_opc_ptr;
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TCGArg *gen_opparam_ptr;
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static inline void tcg_out8(TCGContext *s, uint8_t v)
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{
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    *s->code_ptr++ = v;
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}
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static inline void tcg_out16(TCGContext *s, uint16_t v)
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{
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    *(uint16_t *)s->code_ptr = v;
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    s->code_ptr += 2;
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}
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static inline void tcg_out32(TCGContext *s, uint32_t v)
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{
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    *(uint32_t *)s->code_ptr = v;
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    s->code_ptr += 4;
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}
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/* label relocation processing */
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void tcg_out_reloc(TCGContext *s, uint8_t *code_ptr, int type, 
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                   int label_index, long addend)
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{
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    TCGLabel *l;
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    TCGRelocation *r;
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    l = &s->labels[label_index];
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    if (l->has_value) {
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        /* FIXME: This may break relocations on RISC targets that
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           modify instruction fields in place.  The caller may not have 
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           written the initial value.  */
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        patch_reloc(code_ptr, type, l->u.value, addend);
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    } else {
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        /* add a new relocation entry */
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        r = tcg_malloc(sizeof(TCGRelocation));
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        r->type = type;
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        r->ptr = code_ptr;
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        r->addend = addend;
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        r->next = l->u.first_reloc;
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        l->u.first_reloc = r;
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    }
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}
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static void tcg_out_label(TCGContext *s, int label_index, 
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                          tcg_target_long value)
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{
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    TCGLabel *l;
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    TCGRelocation *r;
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    l = &s->labels[label_index];
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    if (l->has_value)
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        tcg_abort();
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    r = l->u.first_reloc;
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    while (r != NULL) {
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        patch_reloc(r->ptr, r->type, value, r->addend);
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        r = r->next;
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    }
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    l->has_value = 1;
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    l->u.value = value;
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}
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int gen_new_label(void)
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{
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    TCGContext *s = &tcg_ctx;
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    int idx;
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    TCGLabel *l;
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    if (s->nb_labels >= TCG_MAX_LABELS)
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        tcg_abort();
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    idx = s->nb_labels++;
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    l = &s->labels[idx];
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    l->has_value = 0;
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    l->u.first_reloc = NULL;
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    return idx;
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}
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#include "tcg-target.c"
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/* pool based memory allocation */
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void *tcg_malloc_internal(TCGContext *s, int size)
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{
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    TCGPool *p;
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    int pool_size;
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    if (size > TCG_POOL_CHUNK_SIZE) {
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        /* big malloc: insert a new pool (XXX: could optimize) */
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        p = qemu_malloc(sizeof(TCGPool) + size);
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        p->size = size;
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        if (s->pool_current)
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            s->pool_current->next = p;
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        else
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            s->pool_first = p;
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        p->next = s->pool_current;
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    } else {
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        p = s->pool_current;
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        if (!p) {
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            p = s->pool_first;
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            if (!p)
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                goto new_pool;
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        } else {
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            if (!p->next) {
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            new_pool:
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                pool_size = TCG_POOL_CHUNK_SIZE;
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                p = qemu_malloc(sizeof(TCGPool) + pool_size);
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                p->size = pool_size;
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                p->next = NULL;
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                if (s->pool_current) 
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                    s->pool_current->next = p;
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                else
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                    s->pool_first = p;
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            } else {
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                p = p->next;
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            }
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        }
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    }
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    s->pool_current = p;
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    s->pool_cur = p->data + size;
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    s->pool_end = p->data + p->size;
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    return p->data;
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}
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void tcg_pool_reset(TCGContext *s)
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{
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    s->pool_cur = s->pool_end = NULL;
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    s->pool_current = NULL;
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}
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void tcg_context_init(TCGContext *s)
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{
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    int op, total_args, n;
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    TCGOpDef *def;
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    TCGArgConstraint *args_ct;
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    int *sorted_args;
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    memset(s, 0, sizeof(*s));
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    s->temps = s->static_temps;
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    s->nb_globals = 0;
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    /* Count total number of arguments and allocate the corresponding
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       space */
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    total_args = 0;
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    for(op = 0; op < NB_OPS; op++) {
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        def = &tcg_op_defs[op];
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        n = def->nb_iargs + def->nb_oargs;
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        total_args += n;
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    }
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    args_ct = qemu_malloc(sizeof(TCGArgConstraint) * total_args);
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    sorted_args = qemu_malloc(sizeof(int) * total_args);
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    for(op = 0; op < NB_OPS; op++) {
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        def = &tcg_op_defs[op];
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        def->args_ct = args_ct;
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        def->sorted_args = sorted_args;
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        n = def->nb_iargs + def->nb_oargs;
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        sorted_args += n;
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        args_ct += n;
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    }
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    tcg_target_init(s);
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    /* init global prologue and epilogue */
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    s->code_buf = code_gen_prologue;
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    s->code_ptr = s->code_buf;
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    tcg_target_qemu_prologue(s);
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    flush_icache_range((unsigned long)s->code_buf, 
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                       (unsigned long)s->code_ptr);
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}
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void tcg_set_frame(TCGContext *s, int reg,
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                   tcg_target_long start, tcg_target_long size)
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{
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    s->frame_start = start;
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    s->frame_end = start + size;
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    s->frame_reg = reg;
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}
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void tcg_func_start(TCGContext *s)
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{
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    int i;
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    tcg_pool_reset(s);
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    s->nb_temps = s->nb_globals;
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    for(i = 0; i < (TCG_TYPE_COUNT * 2); i++)
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        s->first_free_temp[i] = -1;
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    s->labels = tcg_malloc(sizeof(TCGLabel) * TCG_MAX_LABELS);
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    s->nb_labels = 0;
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    s->current_frame_offset = s->frame_start;
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    gen_opc_ptr = gen_opc_buf;
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    gen_opparam_ptr = gen_opparam_buf;
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}
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static inline void tcg_temp_alloc(TCGContext *s, int n)
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{
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    if (n > TCG_MAX_TEMPS)
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        tcg_abort();
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}
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static inline int tcg_global_reg_new_internal(TCGType type, int reg,
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                                              const char *name)
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{
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    TCGContext *s = &tcg_ctx;
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    TCGTemp *ts;
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    int idx;
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#if TCG_TARGET_REG_BITS == 32
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    if (type != TCG_TYPE_I32)
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        tcg_abort();
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#endif
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    if (tcg_regset_test_reg(s->reserved_regs, reg))
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        tcg_abort();
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    idx = s->nb_globals;
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    tcg_temp_alloc(s, s->nb_globals + 1);
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    ts = &s->temps[s->nb_globals];
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    ts->base_type = type;
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    ts->type = type;
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    ts->fixed_reg = 1;
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    ts->reg = reg;
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    ts->name = name;
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    s->nb_globals++;
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    tcg_regset_set_reg(s->reserved_regs, reg);
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    return idx;
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}
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TCGv_i32 tcg_global_reg_new_i32(int reg, const char *name)
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{
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    int idx;
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    idx = tcg_global_reg_new_internal(TCG_TYPE_I32, reg, name);
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    return MAKE_TCGV_I32(idx);
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}
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TCGv_i64 tcg_global_reg_new_i64(int reg, const char *name)
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{
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    int idx;
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    idx = tcg_global_reg_new_internal(TCG_TYPE_I64, reg, name);
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    return MAKE_TCGV_I64(idx);
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}
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static inline int tcg_global_mem_new_internal(TCGType type, int reg,
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                                              tcg_target_long offset,
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                                              const char *name)
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{
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    TCGContext *s = &tcg_ctx;
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    TCGTemp *ts;
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    int idx;
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    idx = s->nb_globals;
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#if TCG_TARGET_REG_BITS == 32
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    if (type == TCG_TYPE_I64) {
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        char buf[64];
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        tcg_temp_alloc(s, s->nb_globals + 2);
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        ts = &s->temps[s->nb_globals];
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        ts->base_type = type;
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        ts->type = TCG_TYPE_I32;
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        ts->fixed_reg = 0;
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        ts->mem_allocated = 1;
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        ts->mem_reg = reg;
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#ifdef TCG_TARGET_WORDS_BIGENDIAN
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        ts->mem_offset = offset + 4;
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#else
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        ts->mem_offset = offset;
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#endif
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        pstrcpy(buf, sizeof(buf), name);
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        pstrcat(buf, sizeof(buf), "_0");
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        ts->name = strdup(buf);
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        ts++;
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        ts->base_type = type;
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        ts->type = TCG_TYPE_I32;
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        ts->fixed_reg = 0;
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        ts->mem_allocated = 1;
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        ts->mem_reg = reg;
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#ifdef TCG_TARGET_WORDS_BIGENDIAN
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        ts->mem_offset = offset;
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#else
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        ts->mem_offset = offset + 4;
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#endif
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        pstrcpy(buf, sizeof(buf), name);
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        pstrcat(buf, sizeof(buf), "_1");
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        ts->name = strdup(buf);
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        s->nb_globals += 2;
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    } else
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#endif
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    {
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        tcg_temp_alloc(s, s->nb_globals + 1);
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        ts = &s->temps[s->nb_globals];
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        ts->base_type = type;
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        ts->type = type;
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        ts->fixed_reg = 0;
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        ts->mem_allocated = 1;
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        ts->mem_reg = reg;
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        ts->mem_offset = offset;
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        ts->name = name;
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        s->nb_globals++;
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    }
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    return idx;
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}
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TCGv_i32 tcg_global_mem_new_i32(int reg, tcg_target_long offset,
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                                const char *name)
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{
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    int idx;
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    idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
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    return MAKE_TCGV_I32(idx);
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}
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TCGv_i64 tcg_global_mem_new_i64(int reg, tcg_target_long offset,
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                                const char *name)
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{
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    int idx;
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    idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
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    return MAKE_TCGV_I64(idx);
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}
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static inline int tcg_temp_new_internal(TCGType type, int temp_local)
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{
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    TCGContext *s = &tcg_ctx;
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    TCGTemp *ts;
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    int idx, k;
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    k = type;
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    if (temp_local)
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        k += TCG_TYPE_COUNT;
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    idx = s->first_free_temp[k];
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    if (idx != -1) {
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        /* There is already an available temp with the
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           right type */
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        ts = &s->temps[idx];
415 641d5fbe bellard
        s->first_free_temp[k] = ts->next_free_temp;
416 e8996ee0 bellard
        ts->temp_allocated = 1;
417 641d5fbe bellard
        assert(ts->temp_local == temp_local);
418 e8996ee0 bellard
    } else {
419 e8996ee0 bellard
        idx = s->nb_temps;
420 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
421 e8996ee0 bellard
        if (type == TCG_TYPE_I64) {
422 8df1ca4b ths
            tcg_temp_alloc(s, s->nb_temps + 2);
423 e8996ee0 bellard
            ts = &s->temps[s->nb_temps];
424 e8996ee0 bellard
            ts->base_type = type;
425 e8996ee0 bellard
            ts->type = TCG_TYPE_I32;
426 e8996ee0 bellard
            ts->temp_allocated = 1;
427 641d5fbe bellard
            ts->temp_local = temp_local;
428 e8996ee0 bellard
            ts->name = NULL;
429 e8996ee0 bellard
            ts++;
430 e8996ee0 bellard
            ts->base_type = TCG_TYPE_I32;
431 e8996ee0 bellard
            ts->type = TCG_TYPE_I32;
432 e8996ee0 bellard
            ts->temp_allocated = 1;
433 641d5fbe bellard
            ts->temp_local = temp_local;
434 e8996ee0 bellard
            ts->name = NULL;
435 e8996ee0 bellard
            s->nb_temps += 2;
436 e8996ee0 bellard
        } else
437 c896fe29 bellard
#endif
438 e8996ee0 bellard
        {
439 e8996ee0 bellard
            tcg_temp_alloc(s, s->nb_temps + 1);
440 e8996ee0 bellard
            ts = &s->temps[s->nb_temps];
441 e8996ee0 bellard
            ts->base_type = type;
442 e8996ee0 bellard
            ts->type = type;
443 e8996ee0 bellard
            ts->temp_allocated = 1;
444 641d5fbe bellard
            ts->temp_local = temp_local;
445 e8996ee0 bellard
            ts->name = NULL;
446 e8996ee0 bellard
            s->nb_temps++;
447 e8996ee0 bellard
        }
448 c896fe29 bellard
    }
449 a7812ae4 pbrook
    return idx;
450 c896fe29 bellard
}
451 c896fe29 bellard
452 a7812ae4 pbrook
TCGv_i32 tcg_temp_new_internal_i32(int temp_local)
453 a7812ae4 pbrook
{
454 a7812ae4 pbrook
    int idx;
455 a7812ae4 pbrook
456 a7812ae4 pbrook
    idx = tcg_temp_new_internal(TCG_TYPE_I32, temp_local);
457 a7812ae4 pbrook
    return MAKE_TCGV_I32(idx);
458 a7812ae4 pbrook
}
459 a7812ae4 pbrook
460 a7812ae4 pbrook
TCGv_i64 tcg_temp_new_internal_i64(int temp_local)
461 a7812ae4 pbrook
{
462 a7812ae4 pbrook
    int idx;
463 a7812ae4 pbrook
464 a7812ae4 pbrook
    idx = tcg_temp_new_internal(TCG_TYPE_I64, temp_local);
465 a7812ae4 pbrook
    return MAKE_TCGV_I64(idx);
466 a7812ae4 pbrook
}
467 a7812ae4 pbrook
468 a7812ae4 pbrook
static inline void tcg_temp_free_internal(int idx)
469 c896fe29 bellard
{
470 c896fe29 bellard
    TCGContext *s = &tcg_ctx;
471 c896fe29 bellard
    TCGTemp *ts;
472 641d5fbe bellard
    int k;
473 c896fe29 bellard
474 e8996ee0 bellard
    assert(idx >= s->nb_globals && idx < s->nb_temps);
475 c896fe29 bellard
    ts = &s->temps[idx];
476 e8996ee0 bellard
    assert(ts->temp_allocated != 0);
477 e8996ee0 bellard
    ts->temp_allocated = 0;
478 641d5fbe bellard
    k = ts->base_type;
479 641d5fbe bellard
    if (ts->temp_local)
480 641d5fbe bellard
        k += TCG_TYPE_COUNT;
481 641d5fbe bellard
    ts->next_free_temp = s->first_free_temp[k];
482 641d5fbe bellard
    s->first_free_temp[k] = idx;
483 c896fe29 bellard
}
484 c896fe29 bellard
485 a7812ae4 pbrook
void tcg_temp_free_i32(TCGv_i32 arg)
486 a7812ae4 pbrook
{
487 a7812ae4 pbrook
    tcg_temp_free_internal(GET_TCGV_I32(arg));
488 a7812ae4 pbrook
}
489 a7812ae4 pbrook
490 a7812ae4 pbrook
void tcg_temp_free_i64(TCGv_i64 arg)
491 a7812ae4 pbrook
{
492 a7812ae4 pbrook
    tcg_temp_free_internal(GET_TCGV_I64(arg));
493 a7812ae4 pbrook
}
494 e8996ee0 bellard
495 a7812ae4 pbrook
TCGv_i32 tcg_const_i32(int32_t val)
496 c896fe29 bellard
{
497 a7812ae4 pbrook
    TCGv_i32 t0;
498 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
499 e8996ee0 bellard
    tcg_gen_movi_i32(t0, val);
500 e8996ee0 bellard
    return t0;
501 e8996ee0 bellard
}
502 c896fe29 bellard
503 a7812ae4 pbrook
TCGv_i64 tcg_const_i64(int64_t val)
504 e8996ee0 bellard
{
505 a7812ae4 pbrook
    TCGv_i64 t0;
506 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
507 e8996ee0 bellard
    tcg_gen_movi_i64(t0, val);
508 e8996ee0 bellard
    return t0;
509 c896fe29 bellard
}
510 c896fe29 bellard
511 a7812ae4 pbrook
TCGv_i32 tcg_const_local_i32(int32_t val)
512 bdffd4a9 aurel32
{
513 a7812ae4 pbrook
    TCGv_i32 t0;
514 a7812ae4 pbrook
    t0 = tcg_temp_local_new_i32();
515 bdffd4a9 aurel32
    tcg_gen_movi_i32(t0, val);
516 bdffd4a9 aurel32
    return t0;
517 bdffd4a9 aurel32
}
518 bdffd4a9 aurel32
519 a7812ae4 pbrook
TCGv_i64 tcg_const_local_i64(int64_t val)
520 bdffd4a9 aurel32
{
521 a7812ae4 pbrook
    TCGv_i64 t0;
522 a7812ae4 pbrook
    t0 = tcg_temp_local_new_i64();
523 bdffd4a9 aurel32
    tcg_gen_movi_i64(t0, val);
524 bdffd4a9 aurel32
    return t0;
525 bdffd4a9 aurel32
}
526 bdffd4a9 aurel32
527 c896fe29 bellard
void tcg_register_helper(void *func, const char *name)
528 c896fe29 bellard
{
529 c896fe29 bellard
    TCGContext *s = &tcg_ctx;
530 c896fe29 bellard
    int n;
531 c896fe29 bellard
    if ((s->nb_helpers + 1) > s->allocated_helpers) {
532 c896fe29 bellard
        n = s->allocated_helpers;
533 c896fe29 bellard
        if (n == 0) {
534 c896fe29 bellard
            n = 4;
535 c896fe29 bellard
        } else {
536 c896fe29 bellard
            n *= 2;
537 c896fe29 bellard
        }
538 c896fe29 bellard
        s->helpers = realloc(s->helpers, n * sizeof(TCGHelperInfo));
539 c896fe29 bellard
        s->allocated_helpers = n;
540 c896fe29 bellard
    }
541 4dc81f28 bellard
    s->helpers[s->nb_helpers].func = (tcg_target_ulong)func;
542 c896fe29 bellard
    s->helpers[s->nb_helpers].name = name;
543 c896fe29 bellard
    s->nb_helpers++;
544 c896fe29 bellard
}
545 c896fe29 bellard
546 39cf05d3 bellard
/* Note: we convert the 64 bit args to 32 bit and do some alignment
547 39cf05d3 bellard
   and endian swap. Maybe it would be better to do the alignment
548 39cf05d3 bellard
   and endian swap in tcg_reg_alloc_call(). */
549 a7812ae4 pbrook
void tcg_gen_callN(TCGContext *s, TCGv_ptr func, unsigned int flags,
550 a7812ae4 pbrook
                   int sizemask, TCGArg ret, int nargs, TCGArg *args)
551 c896fe29 bellard
{
552 a7812ae4 pbrook
    int call_type;
553 a7812ae4 pbrook
    int i;
554 a7812ae4 pbrook
    int real_args;
555 a7812ae4 pbrook
    int nb_rets;
556 a7812ae4 pbrook
    TCGArg *nparam;
557 a7812ae4 pbrook
    *gen_opc_ptr++ = INDEX_op_call;
558 a7812ae4 pbrook
    nparam = gen_opparam_ptr++;
559 a7812ae4 pbrook
    call_type = (flags & TCG_CALL_TYPE_MASK);
560 a7812ae4 pbrook
    if (ret != TCG_CALL_DUMMY_ARG) {
561 a7812ae4 pbrook
#if TCG_TARGET_REG_BITS < 64
562 a7812ae4 pbrook
        if (sizemask & 1) {
563 39cf05d3 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
564 a7812ae4 pbrook
            *gen_opparam_ptr++ = ret + 1;
565 a7812ae4 pbrook
            *gen_opparam_ptr++ = ret;
566 39cf05d3 bellard
#else
567 a7812ae4 pbrook
            *gen_opparam_ptr++ = ret;
568 a7812ae4 pbrook
            *gen_opparam_ptr++ = ret + 1;
569 39cf05d3 bellard
#endif
570 a7812ae4 pbrook
            nb_rets = 2;
571 a7812ae4 pbrook
        } else
572 a7812ae4 pbrook
#endif
573 a7812ae4 pbrook
        {
574 a7812ae4 pbrook
            *gen_opparam_ptr++ = ret;
575 a7812ae4 pbrook
            nb_rets = 1;
576 c896fe29 bellard
        }
577 a7812ae4 pbrook
    } else {
578 a7812ae4 pbrook
        nb_rets = 0;
579 c896fe29 bellard
    }
580 a7812ae4 pbrook
    real_args = 0;
581 a7812ae4 pbrook
    for (i = 0; i < nargs; i++) {
582 a7812ae4 pbrook
#if TCG_TARGET_REG_BITS < 64
583 a7812ae4 pbrook
        if (sizemask & (2 << i)) {
584 c896fe29 bellard
#ifdef TCG_TARGET_I386
585 c896fe29 bellard
            /* REGPARM case: if the third parameter is 64 bit, it is
586 c896fe29 bellard
               allocated on the stack */
587 a7812ae4 pbrook
            if (i == 2 && call_type == TCG_CALL_TYPE_REGPARM) {
588 c896fe29 bellard
                call_type = TCG_CALL_TYPE_REGPARM_2;
589 c896fe29 bellard
                flags = (flags & ~TCG_CALL_TYPE_MASK) | call_type;
590 c896fe29 bellard
            }
591 a7812ae4 pbrook
#endif
592 39cf05d3 bellard
#ifdef TCG_TARGET_CALL_ALIGN_ARGS
593 39cf05d3 bellard
            /* some targets want aligned 64 bit args */
594 ebd486d5 malc
            if (real_args & 1) {
595 a7812ae4 pbrook
                *gen_opparam_ptr++ = TCG_CALL_DUMMY_ARG;
596 ebd486d5 malc
                real_args++;
597 39cf05d3 bellard
            }
598 39cf05d3 bellard
#endif
599 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
600 a7812ae4 pbrook
            *gen_opparam_ptr++ = args[i] + 1;
601 a7812ae4 pbrook
            *gen_opparam_ptr++ = args[i];
602 c896fe29 bellard
#else
603 a7812ae4 pbrook
            *gen_opparam_ptr++ = args[i];
604 a7812ae4 pbrook
            *gen_opparam_ptr++ = args[i] + 1;
605 c896fe29 bellard
#endif
606 a7812ae4 pbrook
            real_args += 2;
607 a7812ae4 pbrook
        } else
608 c896fe29 bellard
#endif
609 a7812ae4 pbrook
        {
610 a7812ae4 pbrook
            *gen_opparam_ptr++ = args[i];
611 a7812ae4 pbrook
            real_args++;
612 c896fe29 bellard
        }
613 c896fe29 bellard
    }
614 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_PTR(func);
615 a7812ae4 pbrook
616 a7812ae4 pbrook
    *gen_opparam_ptr++ = flags;
617 a7812ae4 pbrook
618 a7812ae4 pbrook
    *nparam = (nb_rets << 16) | (real_args + 1);
619 a7812ae4 pbrook
620 a7812ae4 pbrook
    /* total parameters, needed to go backward in the instruction stream */
621 a7812ae4 pbrook
    *gen_opparam_ptr++ = 1 + nb_rets + real_args + 3;
622 c896fe29 bellard
}
623 c896fe29 bellard
624 ac56dd48 pbrook
#if TCG_TARGET_REG_BITS == 32
625 a7812ae4 pbrook
void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
626 c896fe29 bellard
                        int c, int right, int arith)
627 c896fe29 bellard
{
628 cf60bce4 bellard
    if (c == 0) {
629 a7812ae4 pbrook
        tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
630 cf60bce4 bellard
        tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
631 cf60bce4 bellard
    } else if (c >= 32) {
632 c896fe29 bellard
        c -= 32;
633 c896fe29 bellard
        if (right) {
634 c896fe29 bellard
            if (arith) {
635 a7812ae4 pbrook
                tcg_gen_sari_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), c);
636 ac56dd48 pbrook
                tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), 31);
637 c896fe29 bellard
            } else {
638 a7812ae4 pbrook
                tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), c);
639 ac56dd48 pbrook
                tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
640 c896fe29 bellard
            }
641 c896fe29 bellard
        } else {
642 a7812ae4 pbrook
            tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), c);
643 a7812ae4 pbrook
            tcg_gen_movi_i32(TCGV_LOW(ret), 0);
644 c896fe29 bellard
        }
645 c896fe29 bellard
    } else {
646 a7812ae4 pbrook
        TCGv_i32 t0, t1;
647 c896fe29 bellard
648 a7812ae4 pbrook
        t0 = tcg_temp_new_i32();
649 a7812ae4 pbrook
        t1 = tcg_temp_new_i32();
650 c896fe29 bellard
        if (right) {
651 ac56dd48 pbrook
            tcg_gen_shli_i32(t0, TCGV_HIGH(arg1), 32 - c);
652 c896fe29 bellard
            if (arith)
653 ac56dd48 pbrook
                tcg_gen_sari_i32(t1, TCGV_HIGH(arg1), c);
654 a7812ae4 pbrook
            else
655 ac56dd48 pbrook
                tcg_gen_shri_i32(t1, TCGV_HIGH(arg1), c);
656 a7812ae4 pbrook
            tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
657 a7812ae4 pbrook
            tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t0);
658 ac56dd48 pbrook
            tcg_gen_mov_i32(TCGV_HIGH(ret), t1);
659 c896fe29 bellard
        } else {
660 a7812ae4 pbrook
            tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
661 c896fe29 bellard
            /* Note: ret can be the same as arg1, so we use t1 */
662 a7812ae4 pbrook
            tcg_gen_shli_i32(t1, TCGV_LOW(arg1), c);
663 ac56dd48 pbrook
            tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
664 ac56dd48 pbrook
            tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t0);
665 a7812ae4 pbrook
            tcg_gen_mov_i32(TCGV_LOW(ret), t1);
666 c896fe29 bellard
        }
667 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
668 a7812ae4 pbrook
        tcg_temp_free_i32(t1);
669 c896fe29 bellard
    }
670 c896fe29 bellard
}
671 ac56dd48 pbrook
#endif
672 c896fe29 bellard
673 be210acb Richard Henderson
674 8fcd3692 blueswir1
static void tcg_reg_alloc_start(TCGContext *s)
675 c896fe29 bellard
{
676 c896fe29 bellard
    int i;
677 c896fe29 bellard
    TCGTemp *ts;
678 c896fe29 bellard
    for(i = 0; i < s->nb_globals; i++) {
679 c896fe29 bellard
        ts = &s->temps[i];
680 c896fe29 bellard
        if (ts->fixed_reg) {
681 c896fe29 bellard
            ts->val_type = TEMP_VAL_REG;
682 c896fe29 bellard
        } else {
683 c896fe29 bellard
            ts->val_type = TEMP_VAL_MEM;
684 c896fe29 bellard
        }
685 c896fe29 bellard
    }
686 e8996ee0 bellard
    for(i = s->nb_globals; i < s->nb_temps; i++) {
687 e8996ee0 bellard
        ts = &s->temps[i];
688 e8996ee0 bellard
        ts->val_type = TEMP_VAL_DEAD;
689 e8996ee0 bellard
        ts->mem_allocated = 0;
690 e8996ee0 bellard
        ts->fixed_reg = 0;
691 e8996ee0 bellard
    }
692 c896fe29 bellard
    for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
693 c896fe29 bellard
        s->reg_to_temp[i] = -1;
694 c896fe29 bellard
    }
695 c896fe29 bellard
}
696 c896fe29 bellard
697 ac56dd48 pbrook
static char *tcg_get_arg_str_idx(TCGContext *s, char *buf, int buf_size,
698 ac56dd48 pbrook
                                 int idx)
699 c896fe29 bellard
{
700 c896fe29 bellard
    TCGTemp *ts;
701 ac56dd48 pbrook
702 ac56dd48 pbrook
    ts = &s->temps[idx];
703 ac56dd48 pbrook
    if (idx < s->nb_globals) {
704 ac56dd48 pbrook
        pstrcpy(buf, buf_size, ts->name);
705 c896fe29 bellard
    } else {
706 641d5fbe bellard
        if (ts->temp_local) 
707 641d5fbe bellard
            snprintf(buf, buf_size, "loc%d", idx - s->nb_globals);
708 641d5fbe bellard
        else
709 641d5fbe bellard
            snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals);
710 c896fe29 bellard
    }
711 c896fe29 bellard
    return buf;
712 c896fe29 bellard
}
713 c896fe29 bellard
714 a7812ae4 pbrook
char *tcg_get_arg_str_i32(TCGContext *s, char *buf, int buf_size, TCGv_i32 arg)
715 a7812ae4 pbrook
{
716 a7812ae4 pbrook
    return tcg_get_arg_str_idx(s, buf, buf_size, GET_TCGV_I32(arg));
717 a7812ae4 pbrook
}
718 a7812ae4 pbrook
719 a7812ae4 pbrook
char *tcg_get_arg_str_i64(TCGContext *s, char *buf, int buf_size, TCGv_i64 arg)
720 ac56dd48 pbrook
{
721 a810a2de blueswir1
    return tcg_get_arg_str_idx(s, buf, buf_size, GET_TCGV_I64(arg));
722 ac56dd48 pbrook
}
723 ac56dd48 pbrook
724 e8996ee0 bellard
static int helper_cmp(const void *p1, const void *p2)
725 4dc81f28 bellard
{
726 e8996ee0 bellard
    const TCGHelperInfo *th1 = p1;
727 e8996ee0 bellard
    const TCGHelperInfo *th2 = p2;
728 e8996ee0 bellard
    if (th1->func < th2->func)
729 e8996ee0 bellard
        return -1;
730 e8996ee0 bellard
    else if (th1->func == th2->func)
731 e8996ee0 bellard
        return 0;
732 e8996ee0 bellard
    else
733 e8996ee0 bellard
        return 1;
734 4dc81f28 bellard
}
735 4dc81f28 bellard
736 e8996ee0 bellard
/* find helper definition (Note: A hash table would be better) */
737 e8996ee0 bellard
static TCGHelperInfo *tcg_find_helper(TCGContext *s, tcg_target_ulong val)
738 4dc81f28 bellard
{
739 e8996ee0 bellard
    int m, m_min, m_max;
740 4dc81f28 bellard
    TCGHelperInfo *th;
741 e8996ee0 bellard
    tcg_target_ulong v;
742 4dc81f28 bellard
743 e8996ee0 bellard
    if (unlikely(!s->helpers_sorted)) {
744 e8996ee0 bellard
        qsort(s->helpers, s->nb_helpers, sizeof(TCGHelperInfo), 
745 e8996ee0 bellard
              helper_cmp);
746 e8996ee0 bellard
        s->helpers_sorted = 1;
747 e8996ee0 bellard
    }
748 e8996ee0 bellard
749 e8996ee0 bellard
    /* binary search */
750 e8996ee0 bellard
    m_min = 0;
751 e8996ee0 bellard
    m_max = s->nb_helpers - 1;
752 e8996ee0 bellard
    while (m_min <= m_max) {
753 e8996ee0 bellard
        m = (m_min + m_max) >> 1;
754 e8996ee0 bellard
        th = &s->helpers[m];
755 e8996ee0 bellard
        v = th->func;
756 e8996ee0 bellard
        if (v == val)
757 e8996ee0 bellard
            return th;
758 e8996ee0 bellard
        else if (val < v) {
759 e8996ee0 bellard
            m_max = m - 1;
760 e8996ee0 bellard
        } else {
761 e8996ee0 bellard
            m_min = m + 1;
762 4dc81f28 bellard
        }
763 4dc81f28 bellard
    }
764 e8996ee0 bellard
    return NULL;
765 4dc81f28 bellard
}
766 4dc81f28 bellard
767 f48f3ede blueswir1
static const char * const cond_name[] =
768 f48f3ede blueswir1
{
769 f48f3ede blueswir1
    [TCG_COND_EQ] = "eq",
770 f48f3ede blueswir1
    [TCG_COND_NE] = "ne",
771 f48f3ede blueswir1
    [TCG_COND_LT] = "lt",
772 f48f3ede blueswir1
    [TCG_COND_GE] = "ge",
773 f48f3ede blueswir1
    [TCG_COND_LE] = "le",
774 f48f3ede blueswir1
    [TCG_COND_GT] = "gt",
775 f48f3ede blueswir1
    [TCG_COND_LTU] = "ltu",
776 f48f3ede blueswir1
    [TCG_COND_GEU] = "geu",
777 f48f3ede blueswir1
    [TCG_COND_LEU] = "leu",
778 f48f3ede blueswir1
    [TCG_COND_GTU] = "gtu"
779 f48f3ede blueswir1
};
780 f48f3ede blueswir1
781 c896fe29 bellard
void tcg_dump_ops(TCGContext *s, FILE *outfile)
782 c896fe29 bellard
{
783 c896fe29 bellard
    const uint16_t *opc_ptr;
784 c896fe29 bellard
    const TCGArg *args;
785 c896fe29 bellard
    TCGArg arg;
786 7e4597d7 bellard
    int c, i, k, nb_oargs, nb_iargs, nb_cargs, first_insn;
787 c896fe29 bellard
    const TCGOpDef *def;
788 c896fe29 bellard
    char buf[128];
789 c896fe29 bellard
790 7e4597d7 bellard
    first_insn = 1;
791 c896fe29 bellard
    opc_ptr = gen_opc_buf;
792 c896fe29 bellard
    args = gen_opparam_buf;
793 c896fe29 bellard
    while (opc_ptr < gen_opc_ptr) {
794 c896fe29 bellard
        c = *opc_ptr++;
795 c896fe29 bellard
        def = &tcg_op_defs[c];
796 7e4597d7 bellard
        if (c == INDEX_op_debug_insn_start) {
797 7e4597d7 bellard
            uint64_t pc;
798 7e4597d7 bellard
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
799 7e4597d7 bellard
            pc = ((uint64_t)args[1] << 32) | args[0];
800 7e4597d7 bellard
#else
801 7e4597d7 bellard
            pc = args[0];
802 7e4597d7 bellard
#endif
803 7e4597d7 bellard
            if (!first_insn) 
804 7e4597d7 bellard
                fprintf(outfile, "\n");
805 7e4597d7 bellard
            fprintf(outfile, " ---- 0x%" PRIx64, pc);
806 7e4597d7 bellard
            first_insn = 0;
807 7e4597d7 bellard
            nb_oargs = def->nb_oargs;
808 7e4597d7 bellard
            nb_iargs = def->nb_iargs;
809 7e4597d7 bellard
            nb_cargs = def->nb_cargs;
810 7e4597d7 bellard
        } else if (c == INDEX_op_call) {
811 c896fe29 bellard
            TCGArg arg;
812 4dc81f28 bellard
813 c896fe29 bellard
            /* variable number of arguments */
814 c896fe29 bellard
            arg = *args++;
815 c896fe29 bellard
            nb_oargs = arg >> 16;
816 c896fe29 bellard
            nb_iargs = arg & 0xffff;
817 c896fe29 bellard
            nb_cargs = def->nb_cargs;
818 c896fe29 bellard
819 7e4597d7 bellard
            fprintf(outfile, " %s ", def->name);
820 7e4597d7 bellard
821 b03cce8e bellard
            /* function name */
822 ac56dd48 pbrook
            fprintf(outfile, "%s",
823 e8996ee0 bellard
                    tcg_get_arg_str_idx(s, buf, sizeof(buf), args[nb_oargs + nb_iargs - 1]));
824 b03cce8e bellard
            /* flags */
825 b03cce8e bellard
            fprintf(outfile, ",$0x%" TCG_PRIlx,
826 b03cce8e bellard
                    args[nb_oargs + nb_iargs]);
827 b03cce8e bellard
            /* nb out args */
828 b03cce8e bellard
            fprintf(outfile, ",$%d", nb_oargs);
829 b03cce8e bellard
            for(i = 0; i < nb_oargs; i++) {
830 b03cce8e bellard
                fprintf(outfile, ",");
831 b03cce8e bellard
                fprintf(outfile, "%s",
832 b03cce8e bellard
                        tcg_get_arg_str_idx(s, buf, sizeof(buf), args[i]));
833 b03cce8e bellard
            }
834 b03cce8e bellard
            for(i = 0; i < (nb_iargs - 1); i++) {
835 c896fe29 bellard
                fprintf(outfile, ",");
836 39cf05d3 bellard
                if (args[nb_oargs + i] == TCG_CALL_DUMMY_ARG) {
837 39cf05d3 bellard
                    fprintf(outfile, "<dummy>");
838 39cf05d3 bellard
                } else {
839 39cf05d3 bellard
                    fprintf(outfile, "%s",
840 39cf05d3 bellard
                            tcg_get_arg_str_idx(s, buf, sizeof(buf), args[nb_oargs + i]));
841 39cf05d3 bellard
                }
842 b03cce8e bellard
            }
843 e8996ee0 bellard
        } else if (c == INDEX_op_movi_i32 
844 e8996ee0 bellard
#if TCG_TARGET_REG_BITS == 64
845 e8996ee0 bellard
                   || c == INDEX_op_movi_i64
846 e8996ee0 bellard
#endif
847 e8996ee0 bellard
                   ) {
848 e8996ee0 bellard
            tcg_target_ulong val;
849 e8996ee0 bellard
            TCGHelperInfo *th;
850 e8996ee0 bellard
851 e8996ee0 bellard
            nb_oargs = def->nb_oargs;
852 e8996ee0 bellard
            nb_iargs = def->nb_iargs;
853 e8996ee0 bellard
            nb_cargs = def->nb_cargs;
854 e8996ee0 bellard
            fprintf(outfile, " %s %s,$", def->name, 
855 e8996ee0 bellard
                    tcg_get_arg_str_idx(s, buf, sizeof(buf), args[0]));
856 e8996ee0 bellard
            val = args[1];
857 e8996ee0 bellard
            th = tcg_find_helper(s, val);
858 e8996ee0 bellard
            if (th) {
859 3e9a474e aurel32
                fprintf(outfile, "%s", th->name);
860 e8996ee0 bellard
            } else {
861 e8996ee0 bellard
                if (c == INDEX_op_movi_i32)
862 e8996ee0 bellard
                    fprintf(outfile, "0x%x", (uint32_t)val);
863 e8996ee0 bellard
                else
864 e8996ee0 bellard
                    fprintf(outfile, "0x%" PRIx64 , (uint64_t)val);
865 e8996ee0 bellard
            }
866 b03cce8e bellard
        } else {
867 7e4597d7 bellard
            fprintf(outfile, " %s ", def->name);
868 b03cce8e bellard
            if (c == INDEX_op_nopn) {
869 b03cce8e bellard
                /* variable number of arguments */
870 b03cce8e bellard
                nb_cargs = *args;
871 b03cce8e bellard
                nb_oargs = 0;
872 b03cce8e bellard
                nb_iargs = 0;
873 b03cce8e bellard
            } else {
874 b03cce8e bellard
                nb_oargs = def->nb_oargs;
875 b03cce8e bellard
                nb_iargs = def->nb_iargs;
876 b03cce8e bellard
                nb_cargs = def->nb_cargs;
877 b03cce8e bellard
            }
878 b03cce8e bellard
            
879 b03cce8e bellard
            k = 0;
880 b03cce8e bellard
            for(i = 0; i < nb_oargs; i++) {
881 b03cce8e bellard
                if (k != 0)
882 b03cce8e bellard
                    fprintf(outfile, ",");
883 b03cce8e bellard
                fprintf(outfile, "%s",
884 b03cce8e bellard
                        tcg_get_arg_str_idx(s, buf, sizeof(buf), args[k++]));
885 b03cce8e bellard
            }
886 b03cce8e bellard
            for(i = 0; i < nb_iargs; i++) {
887 b03cce8e bellard
                if (k != 0)
888 b03cce8e bellard
                    fprintf(outfile, ",");
889 b03cce8e bellard
                fprintf(outfile, "%s",
890 b03cce8e bellard
                        tcg_get_arg_str_idx(s, buf, sizeof(buf), args[k++]));
891 b03cce8e bellard
            }
892 be210acb Richard Henderson
            switch (c) {
893 be210acb Richard Henderson
            case INDEX_op_brcond_i32:
894 be210acb Richard Henderson
#if TCG_TARGET_REG_BITS == 32
895 be210acb Richard Henderson
            case INDEX_op_brcond2_i32:
896 be210acb Richard Henderson
#elif TCG_TARGET_REG_BITS == 64
897 be210acb Richard Henderson
            case INDEX_op_brcond_i64:
898 be210acb Richard Henderson
#endif
899 be210acb Richard Henderson
            case INDEX_op_setcond_i32:
900 f48f3ede blueswir1
#if TCG_TARGET_REG_BITS == 32
901 be210acb Richard Henderson
            case INDEX_op_setcond2_i32:
902 f48f3ede blueswir1
#elif TCG_TARGET_REG_BITS == 64
903 be210acb Richard Henderson
            case INDEX_op_setcond_i64:
904 f48f3ede blueswir1
#endif
905 f48f3ede blueswir1
                if (args[k] < ARRAY_SIZE(cond_name) && cond_name[args[k]])
906 f48f3ede blueswir1
                    fprintf(outfile, ",%s", cond_name[args[k++]]);
907 f48f3ede blueswir1
                else
908 f48f3ede blueswir1
                    fprintf(outfile, ",$0x%" TCG_PRIlx, args[k++]);
909 f48f3ede blueswir1
                i = 1;
910 be210acb Richard Henderson
                break;
911 be210acb Richard Henderson
            default:
912 f48f3ede blueswir1
                i = 0;
913 be210acb Richard Henderson
                break;
914 be210acb Richard Henderson
            }
915 f48f3ede blueswir1
            for(; i < nb_cargs; i++) {
916 b03cce8e bellard
                if (k != 0)
917 b03cce8e bellard
                    fprintf(outfile, ",");
918 b03cce8e bellard
                arg = args[k++];
919 b03cce8e bellard
                fprintf(outfile, "$0x%" TCG_PRIlx, arg);
920 b03cce8e bellard
            }
921 c896fe29 bellard
        }
922 c896fe29 bellard
        fprintf(outfile, "\n");
923 c896fe29 bellard
        args += nb_iargs + nb_oargs + nb_cargs;
924 c896fe29 bellard
    }
925 c896fe29 bellard
}
926 c896fe29 bellard
927 c896fe29 bellard
/* we give more priority to constraints with less registers */
928 c896fe29 bellard
static int get_constraint_priority(const TCGOpDef *def, int k)
929 c896fe29 bellard
{
930 c896fe29 bellard
    const TCGArgConstraint *arg_ct;
931 c896fe29 bellard
932 c896fe29 bellard
    int i, n;
933 c896fe29 bellard
    arg_ct = &def->args_ct[k];
934 c896fe29 bellard
    if (arg_ct->ct & TCG_CT_ALIAS) {
935 c896fe29 bellard
        /* an alias is equivalent to a single register */
936 c896fe29 bellard
        n = 1;
937 c896fe29 bellard
    } else {
938 c896fe29 bellard
        if (!(arg_ct->ct & TCG_CT_REG))
939 c896fe29 bellard
            return 0;
940 c896fe29 bellard
        n = 0;
941 c896fe29 bellard
        for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
942 c896fe29 bellard
            if (tcg_regset_test_reg(arg_ct->u.regs, i))
943 c896fe29 bellard
                n++;
944 c896fe29 bellard
        }
945 c896fe29 bellard
    }
946 c896fe29 bellard
    return TCG_TARGET_NB_REGS - n + 1;
947 c896fe29 bellard
}
948 c896fe29 bellard
949 c896fe29 bellard
/* sort from highest priority to lowest */
950 c896fe29 bellard
static void sort_constraints(TCGOpDef *def, int start, int n)
951 c896fe29 bellard
{
952 c896fe29 bellard
    int i, j, p1, p2, tmp;
953 c896fe29 bellard
954 c896fe29 bellard
    for(i = 0; i < n; i++)
955 c896fe29 bellard
        def->sorted_args[start + i] = start + i;
956 c896fe29 bellard
    if (n <= 1)
957 c896fe29 bellard
        return;
958 c896fe29 bellard
    for(i = 0; i < n - 1; i++) {
959 c896fe29 bellard
        for(j = i + 1; j < n; j++) {
960 c896fe29 bellard
            p1 = get_constraint_priority(def, def->sorted_args[start + i]);
961 c896fe29 bellard
            p2 = get_constraint_priority(def, def->sorted_args[start + j]);
962 c896fe29 bellard
            if (p1 < p2) {
963 c896fe29 bellard
                tmp = def->sorted_args[start + i];
964 c896fe29 bellard
                def->sorted_args[start + i] = def->sorted_args[start + j];
965 c896fe29 bellard
                def->sorted_args[start + j] = tmp;
966 c896fe29 bellard
            }
967 c896fe29 bellard
        }
968 c896fe29 bellard
    }
969 c896fe29 bellard
}
970 c896fe29 bellard
971 c896fe29 bellard
void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs)
972 c896fe29 bellard
{
973 c896fe29 bellard
    int op;
974 c896fe29 bellard
    TCGOpDef *def;
975 c896fe29 bellard
    const char *ct_str;
976 c896fe29 bellard
    int i, nb_args;
977 c896fe29 bellard
978 c896fe29 bellard
    for(;;) {
979 c896fe29 bellard
        if (tdefs->op < 0)
980 c896fe29 bellard
            break;
981 c896fe29 bellard
        op = tdefs->op;
982 c896fe29 bellard
        assert(op >= 0 && op < NB_OPS);
983 c896fe29 bellard
        def = &tcg_op_defs[op];
984 c68aaa18 Stefan Weil
#if defined(CONFIG_DEBUG_TCG)
985 c68aaa18 Stefan Weil
        /* Duplicate entry in op definitions? */
986 c68aaa18 Stefan Weil
        assert(!def->used);
987 c68aaa18 Stefan Weil
        def->used = 1;
988 c68aaa18 Stefan Weil
#endif
989 c896fe29 bellard
        nb_args = def->nb_iargs + def->nb_oargs;
990 c896fe29 bellard
        for(i = 0; i < nb_args; i++) {
991 c896fe29 bellard
            ct_str = tdefs->args_ct_str[i];
992 c68aaa18 Stefan Weil
            /* Incomplete TCGTargetOpDef entry? */
993 c68aaa18 Stefan Weil
            assert(ct_str != NULL);
994 c896fe29 bellard
            tcg_regset_clear(def->args_ct[i].u.regs);
995 c896fe29 bellard
            def->args_ct[i].ct = 0;
996 c896fe29 bellard
            if (ct_str[0] >= '0' && ct_str[0] <= '9') {
997 c896fe29 bellard
                int oarg;
998 c896fe29 bellard
                oarg = ct_str[0] - '0';
999 c896fe29 bellard
                assert(oarg < def->nb_oargs);
1000 c896fe29 bellard
                assert(def->args_ct[oarg].ct & TCG_CT_REG);
1001 c896fe29 bellard
                /* TCG_CT_ALIAS is for the output arguments. The input
1002 5ff9d6a4 bellard
                   argument is tagged with TCG_CT_IALIAS. */
1003 c896fe29 bellard
                def->args_ct[i] = def->args_ct[oarg];
1004 5ff9d6a4 bellard
                def->args_ct[oarg].ct = TCG_CT_ALIAS;
1005 5ff9d6a4 bellard
                def->args_ct[oarg].alias_index = i;
1006 c896fe29 bellard
                def->args_ct[i].ct |= TCG_CT_IALIAS;
1007 5ff9d6a4 bellard
                def->args_ct[i].alias_index = oarg;
1008 c896fe29 bellard
            } else {
1009 c896fe29 bellard
                for(;;) {
1010 c896fe29 bellard
                    if (*ct_str == '\0')
1011 c896fe29 bellard
                        break;
1012 c896fe29 bellard
                    switch(*ct_str) {
1013 c896fe29 bellard
                    case 'i':
1014 c896fe29 bellard
                        def->args_ct[i].ct |= TCG_CT_CONST;
1015 c896fe29 bellard
                        ct_str++;
1016 c896fe29 bellard
                        break;
1017 c896fe29 bellard
                    default:
1018 c896fe29 bellard
                        if (target_parse_constraint(&def->args_ct[i], &ct_str) < 0) {
1019 c896fe29 bellard
                            fprintf(stderr, "Invalid constraint '%s' for arg %d of operation '%s'\n",
1020 c896fe29 bellard
                                    ct_str, i, def->name);
1021 c896fe29 bellard
                            exit(1);
1022 c896fe29 bellard
                        }
1023 c896fe29 bellard
                    }
1024 c896fe29 bellard
                }
1025 c896fe29 bellard
            }
1026 c896fe29 bellard
        }
1027 c896fe29 bellard
1028 c68aaa18 Stefan Weil
        /* TCGTargetOpDef entry with too much information? */
1029 c68aaa18 Stefan Weil
        assert(i == TCG_MAX_OP_ARGS || tdefs->args_ct_str[i] == NULL);
1030 c68aaa18 Stefan Weil
1031 c896fe29 bellard
        /* sort the constraints (XXX: this is just an heuristic) */
1032 c896fe29 bellard
        sort_constraints(def, 0, def->nb_oargs);
1033 c896fe29 bellard
        sort_constraints(def, def->nb_oargs, def->nb_iargs);
1034 c896fe29 bellard
1035 c896fe29 bellard
#if 0
1036 c896fe29 bellard
        {
1037 c896fe29 bellard
            int i;
1038 c896fe29 bellard

1039 c896fe29 bellard
            printf("%s: sorted=", def->name);
1040 c896fe29 bellard
            for(i = 0; i < def->nb_oargs + def->nb_iargs; i++)
1041 c896fe29 bellard
                printf(" %d", def->sorted_args[i]);
1042 c896fe29 bellard
            printf("\n");
1043 c896fe29 bellard
        }
1044 c896fe29 bellard
#endif
1045 c896fe29 bellard
        tdefs++;
1046 c896fe29 bellard
    }
1047 c896fe29 bellard
1048 c68aaa18 Stefan Weil
#if defined(CONFIG_DEBUG_TCG)
1049 c68aaa18 Stefan Weil
    for (op = 0; op < ARRAY_SIZE(tcg_op_defs); op++) {
1050 c68aaa18 Stefan Weil
        if (op < INDEX_op_call || op == INDEX_op_debug_insn_start) {
1051 c68aaa18 Stefan Weil
            /* Wrong entry in op definitions? */
1052 c68aaa18 Stefan Weil
            assert(!tcg_op_defs[op].used);
1053 c68aaa18 Stefan Weil
        } else {
1054 c68aaa18 Stefan Weil
            /* Missing entry in op definitions? */
1055 c68aaa18 Stefan Weil
            assert(tcg_op_defs[op].used);
1056 c68aaa18 Stefan Weil
        }
1057 c68aaa18 Stefan Weil
    }
1058 c68aaa18 Stefan Weil
#endif
1059 c896fe29 bellard
}
1060 c896fe29 bellard
1061 c896fe29 bellard
#ifdef USE_LIVENESS_ANALYSIS
1062 c896fe29 bellard
1063 c896fe29 bellard
/* set a nop for an operation using 'nb_args' */
1064 c896fe29 bellard
static inline void tcg_set_nop(TCGContext *s, uint16_t *opc_ptr, 
1065 c896fe29 bellard
                               TCGArg *args, int nb_args)
1066 c896fe29 bellard
{
1067 c896fe29 bellard
    if (nb_args == 0) {
1068 c896fe29 bellard
        *opc_ptr = INDEX_op_nop;
1069 c896fe29 bellard
    } else {
1070 c896fe29 bellard
        *opc_ptr = INDEX_op_nopn;
1071 c896fe29 bellard
        args[0] = nb_args;
1072 c896fe29 bellard
        args[nb_args - 1] = nb_args;
1073 c896fe29 bellard
    }
1074 c896fe29 bellard
}
1075 c896fe29 bellard
1076 641d5fbe bellard
/* liveness analysis: end of function: globals are live, temps are
1077 641d5fbe bellard
   dead. */
1078 641d5fbe bellard
/* XXX: at this stage, not used as there would be little gains because
1079 641d5fbe bellard
   most TBs end with a conditional jump. */
1080 641d5fbe bellard
static inline void tcg_la_func_end(TCGContext *s, uint8_t *dead_temps)
1081 c896fe29 bellard
{
1082 c896fe29 bellard
    memset(dead_temps, 0, s->nb_globals);
1083 c896fe29 bellard
    memset(dead_temps + s->nb_globals, 1, s->nb_temps - s->nb_globals);
1084 c896fe29 bellard
}
1085 c896fe29 bellard
1086 641d5fbe bellard
/* liveness analysis: end of basic block: globals are live, temps are
1087 641d5fbe bellard
   dead, local temps are live. */
1088 641d5fbe bellard
static inline void tcg_la_bb_end(TCGContext *s, uint8_t *dead_temps)
1089 641d5fbe bellard
{
1090 641d5fbe bellard
    int i;
1091 641d5fbe bellard
    TCGTemp *ts;
1092 641d5fbe bellard
1093 641d5fbe bellard
    memset(dead_temps, 0, s->nb_globals);
1094 641d5fbe bellard
    ts = &s->temps[s->nb_globals];
1095 641d5fbe bellard
    for(i = s->nb_globals; i < s->nb_temps; i++) {
1096 641d5fbe bellard
        if (ts->temp_local)
1097 641d5fbe bellard
            dead_temps[i] = 0;
1098 641d5fbe bellard
        else
1099 641d5fbe bellard
            dead_temps[i] = 1;
1100 641d5fbe bellard
        ts++;
1101 641d5fbe bellard
    }
1102 641d5fbe bellard
}
1103 641d5fbe bellard
1104 c896fe29 bellard
/* Liveness analysis : update the opc_dead_iargs array to tell if a
1105 c896fe29 bellard
   given input arguments is dead. Instructions updating dead
1106 c896fe29 bellard
   temporaries are removed. */
1107 8fcd3692 blueswir1
static void tcg_liveness_analysis(TCGContext *s)
1108 c896fe29 bellard
{
1109 c896fe29 bellard
    int i, op_index, op, nb_args, nb_iargs, nb_oargs, arg, nb_ops;
1110 c896fe29 bellard
    TCGArg *args;
1111 c896fe29 bellard
    const TCGOpDef *def;
1112 c896fe29 bellard
    uint8_t *dead_temps;
1113 c896fe29 bellard
    unsigned int dead_iargs;
1114 c896fe29 bellard
    
1115 c896fe29 bellard
    gen_opc_ptr++; /* skip end */
1116 c896fe29 bellard
1117 c896fe29 bellard
    nb_ops = gen_opc_ptr - gen_opc_buf;
1118 c896fe29 bellard
1119 94f4af02 Aurelien Jarno
    s->op_dead_iargs = tcg_malloc(nb_ops * sizeof(uint16_t));
1120 c896fe29 bellard
    
1121 c896fe29 bellard
    dead_temps = tcg_malloc(s->nb_temps);
1122 c896fe29 bellard
    memset(dead_temps, 1, s->nb_temps);
1123 c896fe29 bellard
1124 c896fe29 bellard
    args = gen_opparam_ptr;
1125 c896fe29 bellard
    op_index = nb_ops - 1;
1126 c896fe29 bellard
    while (op_index >= 0) {
1127 c896fe29 bellard
        op = gen_opc_buf[op_index];
1128 c896fe29 bellard
        def = &tcg_op_defs[op];
1129 c896fe29 bellard
        switch(op) {
1130 c896fe29 bellard
        case INDEX_op_call:
1131 c6e113f5 bellard
            {
1132 c6e113f5 bellard
                int call_flags;
1133 c896fe29 bellard
1134 c6e113f5 bellard
                nb_args = args[-1];
1135 c6e113f5 bellard
                args -= nb_args;
1136 c6e113f5 bellard
                nb_iargs = args[0] & 0xffff;
1137 c6e113f5 bellard
                nb_oargs = args[0] >> 16;
1138 c6e113f5 bellard
                args++;
1139 c6e113f5 bellard
                call_flags = args[nb_oargs + nb_iargs];
1140 c6e113f5 bellard
1141 c6e113f5 bellard
                /* pure functions can be removed if their result is not
1142 c6e113f5 bellard
                   used */
1143 c6e113f5 bellard
                if (call_flags & TCG_CALL_PURE) {
1144 c6e113f5 bellard
                    for(i = 0; i < nb_oargs; i++) {
1145 c6e113f5 bellard
                        arg = args[i];
1146 c6e113f5 bellard
                        if (!dead_temps[arg])
1147 c6e113f5 bellard
                            goto do_not_remove_call;
1148 c6e113f5 bellard
                    }
1149 c6e113f5 bellard
                    tcg_set_nop(s, gen_opc_buf + op_index, 
1150 c6e113f5 bellard
                                args - 1, nb_args);
1151 c6e113f5 bellard
                } else {
1152 c6e113f5 bellard
                do_not_remove_call:
1153 c896fe29 bellard
1154 c6e113f5 bellard
                    /* output args are dead */
1155 c6e113f5 bellard
                    for(i = 0; i < nb_oargs; i++) {
1156 c6e113f5 bellard
                        arg = args[i];
1157 c6e113f5 bellard
                        dead_temps[arg] = 1;
1158 c6e113f5 bellard
                    }
1159 c6e113f5 bellard
                    
1160 b9c18f56 aurel32
                    if (!(call_flags & TCG_CALL_CONST)) {
1161 b9c18f56 aurel32
                        /* globals are live (they may be used by the call) */
1162 b9c18f56 aurel32
                        memset(dead_temps, 0, s->nb_globals);
1163 b9c18f56 aurel32
                    }
1164 b9c18f56 aurel32
1165 c6e113f5 bellard
                    /* input args are live */
1166 c6e113f5 bellard
                    dead_iargs = 0;
1167 c6e113f5 bellard
                    for(i = 0; i < nb_iargs; i++) {
1168 c6e113f5 bellard
                        arg = args[i + nb_oargs];
1169 39cf05d3 bellard
                        if (arg != TCG_CALL_DUMMY_ARG) {
1170 39cf05d3 bellard
                            if (dead_temps[arg]) {
1171 39cf05d3 bellard
                                dead_iargs |= (1 << i);
1172 39cf05d3 bellard
                            }
1173 39cf05d3 bellard
                            dead_temps[arg] = 0;
1174 c6e113f5 bellard
                        }
1175 c6e113f5 bellard
                    }
1176 c6e113f5 bellard
                    s->op_dead_iargs[op_index] = dead_iargs;
1177 c896fe29 bellard
                }
1178 c6e113f5 bellard
                args--;
1179 c896fe29 bellard
            }
1180 c896fe29 bellard
            break;
1181 c896fe29 bellard
        case INDEX_op_set_label:
1182 c896fe29 bellard
            args--;
1183 c896fe29 bellard
            /* mark end of basic block */
1184 c896fe29 bellard
            tcg_la_bb_end(s, dead_temps);
1185 c896fe29 bellard
            break;
1186 7e4597d7 bellard
        case INDEX_op_debug_insn_start:
1187 7e4597d7 bellard
            args -= def->nb_args;
1188 7e4597d7 bellard
            break;
1189 c896fe29 bellard
        case INDEX_op_nopn:
1190 c896fe29 bellard
            nb_args = args[-1];
1191 c896fe29 bellard
            args -= nb_args;
1192 c896fe29 bellard
            break;
1193 5ff9d6a4 bellard
        case INDEX_op_discard:
1194 5ff9d6a4 bellard
            args--;
1195 5ff9d6a4 bellard
            /* mark the temporary as dead */
1196 5ff9d6a4 bellard
            dead_temps[args[0]] = 1;
1197 5ff9d6a4 bellard
            break;
1198 c896fe29 bellard
        case INDEX_op_end:
1199 c896fe29 bellard
            break;
1200 c896fe29 bellard
            /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
1201 c896fe29 bellard
        default:
1202 49516bc0 aurel32
            args -= def->nb_args;
1203 49516bc0 aurel32
            nb_iargs = def->nb_iargs;
1204 49516bc0 aurel32
            nb_oargs = def->nb_oargs;
1205 c896fe29 bellard
1206 49516bc0 aurel32
            /* Test if the operation can be removed because all
1207 49516bc0 aurel32
               its outputs are dead. We assume that nb_oargs == 0
1208 49516bc0 aurel32
               implies side effects */
1209 49516bc0 aurel32
            if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) {
1210 49516bc0 aurel32
                for(i = 0; i < nb_oargs; i++) {
1211 49516bc0 aurel32
                    arg = args[i];
1212 49516bc0 aurel32
                    if (!dead_temps[arg])
1213 49516bc0 aurel32
                        goto do_not_remove;
1214 49516bc0 aurel32
                }
1215 49516bc0 aurel32
                tcg_set_nop(s, gen_opc_buf + op_index, args, def->nb_args);
1216 c896fe29 bellard
#ifdef CONFIG_PROFILER
1217 49516bc0 aurel32
                s->del_op_count++;
1218 c896fe29 bellard
#endif
1219 49516bc0 aurel32
            } else {
1220 49516bc0 aurel32
            do_not_remove:
1221 c896fe29 bellard
1222 49516bc0 aurel32
                /* output args are dead */
1223 49516bc0 aurel32
                for(i = 0; i < nb_oargs; i++) {
1224 49516bc0 aurel32
                    arg = args[i];
1225 49516bc0 aurel32
                    dead_temps[arg] = 1;
1226 49516bc0 aurel32
                }
1227 49516bc0 aurel32
1228 49516bc0 aurel32
                /* if end of basic block, update */
1229 49516bc0 aurel32
                if (def->flags & TCG_OPF_BB_END) {
1230 49516bc0 aurel32
                    tcg_la_bb_end(s, dead_temps);
1231 49516bc0 aurel32
                } else if (def->flags & TCG_OPF_CALL_CLOBBER) {
1232 49516bc0 aurel32
                    /* globals are live */
1233 49516bc0 aurel32
                    memset(dead_temps, 0, s->nb_globals);
1234 49516bc0 aurel32
                }
1235 49516bc0 aurel32
1236 49516bc0 aurel32
                /* input args are live */
1237 49516bc0 aurel32
                dead_iargs = 0;
1238 49516bc0 aurel32
                for(i = 0; i < nb_iargs; i++) {
1239 49516bc0 aurel32
                    arg = args[i + nb_oargs];
1240 49516bc0 aurel32
                    if (dead_temps[arg]) {
1241 49516bc0 aurel32
                        dead_iargs |= (1 << i);
1242 c896fe29 bellard
                    }
1243 49516bc0 aurel32
                    dead_temps[arg] = 0;
1244 c896fe29 bellard
                }
1245 49516bc0 aurel32
                s->op_dead_iargs[op_index] = dead_iargs;
1246 c896fe29 bellard
            }
1247 c896fe29 bellard
            break;
1248 c896fe29 bellard
        }
1249 c896fe29 bellard
        op_index--;
1250 c896fe29 bellard
    }
1251 c896fe29 bellard
1252 c896fe29 bellard
    if (args != gen_opparam_buf)
1253 c896fe29 bellard
        tcg_abort();
1254 c896fe29 bellard
}
1255 c896fe29 bellard
#else
1256 c896fe29 bellard
/* dummy liveness analysis */
1257 c896fe29 bellard
void tcg_liveness_analysis(TCGContext *s)
1258 c896fe29 bellard
{
1259 c896fe29 bellard
    int nb_ops;
1260 c896fe29 bellard
    nb_ops = gen_opc_ptr - gen_opc_buf;
1261 c896fe29 bellard
1262 c896fe29 bellard
    s->op_dead_iargs = tcg_malloc(nb_ops * sizeof(uint16_t));
1263 c896fe29 bellard
    memset(s->op_dead_iargs, 0, nb_ops * sizeof(uint16_t));
1264 c896fe29 bellard
}
1265 c896fe29 bellard
#endif
1266 c896fe29 bellard
1267 c896fe29 bellard
#ifndef NDEBUG
1268 c896fe29 bellard
static void dump_regs(TCGContext *s)
1269 c896fe29 bellard
{
1270 c896fe29 bellard
    TCGTemp *ts;
1271 c896fe29 bellard
    int i;
1272 c896fe29 bellard
    char buf[64];
1273 c896fe29 bellard
1274 c896fe29 bellard
    for(i = 0; i < s->nb_temps; i++) {
1275 c896fe29 bellard
        ts = &s->temps[i];
1276 ac56dd48 pbrook
        printf("  %10s: ", tcg_get_arg_str_idx(s, buf, sizeof(buf), i));
1277 c896fe29 bellard
        switch(ts->val_type) {
1278 c896fe29 bellard
        case TEMP_VAL_REG:
1279 c896fe29 bellard
            printf("%s", tcg_target_reg_names[ts->reg]);
1280 c896fe29 bellard
            break;
1281 c896fe29 bellard
        case TEMP_VAL_MEM:
1282 c896fe29 bellard
            printf("%d(%s)", (int)ts->mem_offset, tcg_target_reg_names[ts->mem_reg]);
1283 c896fe29 bellard
            break;
1284 c896fe29 bellard
        case TEMP_VAL_CONST:
1285 c896fe29 bellard
            printf("$0x%" TCG_PRIlx, ts->val);
1286 c896fe29 bellard
            break;
1287 c896fe29 bellard
        case TEMP_VAL_DEAD:
1288 c896fe29 bellard
            printf("D");
1289 c896fe29 bellard
            break;
1290 c896fe29 bellard
        default:
1291 c896fe29 bellard
            printf("???");
1292 c896fe29 bellard
            break;
1293 c896fe29 bellard
        }
1294 c896fe29 bellard
        printf("\n");
1295 c896fe29 bellard
    }
1296 c896fe29 bellard
1297 c896fe29 bellard
    for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
1298 c896fe29 bellard
        if (s->reg_to_temp[i] >= 0) {
1299 c896fe29 bellard
            printf("%s: %s\n", 
1300 c896fe29 bellard
                   tcg_target_reg_names[i], 
1301 ac56dd48 pbrook
                   tcg_get_arg_str_idx(s, buf, sizeof(buf), s->reg_to_temp[i]));
1302 c896fe29 bellard
        }
1303 c896fe29 bellard
    }
1304 c896fe29 bellard
}
1305 c896fe29 bellard
1306 c896fe29 bellard
static void check_regs(TCGContext *s)
1307 c896fe29 bellard
{
1308 c896fe29 bellard
    int reg, k;
1309 c896fe29 bellard
    TCGTemp *ts;
1310 c896fe29 bellard
    char buf[64];
1311 c896fe29 bellard
1312 c896fe29 bellard
    for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
1313 c896fe29 bellard
        k = s->reg_to_temp[reg];
1314 c896fe29 bellard
        if (k >= 0) {
1315 c896fe29 bellard
            ts = &s->temps[k];
1316 c896fe29 bellard
            if (ts->val_type != TEMP_VAL_REG ||
1317 c896fe29 bellard
                ts->reg != reg) {
1318 c896fe29 bellard
                printf("Inconsistency for register %s:\n", 
1319 c896fe29 bellard
                       tcg_target_reg_names[reg]);
1320 b03cce8e bellard
                goto fail;
1321 c896fe29 bellard
            }
1322 c896fe29 bellard
        }
1323 c896fe29 bellard
    }
1324 c896fe29 bellard
    for(k = 0; k < s->nb_temps; k++) {
1325 c896fe29 bellard
        ts = &s->temps[k];
1326 c896fe29 bellard
        if (ts->val_type == TEMP_VAL_REG &&
1327 c896fe29 bellard
            !ts->fixed_reg &&
1328 c896fe29 bellard
            s->reg_to_temp[ts->reg] != k) {
1329 c896fe29 bellard
                printf("Inconsistency for temp %s:\n", 
1330 ac56dd48 pbrook
                       tcg_get_arg_str_idx(s, buf, sizeof(buf), k));
1331 b03cce8e bellard
        fail:
1332 c896fe29 bellard
                printf("reg state:\n");
1333 c896fe29 bellard
                dump_regs(s);
1334 c896fe29 bellard
                tcg_abort();
1335 c896fe29 bellard
        }
1336 c896fe29 bellard
    }
1337 c896fe29 bellard
}
1338 c896fe29 bellard
#endif
1339 c896fe29 bellard
1340 c896fe29 bellard
static void temp_allocate_frame(TCGContext *s, int temp)
1341 c896fe29 bellard
{
1342 c896fe29 bellard
    TCGTemp *ts;
1343 c896fe29 bellard
    ts = &s->temps[temp];
1344 c896fe29 bellard
    s->current_frame_offset = (s->current_frame_offset + sizeof(tcg_target_long) - 1) & ~(sizeof(tcg_target_long) - 1);
1345 c896fe29 bellard
    if (s->current_frame_offset + sizeof(tcg_target_long) > s->frame_end)
1346 5ff9d6a4 bellard
        tcg_abort();
1347 c896fe29 bellard
    ts->mem_offset = s->current_frame_offset;
1348 c896fe29 bellard
    ts->mem_reg = s->frame_reg;
1349 c896fe29 bellard
    ts->mem_allocated = 1;
1350 c896fe29 bellard
    s->current_frame_offset += sizeof(tcg_target_long);
1351 c896fe29 bellard
}
1352 c896fe29 bellard
1353 c896fe29 bellard
/* free register 'reg' by spilling the corresponding temporary if necessary */
1354 c896fe29 bellard
static void tcg_reg_free(TCGContext *s, int reg)
1355 c896fe29 bellard
{
1356 c896fe29 bellard
    TCGTemp *ts;
1357 c896fe29 bellard
    int temp;
1358 c896fe29 bellard
1359 c896fe29 bellard
    temp = s->reg_to_temp[reg];
1360 c896fe29 bellard
    if (temp != -1) {
1361 c896fe29 bellard
        ts = &s->temps[temp];
1362 c896fe29 bellard
        assert(ts->val_type == TEMP_VAL_REG);
1363 c896fe29 bellard
        if (!ts->mem_coherent) {
1364 c896fe29 bellard
            if (!ts->mem_allocated) 
1365 c896fe29 bellard
                temp_allocate_frame(s, temp);
1366 e4d5434c blueswir1
            tcg_out_st(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
1367 c896fe29 bellard
        }
1368 c896fe29 bellard
        ts->val_type = TEMP_VAL_MEM;
1369 c896fe29 bellard
        s->reg_to_temp[reg] = -1;
1370 c896fe29 bellard
    }
1371 c896fe29 bellard
}
1372 c896fe29 bellard
1373 c896fe29 bellard
/* Allocate a register belonging to reg1 & ~reg2 */
1374 c896fe29 bellard
static int tcg_reg_alloc(TCGContext *s, TCGRegSet reg1, TCGRegSet reg2)
1375 c896fe29 bellard
{
1376 c896fe29 bellard
    int i, reg;
1377 c896fe29 bellard
    TCGRegSet reg_ct;
1378 c896fe29 bellard
1379 c896fe29 bellard
    tcg_regset_andnot(reg_ct, reg1, reg2);
1380 c896fe29 bellard
1381 c896fe29 bellard
    /* first try free registers */
1382 0954d0d9 blueswir1
    for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
1383 c896fe29 bellard
        reg = tcg_target_reg_alloc_order[i];
1384 c896fe29 bellard
        if (tcg_regset_test_reg(reg_ct, reg) && s->reg_to_temp[reg] == -1)
1385 c896fe29 bellard
            return reg;
1386 c896fe29 bellard
    }
1387 c896fe29 bellard
1388 c896fe29 bellard
    /* XXX: do better spill choice */
1389 0954d0d9 blueswir1
    for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
1390 c896fe29 bellard
        reg = tcg_target_reg_alloc_order[i];
1391 c896fe29 bellard
        if (tcg_regset_test_reg(reg_ct, reg)) {
1392 c896fe29 bellard
            tcg_reg_free(s, reg);
1393 c896fe29 bellard
            return reg;
1394 c896fe29 bellard
        }
1395 c896fe29 bellard
    }
1396 c896fe29 bellard
1397 c896fe29 bellard
    tcg_abort();
1398 c896fe29 bellard
}
1399 c896fe29 bellard
1400 641d5fbe bellard
/* save a temporary to memory. 'allocated_regs' is used in case a
1401 641d5fbe bellard
   temporary registers needs to be allocated to store a constant. */
1402 641d5fbe bellard
static void temp_save(TCGContext *s, int temp, TCGRegSet allocated_regs)
1403 641d5fbe bellard
{
1404 641d5fbe bellard
    TCGTemp *ts;
1405 641d5fbe bellard
    int reg;
1406 641d5fbe bellard
1407 641d5fbe bellard
    ts = &s->temps[temp];
1408 641d5fbe bellard
    if (!ts->fixed_reg) {
1409 641d5fbe bellard
        switch(ts->val_type) {
1410 641d5fbe bellard
        case TEMP_VAL_REG:
1411 641d5fbe bellard
            tcg_reg_free(s, ts->reg);
1412 641d5fbe bellard
            break;
1413 641d5fbe bellard
        case TEMP_VAL_DEAD:
1414 641d5fbe bellard
            ts->val_type = TEMP_VAL_MEM;
1415 641d5fbe bellard
            break;
1416 641d5fbe bellard
        case TEMP_VAL_CONST:
1417 d6859202 Aurelien Jarno
            reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type], 
1418 d6859202 Aurelien Jarno
                                allocated_regs);
1419 641d5fbe bellard
            if (!ts->mem_allocated) 
1420 641d5fbe bellard
                temp_allocate_frame(s, temp);
1421 d6859202 Aurelien Jarno
            tcg_out_movi(s, ts->type, reg, ts->val);
1422 d6859202 Aurelien Jarno
            tcg_out_st(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
1423 641d5fbe bellard
            ts->val_type = TEMP_VAL_MEM;
1424 641d5fbe bellard
            break;
1425 641d5fbe bellard
        case TEMP_VAL_MEM:
1426 641d5fbe bellard
            break;
1427 641d5fbe bellard
        default:
1428 641d5fbe bellard
            tcg_abort();
1429 641d5fbe bellard
        }
1430 641d5fbe bellard
    }
1431 641d5fbe bellard
}
1432 641d5fbe bellard
1433 e5097dc8 bellard
/* save globals to their cannonical location and assume they can be
1434 e8996ee0 bellard
   modified be the following code. 'allocated_regs' is used in case a
1435 e8996ee0 bellard
   temporary registers needs to be allocated to store a constant. */
1436 e8996ee0 bellard
static void save_globals(TCGContext *s, TCGRegSet allocated_regs)
1437 c896fe29 bellard
{
1438 641d5fbe bellard
    int i;
1439 c896fe29 bellard
1440 c896fe29 bellard
    for(i = 0; i < s->nb_globals; i++) {
1441 641d5fbe bellard
        temp_save(s, i, allocated_regs);
1442 c896fe29 bellard
    }
1443 e5097dc8 bellard
}
1444 e5097dc8 bellard
1445 e5097dc8 bellard
/* at the end of a basic block, we assume all temporaries are dead and
1446 e8996ee0 bellard
   all globals are stored at their canonical location. */
1447 e8996ee0 bellard
static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs)
1448 e5097dc8 bellard
{
1449 e5097dc8 bellard
    TCGTemp *ts;
1450 e5097dc8 bellard
    int i;
1451 e5097dc8 bellard
1452 c896fe29 bellard
    for(i = s->nb_globals; i < s->nb_temps; i++) {
1453 c896fe29 bellard
        ts = &s->temps[i];
1454 641d5fbe bellard
        if (ts->temp_local) {
1455 641d5fbe bellard
            temp_save(s, i, allocated_regs);
1456 641d5fbe bellard
        } else {
1457 641d5fbe bellard
            if (ts->val_type == TEMP_VAL_REG) {
1458 641d5fbe bellard
                s->reg_to_temp[ts->reg] = -1;
1459 641d5fbe bellard
            }
1460 641d5fbe bellard
            ts->val_type = TEMP_VAL_DEAD;
1461 c896fe29 bellard
        }
1462 c896fe29 bellard
    }
1463 e8996ee0 bellard
1464 e8996ee0 bellard
    save_globals(s, allocated_regs);
1465 c896fe29 bellard
}
1466 c896fe29 bellard
1467 c896fe29 bellard
#define IS_DEAD_IARG(n) ((dead_iargs >> (n)) & 1)
1468 c896fe29 bellard
1469 e8996ee0 bellard
static void tcg_reg_alloc_movi(TCGContext *s, const TCGArg *args)
1470 e8996ee0 bellard
{
1471 e8996ee0 bellard
    TCGTemp *ots;
1472 e8996ee0 bellard
    tcg_target_ulong val;
1473 e8996ee0 bellard
1474 e8996ee0 bellard
    ots = &s->temps[args[0]];
1475 e8996ee0 bellard
    val = args[1];
1476 e8996ee0 bellard
1477 e8996ee0 bellard
    if (ots->fixed_reg) {
1478 e8996ee0 bellard
        /* for fixed registers, we do not do any constant
1479 e8996ee0 bellard
           propagation */
1480 e8996ee0 bellard
        tcg_out_movi(s, ots->type, ots->reg, val);
1481 e8996ee0 bellard
    } else {
1482 1235fc06 ths
        /* The movi is not explicitly generated here */
1483 e8996ee0 bellard
        if (ots->val_type == TEMP_VAL_REG)
1484 e8996ee0 bellard
            s->reg_to_temp[ots->reg] = -1;
1485 e8996ee0 bellard
        ots->val_type = TEMP_VAL_CONST;
1486 e8996ee0 bellard
        ots->val = val;
1487 e8996ee0 bellard
    }
1488 e8996ee0 bellard
}
1489 e8996ee0 bellard
1490 c896fe29 bellard
static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
1491 c896fe29 bellard
                              const TCGArg *args,
1492 c896fe29 bellard
                              unsigned int dead_iargs)
1493 c896fe29 bellard
{
1494 c896fe29 bellard
    TCGTemp *ts, *ots;
1495 c896fe29 bellard
    int reg;
1496 c896fe29 bellard
    const TCGArgConstraint *arg_ct;
1497 c896fe29 bellard
1498 c896fe29 bellard
    ots = &s->temps[args[0]];
1499 c896fe29 bellard
    ts = &s->temps[args[1]];
1500 c896fe29 bellard
    arg_ct = &def->args_ct[0];
1501 c896fe29 bellard
1502 e8996ee0 bellard
    /* XXX: always mark arg dead if IS_DEAD_IARG(0) */
1503 c896fe29 bellard
    if (ts->val_type == TEMP_VAL_REG) {
1504 c896fe29 bellard
        if (IS_DEAD_IARG(0) && !ts->fixed_reg && !ots->fixed_reg) {
1505 c896fe29 bellard
            /* the mov can be suppressed */
1506 c896fe29 bellard
            if (ots->val_type == TEMP_VAL_REG)
1507 c896fe29 bellard
                s->reg_to_temp[ots->reg] = -1;
1508 c896fe29 bellard
            reg = ts->reg;
1509 c896fe29 bellard
            s->reg_to_temp[reg] = -1;
1510 c896fe29 bellard
            ts->val_type = TEMP_VAL_DEAD;
1511 c896fe29 bellard
        } else {
1512 c896fe29 bellard
            if (ots->val_type == TEMP_VAL_REG) {
1513 c896fe29 bellard
                reg = ots->reg;
1514 c896fe29 bellard
            } else {
1515 c896fe29 bellard
                reg = tcg_reg_alloc(s, arg_ct->u.regs, s->reserved_regs);
1516 c896fe29 bellard
            }
1517 c896fe29 bellard
            if (ts->reg != reg) {
1518 c896fe29 bellard
                tcg_out_mov(s, reg, ts->reg);
1519 c896fe29 bellard
            }
1520 c896fe29 bellard
        }
1521 c896fe29 bellard
    } else if (ts->val_type == TEMP_VAL_MEM) {
1522 c896fe29 bellard
        if (ots->val_type == TEMP_VAL_REG) {
1523 c896fe29 bellard
            reg = ots->reg;
1524 c896fe29 bellard
        } else {
1525 c896fe29 bellard
            reg = tcg_reg_alloc(s, arg_ct->u.regs, s->reserved_regs);
1526 c896fe29 bellard
        }
1527 e4d5434c blueswir1
        tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
1528 c896fe29 bellard
    } else if (ts->val_type == TEMP_VAL_CONST) {
1529 e8996ee0 bellard
        if (ots->fixed_reg) {
1530 c896fe29 bellard
            reg = ots->reg;
1531 e8996ee0 bellard
            tcg_out_movi(s, ots->type, reg, ts->val);
1532 c896fe29 bellard
        } else {
1533 e8996ee0 bellard
            /* propagate constant */
1534 e8996ee0 bellard
            if (ots->val_type == TEMP_VAL_REG)
1535 e8996ee0 bellard
                s->reg_to_temp[ots->reg] = -1;
1536 e8996ee0 bellard
            ots->val_type = TEMP_VAL_CONST;
1537 e8996ee0 bellard
            ots->val = ts->val;
1538 e8996ee0 bellard
            return;
1539 c896fe29 bellard
        }
1540 c896fe29 bellard
    } else {
1541 c896fe29 bellard
        tcg_abort();
1542 c896fe29 bellard
    }
1543 c896fe29 bellard
    s->reg_to_temp[reg] = args[0];
1544 c896fe29 bellard
    ots->reg = reg;
1545 c896fe29 bellard
    ots->val_type = TEMP_VAL_REG;
1546 c896fe29 bellard
    ots->mem_coherent = 0;
1547 c896fe29 bellard
}
1548 c896fe29 bellard
1549 c896fe29 bellard
static void tcg_reg_alloc_op(TCGContext *s, 
1550 c896fe29 bellard
                             const TCGOpDef *def, int opc,
1551 c896fe29 bellard
                             const TCGArg *args,
1552 c896fe29 bellard
                             unsigned int dead_iargs)
1553 c896fe29 bellard
{
1554 c896fe29 bellard
    TCGRegSet allocated_regs;
1555 c896fe29 bellard
    int i, k, nb_iargs, nb_oargs, reg;
1556 c896fe29 bellard
    TCGArg arg;
1557 c896fe29 bellard
    const TCGArgConstraint *arg_ct;
1558 c896fe29 bellard
    TCGTemp *ts;
1559 c896fe29 bellard
    TCGArg new_args[TCG_MAX_OP_ARGS];
1560 c896fe29 bellard
    int const_args[TCG_MAX_OP_ARGS];
1561 c896fe29 bellard
1562 c896fe29 bellard
    nb_oargs = def->nb_oargs;
1563 c896fe29 bellard
    nb_iargs = def->nb_iargs;
1564 c896fe29 bellard
1565 c896fe29 bellard
    /* copy constants */
1566 c896fe29 bellard
    memcpy(new_args + nb_oargs + nb_iargs, 
1567 c896fe29 bellard
           args + nb_oargs + nb_iargs, 
1568 c896fe29 bellard
           sizeof(TCGArg) * def->nb_cargs);
1569 c896fe29 bellard
1570 c896fe29 bellard
    /* satisfy input constraints */ 
1571 c896fe29 bellard
    tcg_regset_set(allocated_regs, s->reserved_regs);
1572 c896fe29 bellard
    for(k = 0; k < nb_iargs; k++) {
1573 c896fe29 bellard
        i = def->sorted_args[nb_oargs + k];
1574 c896fe29 bellard
        arg = args[i];
1575 c896fe29 bellard
        arg_ct = &def->args_ct[i];
1576 c896fe29 bellard
        ts = &s->temps[arg];
1577 c896fe29 bellard
        if (ts->val_type == TEMP_VAL_MEM) {
1578 c896fe29 bellard
            reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1579 e4d5434c blueswir1
            tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
1580 c896fe29 bellard
            ts->val_type = TEMP_VAL_REG;
1581 c896fe29 bellard
            ts->reg = reg;
1582 c896fe29 bellard
            ts->mem_coherent = 1;
1583 c896fe29 bellard
            s->reg_to_temp[reg] = arg;
1584 c896fe29 bellard
        } else if (ts->val_type == TEMP_VAL_CONST) {
1585 c896fe29 bellard
            if (tcg_target_const_match(ts->val, arg_ct)) {
1586 c896fe29 bellard
                /* constant is OK for instruction */
1587 c896fe29 bellard
                const_args[i] = 1;
1588 c896fe29 bellard
                new_args[i] = ts->val;
1589 c896fe29 bellard
                goto iarg_end;
1590 c896fe29 bellard
            } else {
1591 e8996ee0 bellard
                /* need to move to a register */
1592 c896fe29 bellard
                reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1593 c896fe29 bellard
                tcg_out_movi(s, ts->type, reg, ts->val);
1594 e8996ee0 bellard
                ts->val_type = TEMP_VAL_REG;
1595 e8996ee0 bellard
                ts->reg = reg;
1596 e8996ee0 bellard
                ts->mem_coherent = 0;
1597 e8996ee0 bellard
                s->reg_to_temp[reg] = arg;
1598 c896fe29 bellard
            }
1599 c896fe29 bellard
        }
1600 c896fe29 bellard
        assert(ts->val_type == TEMP_VAL_REG);
1601 5ff9d6a4 bellard
        if (arg_ct->ct & TCG_CT_IALIAS) {
1602 5ff9d6a4 bellard
            if (ts->fixed_reg) {
1603 5ff9d6a4 bellard
                /* if fixed register, we must allocate a new register
1604 5ff9d6a4 bellard
                   if the alias is not the same register */
1605 5ff9d6a4 bellard
                if (arg != args[arg_ct->alias_index])
1606 5ff9d6a4 bellard
                    goto allocate_in_reg;
1607 5ff9d6a4 bellard
            } else {
1608 5ff9d6a4 bellard
                /* if the input is aliased to an output and if it is
1609 5ff9d6a4 bellard
                   not dead after the instruction, we must allocate
1610 5ff9d6a4 bellard
                   a new register and move it */
1611 5ff9d6a4 bellard
                if (!IS_DEAD_IARG(i - nb_oargs)) 
1612 5ff9d6a4 bellard
                    goto allocate_in_reg;
1613 5ff9d6a4 bellard
            }
1614 c896fe29 bellard
        }
1615 c896fe29 bellard
        reg = ts->reg;
1616 c896fe29 bellard
        if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
1617 c896fe29 bellard
            /* nothing to do : the constraint is satisfied */
1618 c896fe29 bellard
        } else {
1619 c896fe29 bellard
        allocate_in_reg:
1620 c896fe29 bellard
            /* allocate a new register matching the constraint 
1621 c896fe29 bellard
               and move the temporary register into it */
1622 c896fe29 bellard
            reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1623 c896fe29 bellard
            tcg_out_mov(s, reg, ts->reg);
1624 c896fe29 bellard
        }
1625 c896fe29 bellard
        new_args[i] = reg;
1626 c896fe29 bellard
        const_args[i] = 0;
1627 c896fe29 bellard
        tcg_regset_set_reg(allocated_regs, reg);
1628 c896fe29 bellard
    iarg_end: ;
1629 c896fe29 bellard
    }
1630 c896fe29 bellard
    
1631 e8996ee0 bellard
    if (def->flags & TCG_OPF_BB_END) {
1632 e8996ee0 bellard
        tcg_reg_alloc_bb_end(s, allocated_regs);
1633 e8996ee0 bellard
    } else {
1634 e8996ee0 bellard
        /* mark dead temporaries and free the associated registers */
1635 e8996ee0 bellard
        for(i = 0; i < nb_iargs; i++) {
1636 e8996ee0 bellard
            arg = args[nb_oargs + i];
1637 e8996ee0 bellard
            if (IS_DEAD_IARG(i)) {
1638 e8996ee0 bellard
                ts = &s->temps[arg];
1639 e8996ee0 bellard
                if (!ts->fixed_reg) {
1640 e8996ee0 bellard
                    if (ts->val_type == TEMP_VAL_REG)
1641 e8996ee0 bellard
                        s->reg_to_temp[ts->reg] = -1;
1642 e8996ee0 bellard
                    ts->val_type = TEMP_VAL_DEAD;
1643 e8996ee0 bellard
                }
1644 c896fe29 bellard
            }
1645 c896fe29 bellard
        }
1646 e8996ee0 bellard
        
1647 e8996ee0 bellard
        if (def->flags & TCG_OPF_CALL_CLOBBER) {
1648 e8996ee0 bellard
            /* XXX: permit generic clobber register list ? */ 
1649 e8996ee0 bellard
            for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
1650 e8996ee0 bellard
                if (tcg_regset_test_reg(tcg_target_call_clobber_regs, reg)) {
1651 e8996ee0 bellard
                    tcg_reg_free(s, reg);
1652 e8996ee0 bellard
                }
1653 c896fe29 bellard
            }
1654 e8996ee0 bellard
            /* XXX: for load/store we could do that only for the slow path
1655 e8996ee0 bellard
               (i.e. when a memory callback is called) */
1656 e8996ee0 bellard
            
1657 e8996ee0 bellard
            /* store globals and free associated registers (we assume the insn
1658 e8996ee0 bellard
               can modify any global. */
1659 e8996ee0 bellard
            save_globals(s, allocated_regs);
1660 c896fe29 bellard
        }
1661 e8996ee0 bellard
        
1662 e8996ee0 bellard
        /* satisfy the output constraints */
1663 e8996ee0 bellard
        tcg_regset_set(allocated_regs, s->reserved_regs);
1664 e8996ee0 bellard
        for(k = 0; k < nb_oargs; k++) {
1665 e8996ee0 bellard
            i = def->sorted_args[k];
1666 e8996ee0 bellard
            arg = args[i];
1667 e8996ee0 bellard
            arg_ct = &def->args_ct[i];
1668 e8996ee0 bellard
            ts = &s->temps[arg];
1669 e8996ee0 bellard
            if (arg_ct->ct & TCG_CT_ALIAS) {
1670 e8996ee0 bellard
                reg = new_args[arg_ct->alias_index];
1671 e8996ee0 bellard
            } else {
1672 e8996ee0 bellard
                /* if fixed register, we try to use it */
1673 e8996ee0 bellard
                reg = ts->reg;
1674 e8996ee0 bellard
                if (ts->fixed_reg &&
1675 e8996ee0 bellard
                    tcg_regset_test_reg(arg_ct->u.regs, reg)) {
1676 e8996ee0 bellard
                    goto oarg_end;
1677 e8996ee0 bellard
                }
1678 e8996ee0 bellard
                reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1679 c896fe29 bellard
            }
1680 e8996ee0 bellard
            tcg_regset_set_reg(allocated_regs, reg);
1681 e8996ee0 bellard
            /* if a fixed register is used, then a move will be done afterwards */
1682 e8996ee0 bellard
            if (!ts->fixed_reg) {
1683 e8996ee0 bellard
                if (ts->val_type == TEMP_VAL_REG)
1684 e8996ee0 bellard
                    s->reg_to_temp[ts->reg] = -1;
1685 e8996ee0 bellard
                ts->val_type = TEMP_VAL_REG;
1686 e8996ee0 bellard
                ts->reg = reg;
1687 e8996ee0 bellard
                /* temp value is modified, so the value kept in memory is
1688 e8996ee0 bellard
                   potentially not the same */
1689 e8996ee0 bellard
                ts->mem_coherent = 0; 
1690 e8996ee0 bellard
                s->reg_to_temp[reg] = arg;
1691 e8996ee0 bellard
            }
1692 e8996ee0 bellard
        oarg_end:
1693 e8996ee0 bellard
            new_args[i] = reg;
1694 c896fe29 bellard
        }
1695 c896fe29 bellard
    }
1696 c896fe29 bellard
1697 c896fe29 bellard
    /* emit instruction */
1698 c896fe29 bellard
    tcg_out_op(s, opc, new_args, const_args);
1699 c896fe29 bellard
    
1700 c896fe29 bellard
    /* move the outputs in the correct register if needed */
1701 c896fe29 bellard
    for(i = 0; i < nb_oargs; i++) {
1702 c896fe29 bellard
        ts = &s->temps[args[i]];
1703 c896fe29 bellard
        reg = new_args[i];
1704 c896fe29 bellard
        if (ts->fixed_reg && ts->reg != reg) {
1705 c896fe29 bellard
            tcg_out_mov(s, ts->reg, reg);
1706 c896fe29 bellard
        }
1707 c896fe29 bellard
    }
1708 c896fe29 bellard
}
1709 c896fe29 bellard
1710 b03cce8e bellard
#ifdef TCG_TARGET_STACK_GROWSUP
1711 b03cce8e bellard
#define STACK_DIR(x) (-(x))
1712 b03cce8e bellard
#else
1713 b03cce8e bellard
#define STACK_DIR(x) (x)
1714 b03cce8e bellard
#endif
1715 b03cce8e bellard
1716 c896fe29 bellard
static int tcg_reg_alloc_call(TCGContext *s, const TCGOpDef *def,
1717 c896fe29 bellard
                              int opc, const TCGArg *args,
1718 c896fe29 bellard
                              unsigned int dead_iargs)
1719 c896fe29 bellard
{
1720 c896fe29 bellard
    int nb_iargs, nb_oargs, flags, nb_regs, i, reg, nb_params;
1721 c896fe29 bellard
    TCGArg arg, func_arg;
1722 c896fe29 bellard
    TCGTemp *ts;
1723 f54b3f92 aurel32
    tcg_target_long stack_offset, call_stack_size, func_addr;
1724 b03cce8e bellard
    int const_func_arg, allocate_args;
1725 c896fe29 bellard
    TCGRegSet allocated_regs;
1726 c896fe29 bellard
    const TCGArgConstraint *arg_ct;
1727 c896fe29 bellard
1728 c896fe29 bellard
    arg = *args++;
1729 c896fe29 bellard
1730 c896fe29 bellard
    nb_oargs = arg >> 16;
1731 c896fe29 bellard
    nb_iargs = arg & 0xffff;
1732 c896fe29 bellard
    nb_params = nb_iargs - 1;
1733 c896fe29 bellard
1734 c896fe29 bellard
    flags = args[nb_oargs + nb_iargs];
1735 c896fe29 bellard
1736 c896fe29 bellard
    nb_regs = tcg_target_get_call_iarg_regs_count(flags);
1737 c896fe29 bellard
    if (nb_regs > nb_params)
1738 c896fe29 bellard
        nb_regs = nb_params;
1739 c896fe29 bellard
1740 c896fe29 bellard
    /* assign stack slots first */
1741 c896fe29 bellard
    /* XXX: preallocate call stack */
1742 c896fe29 bellard
    call_stack_size = (nb_params - nb_regs) * sizeof(tcg_target_long);
1743 c896fe29 bellard
    call_stack_size = (call_stack_size + TCG_TARGET_STACK_ALIGN - 1) & 
1744 c896fe29 bellard
        ~(TCG_TARGET_STACK_ALIGN - 1);
1745 b03cce8e bellard
    allocate_args = (call_stack_size > TCG_STATIC_CALL_ARGS_SIZE);
1746 b03cce8e bellard
    if (allocate_args) {
1747 b03cce8e bellard
        tcg_out_addi(s, TCG_REG_CALL_STACK, -STACK_DIR(call_stack_size));
1748 b03cce8e bellard
    }
1749 39cf05d3 bellard
1750 39cf05d3 bellard
    stack_offset = TCG_TARGET_CALL_STACK_OFFSET;
1751 c896fe29 bellard
    for(i = nb_regs; i < nb_params; i++) {
1752 c896fe29 bellard
        arg = args[nb_oargs + i];
1753 39cf05d3 bellard
#ifdef TCG_TARGET_STACK_GROWSUP
1754 39cf05d3 bellard
        stack_offset -= sizeof(tcg_target_long);
1755 39cf05d3 bellard
#endif
1756 39cf05d3 bellard
        if (arg != TCG_CALL_DUMMY_ARG) {
1757 39cf05d3 bellard
            ts = &s->temps[arg];
1758 39cf05d3 bellard
            if (ts->val_type == TEMP_VAL_REG) {
1759 39cf05d3 bellard
                tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset);
1760 39cf05d3 bellard
            } else if (ts->val_type == TEMP_VAL_MEM) {
1761 39cf05d3 bellard
                reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type], 
1762 39cf05d3 bellard
                                    s->reserved_regs);
1763 39cf05d3 bellard
                /* XXX: not correct if reading values from the stack */
1764 39cf05d3 bellard
                tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
1765 39cf05d3 bellard
                tcg_out_st(s, ts->type, reg, TCG_REG_CALL_STACK, stack_offset);
1766 39cf05d3 bellard
            } else if (ts->val_type == TEMP_VAL_CONST) {
1767 39cf05d3 bellard
                reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type], 
1768 39cf05d3 bellard
                                    s->reserved_regs);
1769 39cf05d3 bellard
                /* XXX: sign extend may be needed on some targets */
1770 39cf05d3 bellard
                tcg_out_movi(s, ts->type, reg, ts->val);
1771 39cf05d3 bellard
                tcg_out_st(s, ts->type, reg, TCG_REG_CALL_STACK, stack_offset);
1772 39cf05d3 bellard
            } else {
1773 39cf05d3 bellard
                tcg_abort();
1774 39cf05d3 bellard
            }
1775 c896fe29 bellard
        }
1776 39cf05d3 bellard
#ifndef TCG_TARGET_STACK_GROWSUP
1777 39cf05d3 bellard
        stack_offset += sizeof(tcg_target_long);
1778 39cf05d3 bellard
#endif
1779 c896fe29 bellard
    }
1780 c896fe29 bellard
    
1781 c896fe29 bellard
    /* assign input registers */
1782 c896fe29 bellard
    tcg_regset_set(allocated_regs, s->reserved_regs);
1783 c896fe29 bellard
    for(i = 0; i < nb_regs; i++) {
1784 c896fe29 bellard
        arg = args[nb_oargs + i];
1785 39cf05d3 bellard
        if (arg != TCG_CALL_DUMMY_ARG) {
1786 39cf05d3 bellard
            ts = &s->temps[arg];
1787 39cf05d3 bellard
            reg = tcg_target_call_iarg_regs[i];
1788 39cf05d3 bellard
            tcg_reg_free(s, reg);
1789 39cf05d3 bellard
            if (ts->val_type == TEMP_VAL_REG) {
1790 39cf05d3 bellard
                if (ts->reg != reg) {
1791 39cf05d3 bellard
                    tcg_out_mov(s, reg, ts->reg);
1792 39cf05d3 bellard
                }
1793 39cf05d3 bellard
            } else if (ts->val_type == TEMP_VAL_MEM) {
1794 39cf05d3 bellard
                tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
1795 39cf05d3 bellard
            } else if (ts->val_type == TEMP_VAL_CONST) {
1796 39cf05d3 bellard
                /* XXX: sign extend ? */
1797 39cf05d3 bellard
                tcg_out_movi(s, ts->type, reg, ts->val);
1798 39cf05d3 bellard
            } else {
1799 39cf05d3 bellard
                tcg_abort();
1800 c896fe29 bellard
            }
1801 39cf05d3 bellard
            tcg_regset_set_reg(allocated_regs, reg);
1802 c896fe29 bellard
        }
1803 c896fe29 bellard
    }
1804 c896fe29 bellard
    
1805 c896fe29 bellard
    /* assign function address */
1806 c896fe29 bellard
    func_arg = args[nb_oargs + nb_iargs - 1];
1807 c896fe29 bellard
    arg_ct = &def->args_ct[0];
1808 c896fe29 bellard
    ts = &s->temps[func_arg];
1809 f54b3f92 aurel32
    func_addr = ts->val;
1810 c896fe29 bellard
    const_func_arg = 0;
1811 c896fe29 bellard
    if (ts->val_type == TEMP_VAL_MEM) {
1812 c896fe29 bellard
        reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1813 e4d5434c blueswir1
        tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
1814 c896fe29 bellard
        func_arg = reg;
1815 e8996ee0 bellard
        tcg_regset_set_reg(allocated_regs, reg);
1816 c896fe29 bellard
    } else if (ts->val_type == TEMP_VAL_REG) {
1817 c896fe29 bellard
        reg = ts->reg;
1818 c896fe29 bellard
        if (!tcg_regset_test_reg(arg_ct->u.regs, reg)) {
1819 c896fe29 bellard
            reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1820 c896fe29 bellard
            tcg_out_mov(s, reg, ts->reg);
1821 c896fe29 bellard
        }
1822 c896fe29 bellard
        func_arg = reg;
1823 e8996ee0 bellard
        tcg_regset_set_reg(allocated_regs, reg);
1824 c896fe29 bellard
    } else if (ts->val_type == TEMP_VAL_CONST) {
1825 f54b3f92 aurel32
        if (tcg_target_const_match(func_addr, arg_ct)) {
1826 c896fe29 bellard
            const_func_arg = 1;
1827 f54b3f92 aurel32
            func_arg = func_addr;
1828 c896fe29 bellard
        } else {
1829 c896fe29 bellard
            reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1830 f54b3f92 aurel32
            tcg_out_movi(s, ts->type, reg, func_addr);
1831 c896fe29 bellard
            func_arg = reg;
1832 e8996ee0 bellard
            tcg_regset_set_reg(allocated_regs, reg);
1833 c896fe29 bellard
        }
1834 c896fe29 bellard
    } else {
1835 c896fe29 bellard
        tcg_abort();
1836 c896fe29 bellard
    }
1837 e8996ee0 bellard
        
1838 c896fe29 bellard
    
1839 c896fe29 bellard
    /* mark dead temporaries and free the associated registers */
1840 c6e113f5 bellard
    for(i = 0; i < nb_iargs; i++) {
1841 c896fe29 bellard
        arg = args[nb_oargs + i];
1842 c896fe29 bellard
        if (IS_DEAD_IARG(i)) {
1843 c896fe29 bellard
            ts = &s->temps[arg];
1844 e8996ee0 bellard
            if (!ts->fixed_reg) {
1845 c896fe29 bellard
                if (ts->val_type == TEMP_VAL_REG)
1846 c896fe29 bellard
                    s->reg_to_temp[ts->reg] = -1;
1847 c896fe29 bellard
                ts->val_type = TEMP_VAL_DEAD;
1848 c896fe29 bellard
            }
1849 c896fe29 bellard
        }
1850 c896fe29 bellard
    }
1851 c896fe29 bellard
    
1852 c896fe29 bellard
    /* clobber call registers */
1853 c896fe29 bellard
    for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
1854 c896fe29 bellard
        if (tcg_regset_test_reg(tcg_target_call_clobber_regs, reg)) {
1855 c896fe29 bellard
            tcg_reg_free(s, reg);
1856 c896fe29 bellard
        }
1857 c896fe29 bellard
    }
1858 c896fe29 bellard
    
1859 c896fe29 bellard
    /* store globals and free associated registers (we assume the call
1860 c896fe29 bellard
       can modify any global. */
1861 b9c18f56 aurel32
    if (!(flags & TCG_CALL_CONST)) {
1862 b9c18f56 aurel32
        save_globals(s, allocated_regs);
1863 b9c18f56 aurel32
    }
1864 c896fe29 bellard
1865 c896fe29 bellard
    tcg_out_op(s, opc, &func_arg, &const_func_arg);
1866 c896fe29 bellard
    
1867 b03cce8e bellard
    if (allocate_args) {
1868 b03cce8e bellard
        tcg_out_addi(s, TCG_REG_CALL_STACK, STACK_DIR(call_stack_size));
1869 b03cce8e bellard
    }
1870 c896fe29 bellard
1871 c896fe29 bellard
    /* assign output registers and emit moves if needed */
1872 c896fe29 bellard
    for(i = 0; i < nb_oargs; i++) {
1873 c896fe29 bellard
        arg = args[i];
1874 c896fe29 bellard
        ts = &s->temps[arg];
1875 c896fe29 bellard
        reg = tcg_target_call_oarg_regs[i];
1876 e8996ee0 bellard
        assert(s->reg_to_temp[reg] == -1);
1877 c896fe29 bellard
        if (ts->fixed_reg) {
1878 c896fe29 bellard
            if (ts->reg != reg) {
1879 c896fe29 bellard
                tcg_out_mov(s, ts->reg, reg);
1880 c896fe29 bellard
            }
1881 c896fe29 bellard
        } else {
1882 c896fe29 bellard
            if (ts->val_type == TEMP_VAL_REG)
1883 c896fe29 bellard
                s->reg_to_temp[ts->reg] = -1;
1884 c896fe29 bellard
            ts->val_type = TEMP_VAL_REG;
1885 c896fe29 bellard
            ts->reg = reg;
1886 c896fe29 bellard
            ts->mem_coherent = 0; 
1887 c896fe29 bellard
            s->reg_to_temp[reg] = arg;
1888 c896fe29 bellard
        }
1889 c896fe29 bellard
    }
1890 c896fe29 bellard
    
1891 c896fe29 bellard
    return nb_iargs + nb_oargs + def->nb_cargs + 1;
1892 c896fe29 bellard
}
1893 c896fe29 bellard
1894 c896fe29 bellard
#ifdef CONFIG_PROFILER
1895 c896fe29 bellard
1896 54604f74 aurel32
static int64_t tcg_table_op_count[NB_OPS];
1897 c896fe29 bellard
1898 871e6c35 Blue Swirl
static void dump_op_count(void)
1899 c896fe29 bellard
{
1900 c896fe29 bellard
    int i;
1901 c896fe29 bellard
    FILE *f;
1902 54604f74 aurel32
    f = fopen("/tmp/op.log", "w");
1903 c896fe29 bellard
    for(i = INDEX_op_end; i < NB_OPS; i++) {
1904 54604f74 aurel32
        fprintf(f, "%s %" PRId64 "\n", tcg_op_defs[i].name, tcg_table_op_count[i]);
1905 c896fe29 bellard
    }
1906 c896fe29 bellard
    fclose(f);
1907 c896fe29 bellard
}
1908 c896fe29 bellard
#endif
1909 c896fe29 bellard
1910 c896fe29 bellard
1911 c896fe29 bellard
static inline int tcg_gen_code_common(TCGContext *s, uint8_t *gen_code_buf,
1912 2ba1eeb6 pbrook
                                      long search_pc)
1913 c896fe29 bellard
{
1914 b314f270 bellard
    int opc, op_index;
1915 c896fe29 bellard
    const TCGOpDef *def;
1916 c896fe29 bellard
    unsigned int dead_iargs;
1917 c896fe29 bellard
    const TCGArg *args;
1918 c896fe29 bellard
1919 c896fe29 bellard
#ifdef DEBUG_DISAS
1920 8fec2b8c aliguori
    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
1921 93fcfe39 aliguori
        qemu_log("OP:\n");
1922 c896fe29 bellard
        tcg_dump_ops(s, logfile);
1923 93fcfe39 aliguori
        qemu_log("\n");
1924 c896fe29 bellard
    }
1925 c896fe29 bellard
#endif
1926 c896fe29 bellard
1927 a23a9ec6 bellard
#ifdef CONFIG_PROFILER
1928 a23a9ec6 bellard
    s->la_time -= profile_getclock();
1929 a23a9ec6 bellard
#endif
1930 c896fe29 bellard
    tcg_liveness_analysis(s);
1931 a23a9ec6 bellard
#ifdef CONFIG_PROFILER
1932 a23a9ec6 bellard
    s->la_time += profile_getclock();
1933 a23a9ec6 bellard
#endif
1934 c896fe29 bellard
1935 c896fe29 bellard
#ifdef DEBUG_DISAS
1936 8fec2b8c aliguori
    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) {
1937 6a957025 Aurelien Jarno
        qemu_log("OP after liveness analysis:\n");
1938 c896fe29 bellard
        tcg_dump_ops(s, logfile);
1939 93fcfe39 aliguori
        qemu_log("\n");
1940 c896fe29 bellard
    }
1941 c896fe29 bellard
#endif
1942 c896fe29 bellard
1943 c896fe29 bellard
    tcg_reg_alloc_start(s);
1944 c896fe29 bellard
1945 c896fe29 bellard
    s->code_buf = gen_code_buf;
1946 c896fe29 bellard
    s->code_ptr = gen_code_buf;
1947 c896fe29 bellard
1948 c896fe29 bellard
    args = gen_opparam_buf;
1949 c896fe29 bellard
    op_index = 0;
1950 b3db8758 blueswir1
1951 c896fe29 bellard
    for(;;) {
1952 c896fe29 bellard
        opc = gen_opc_buf[op_index];
1953 c896fe29 bellard
#ifdef CONFIG_PROFILER
1954 54604f74 aurel32
        tcg_table_op_count[opc]++;
1955 c896fe29 bellard
#endif
1956 c896fe29 bellard
        def = &tcg_op_defs[opc];
1957 c896fe29 bellard
#if 0
1958 c896fe29 bellard
        printf("%s: %d %d %d\n", def->name,
1959 c896fe29 bellard
               def->nb_oargs, def->nb_iargs, def->nb_cargs);
1960 c896fe29 bellard
        //        dump_regs(s);
1961 c896fe29 bellard
#endif
1962 c896fe29 bellard
        switch(opc) {
1963 c896fe29 bellard
        case INDEX_op_mov_i32:
1964 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 64
1965 c896fe29 bellard
        case INDEX_op_mov_i64:
1966 c896fe29 bellard
#endif
1967 c896fe29 bellard
            dead_iargs = s->op_dead_iargs[op_index];
1968 c896fe29 bellard
            tcg_reg_alloc_mov(s, def, args, dead_iargs);
1969 c896fe29 bellard
            break;
1970 e8996ee0 bellard
        case INDEX_op_movi_i32:
1971 e8996ee0 bellard
#if TCG_TARGET_REG_BITS == 64
1972 e8996ee0 bellard
        case INDEX_op_movi_i64:
1973 e8996ee0 bellard
#endif
1974 e8996ee0 bellard
            tcg_reg_alloc_movi(s, args);
1975 e8996ee0 bellard
            break;
1976 7e4597d7 bellard
        case INDEX_op_debug_insn_start:
1977 7e4597d7 bellard
            /* debug instruction */
1978 7e4597d7 bellard
            break;
1979 c896fe29 bellard
        case INDEX_op_nop:
1980 c896fe29 bellard
        case INDEX_op_nop1:
1981 c896fe29 bellard
        case INDEX_op_nop2:
1982 c896fe29 bellard
        case INDEX_op_nop3:
1983 c896fe29 bellard
            break;
1984 c896fe29 bellard
        case INDEX_op_nopn:
1985 c896fe29 bellard
            args += args[0];
1986 c896fe29 bellard
            goto next;
1987 5ff9d6a4 bellard
        case INDEX_op_discard:
1988 5ff9d6a4 bellard
            {
1989 5ff9d6a4 bellard
                TCGTemp *ts;
1990 5ff9d6a4 bellard
                ts = &s->temps[args[0]];
1991 5ff9d6a4 bellard
                /* mark the temporary as dead */
1992 e8996ee0 bellard
                if (!ts->fixed_reg) {
1993 5ff9d6a4 bellard
                    if (ts->val_type == TEMP_VAL_REG)
1994 5ff9d6a4 bellard
                        s->reg_to_temp[ts->reg] = -1;
1995 5ff9d6a4 bellard
                    ts->val_type = TEMP_VAL_DEAD;
1996 5ff9d6a4 bellard
                }
1997 5ff9d6a4 bellard
            }
1998 5ff9d6a4 bellard
            break;
1999 c896fe29 bellard
        case INDEX_op_set_label:
2000 e8996ee0 bellard
            tcg_reg_alloc_bb_end(s, s->reserved_regs);
2001 c896fe29 bellard
            tcg_out_label(s, args[0], (long)s->code_ptr);
2002 c896fe29 bellard
            break;
2003 c896fe29 bellard
        case INDEX_op_call:
2004 c896fe29 bellard
            dead_iargs = s->op_dead_iargs[op_index];
2005 c896fe29 bellard
            args += tcg_reg_alloc_call(s, def, opc, args, dead_iargs);
2006 c896fe29 bellard
            goto next;
2007 c896fe29 bellard
        case INDEX_op_end:
2008 c896fe29 bellard
            goto the_end;
2009 c896fe29 bellard
        default:
2010 c896fe29 bellard
            /* Note: in order to speed up the code, it would be much
2011 c896fe29 bellard
               faster to have specialized register allocator functions for
2012 c896fe29 bellard
               some common argument patterns */
2013 c896fe29 bellard
            dead_iargs = s->op_dead_iargs[op_index];
2014 c896fe29 bellard
            tcg_reg_alloc_op(s, def, opc, args, dead_iargs);
2015 c896fe29 bellard
            break;
2016 c896fe29 bellard
        }
2017 c896fe29 bellard
        args += def->nb_args;
2018 8df1ca4b ths
    next:
2019 2ba1eeb6 pbrook
        if (search_pc >= 0 && search_pc < s->code_ptr - gen_code_buf) {
2020 b314f270 bellard
            return op_index;
2021 c896fe29 bellard
        }
2022 c896fe29 bellard
        op_index++;
2023 c896fe29 bellard
#ifndef NDEBUG
2024 c896fe29 bellard
        check_regs(s);
2025 c896fe29 bellard
#endif
2026 c896fe29 bellard
    }
2027 c896fe29 bellard
 the_end:
2028 c896fe29 bellard
    return -1;
2029 c896fe29 bellard
}
2030 c896fe29 bellard
2031 54604f74 aurel32
int tcg_gen_code(TCGContext *s, uint8_t *gen_code_buf)
2032 c896fe29 bellard
{
2033 c896fe29 bellard
#ifdef CONFIG_PROFILER
2034 c896fe29 bellard
    {
2035 c896fe29 bellard
        int n;
2036 c896fe29 bellard
        n = (gen_opc_ptr - gen_opc_buf);
2037 a23a9ec6 bellard
        s->op_count += n;
2038 a23a9ec6 bellard
        if (n > s->op_count_max)
2039 a23a9ec6 bellard
            s->op_count_max = n;
2040 a23a9ec6 bellard
2041 a23a9ec6 bellard
        s->temp_count += s->nb_temps;
2042 a23a9ec6 bellard
        if (s->nb_temps > s->temp_count_max)
2043 a23a9ec6 bellard
            s->temp_count_max = s->nb_temps;
2044 c896fe29 bellard
    }
2045 c896fe29 bellard
#endif
2046 c896fe29 bellard
2047 2ba1eeb6 pbrook
    tcg_gen_code_common(s, gen_code_buf, -1);
2048 c896fe29 bellard
2049 c896fe29 bellard
    /* flush instruction cache */
2050 c896fe29 bellard
    flush_icache_range((unsigned long)gen_code_buf, 
2051 c896fe29 bellard
                       (unsigned long)s->code_ptr);
2052 c896fe29 bellard
    return s->code_ptr -  gen_code_buf;
2053 c896fe29 bellard
}
2054 c896fe29 bellard
2055 2ba1eeb6 pbrook
/* Return the index of the micro operation such as the pc after is <
2056 623e265c pbrook
   offset bytes from the start of the TB.  The contents of gen_code_buf must
2057 623e265c pbrook
   not be changed, though writing the same values is ok.
2058 623e265c pbrook
   Return -1 if not found. */
2059 54604f74 aurel32
int tcg_gen_code_search_pc(TCGContext *s, uint8_t *gen_code_buf, long offset)
2060 c896fe29 bellard
{
2061 623e265c pbrook
    return tcg_gen_code_common(s, gen_code_buf, offset);
2062 c896fe29 bellard
}
2063 a23a9ec6 bellard
2064 a23a9ec6 bellard
#ifdef CONFIG_PROFILER
2065 a23a9ec6 bellard
void tcg_dump_info(FILE *f,
2066 a23a9ec6 bellard
                   int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
2067 a23a9ec6 bellard
{
2068 a23a9ec6 bellard
    TCGContext *s = &tcg_ctx;
2069 a23a9ec6 bellard
    int64_t tot;
2070 a23a9ec6 bellard
2071 a23a9ec6 bellard
    tot = s->interm_time + s->code_time;
2072 a23a9ec6 bellard
    cpu_fprintf(f, "JIT cycles          %" PRId64 " (%0.3f s at 2.4 GHz)\n",
2073 a23a9ec6 bellard
                tot, tot / 2.4e9);
2074 a23a9ec6 bellard
    cpu_fprintf(f, "translated TBs      %" PRId64 " (aborted=%" PRId64 " %0.1f%%)\n", 
2075 a23a9ec6 bellard
                s->tb_count, 
2076 a23a9ec6 bellard
                s->tb_count1 - s->tb_count,
2077 a23a9ec6 bellard
                s->tb_count1 ? (double)(s->tb_count1 - s->tb_count) / s->tb_count1 * 100.0 : 0);
2078 a23a9ec6 bellard
    cpu_fprintf(f, "avg ops/TB          %0.1f max=%d\n", 
2079 a23a9ec6 bellard
                s->tb_count ? (double)s->op_count / s->tb_count : 0, s->op_count_max);
2080 a23a9ec6 bellard
    cpu_fprintf(f, "deleted ops/TB      %0.2f\n",
2081 a23a9ec6 bellard
                s->tb_count ? 
2082 a23a9ec6 bellard
                (double)s->del_op_count / s->tb_count : 0);
2083 a23a9ec6 bellard
    cpu_fprintf(f, "avg temps/TB        %0.2f max=%d\n",
2084 a23a9ec6 bellard
                s->tb_count ? 
2085 a23a9ec6 bellard
                (double)s->temp_count / s->tb_count : 0,
2086 a23a9ec6 bellard
                s->temp_count_max);
2087 a23a9ec6 bellard
    
2088 a23a9ec6 bellard
    cpu_fprintf(f, "cycles/op           %0.1f\n", 
2089 a23a9ec6 bellard
                s->op_count ? (double)tot / s->op_count : 0);
2090 a23a9ec6 bellard
    cpu_fprintf(f, "cycles/in byte      %0.1f\n", 
2091 a23a9ec6 bellard
                s->code_in_len ? (double)tot / s->code_in_len : 0);
2092 a23a9ec6 bellard
    cpu_fprintf(f, "cycles/out byte     %0.1f\n", 
2093 a23a9ec6 bellard
                s->code_out_len ? (double)tot / s->code_out_len : 0);
2094 a23a9ec6 bellard
    if (tot == 0)
2095 a23a9ec6 bellard
        tot = 1;
2096 a23a9ec6 bellard
    cpu_fprintf(f, "  gen_interm time   %0.1f%%\n", 
2097 a23a9ec6 bellard
                (double)s->interm_time / tot * 100.0);
2098 a23a9ec6 bellard
    cpu_fprintf(f, "  gen_code time     %0.1f%%\n", 
2099 a23a9ec6 bellard
                (double)s->code_time / tot * 100.0);
2100 a23a9ec6 bellard
    cpu_fprintf(f, "liveness/code time  %0.1f%%\n", 
2101 a23a9ec6 bellard
                (double)s->la_time / (s->code_time ? s->code_time : 1) * 100.0);
2102 a23a9ec6 bellard
    cpu_fprintf(f, "cpu_restore count   %" PRId64 "\n",
2103 a23a9ec6 bellard
                s->restore_count);
2104 a23a9ec6 bellard
    cpu_fprintf(f, "  avg cycles        %0.1f\n",
2105 a23a9ec6 bellard
                s->restore_count ? (double)s->restore_time / s->restore_count : 0);
2106 871e6c35 Blue Swirl
2107 871e6c35 Blue Swirl
    dump_op_count();
2108 a23a9ec6 bellard
}
2109 a23a9ec6 bellard
#else
2110 24bf7b3a bellard
void tcg_dump_info(FILE *f,
2111 a23a9ec6 bellard
                   int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
2112 a23a9ec6 bellard
{
2113 24bf7b3a bellard
    cpu_fprintf(f, "[TCG profiler not compiled]\n");
2114 a23a9ec6 bellard
}
2115 a23a9ec6 bellard
#endif