Revision 4e273869
| b/target-xtensa/helper.h | ||
|---|---|---|
| 49 | 49 |
DEF_HELPER_3(itof, f32, env, i32, i32) |
| 50 | 50 |
DEF_HELPER_3(uitof, f32, env, i32, i32) |
| 51 | 51 |
|
| 52 |
DEF_HELPER_4(un_s, void, env, i32, f32, f32) |
|
| 53 |
DEF_HELPER_4(oeq_s, void, env, i32, f32, f32) |
|
| 54 |
DEF_HELPER_4(ueq_s, void, env, i32, f32, f32) |
|
| 55 |
DEF_HELPER_4(olt_s, void, env, i32, f32, f32) |
|
| 56 |
DEF_HELPER_4(ult_s, void, env, i32, f32, f32) |
|
| 57 |
DEF_HELPER_4(ole_s, void, env, i32, f32, f32) |
|
| 58 |
DEF_HELPER_4(ule_s, void, env, i32, f32, f32) |
|
| 59 |
|
|
| 52 | 60 |
#include "def-helper.h" |
| b/target-xtensa/op_helper.c | ||
|---|---|---|
| 858 | 858 |
return float32_scalbn(uint32_to_float32(v, &env->fp_status), |
| 859 | 859 |
(int32_t)scale, &env->fp_status); |
| 860 | 860 |
} |
| 861 |
|
|
| 862 |
static inline void set_br(CPUXtensaState *env, bool v, uint32_t br) |
|
| 863 |
{
|
|
| 864 |
if (v) {
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|
| 865 |
env->sregs[BR] |= br; |
|
| 866 |
} else {
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|
| 867 |
env->sregs[BR] &= ~br; |
|
| 868 |
} |
|
| 869 |
} |
|
| 870 |
|
|
| 871 |
void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) |
|
| 872 |
{
|
|
| 873 |
set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br); |
|
| 874 |
} |
|
| 875 |
|
|
| 876 |
void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) |
|
| 877 |
{
|
|
| 878 |
set_br(env, float32_eq_quiet(a, b, &env->fp_status), br); |
|
| 879 |
} |
|
| 880 |
|
|
| 881 |
void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) |
|
| 882 |
{
|
|
| 883 |
int v = float32_compare_quiet(a, b, &env->fp_status); |
|
| 884 |
set_br(env, v == float_relation_equal || v == float_relation_unordered, br); |
|
| 885 |
} |
|
| 886 |
|
|
| 887 |
void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) |
|
| 888 |
{
|
|
| 889 |
set_br(env, float32_lt_quiet(a, b, &env->fp_status), br); |
|
| 890 |
} |
|
| 891 |
|
|
| 892 |
void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) |
|
| 893 |
{
|
|
| 894 |
int v = float32_compare_quiet(a, b, &env->fp_status); |
|
| 895 |
set_br(env, v == float_relation_less || v == float_relation_unordered, br); |
|
| 896 |
} |
|
| 897 |
|
|
| 898 |
void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) |
|
| 899 |
{
|
|
| 900 |
set_br(env, float32_le_quiet(a, b, &env->fp_status), br); |
|
| 901 |
} |
|
| 902 |
|
|
| 903 |
void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) |
|
| 904 |
{
|
|
| 905 |
int v = float32_compare_quiet(a, b, &env->fp_status); |
|
| 906 |
set_br(env, v != float_relation_greater, br); |
|
| 907 |
} |
|
| b/target-xtensa/translate.c | ||
|---|---|---|
| 2019 | 2019 |
|
| 2020 | 2020 |
case 11: /*FP1*/ |
| 2021 | 2021 |
HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); |
| 2022 |
TBD(); |
|
| 2022 |
|
|
| 2023 |
#define gen_compare(rel, br, a, b) \ |
|
| 2024 |
do { \
|
|
| 2025 |
TCGv_i32 bit = tcg_const_i32(1 << br); \ |
|
| 2026 |
\ |
|
| 2027 |
gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \ |
|
| 2028 |
tcg_temp_free(bit); \ |
|
| 2029 |
} while (0) |
|
| 2030 |
|
|
| 2031 |
switch (OP2) {
|
|
| 2032 |
case 1: /*UN.Sf*/ |
|
| 2033 |
gen_compare(un_s, RRR_R, RRR_S, RRR_T); |
|
| 2034 |
break; |
|
| 2035 |
|
|
| 2036 |
case 2: /*OEQ.Sf*/ |
|
| 2037 |
gen_compare(oeq_s, RRR_R, RRR_S, RRR_T); |
|
| 2038 |
break; |
|
| 2039 |
|
|
| 2040 |
case 3: /*UEQ.Sf*/ |
|
| 2041 |
gen_compare(ueq_s, RRR_R, RRR_S, RRR_T); |
|
| 2042 |
break; |
|
| 2043 |
|
|
| 2044 |
case 4: /*OLT.Sf*/ |
|
| 2045 |
gen_compare(olt_s, RRR_R, RRR_S, RRR_T); |
|
| 2046 |
break; |
|
| 2047 |
|
|
| 2048 |
case 5: /*ULT.Sf*/ |
|
| 2049 |
gen_compare(ult_s, RRR_R, RRR_S, RRR_T); |
|
| 2050 |
break; |
|
| 2051 |
|
|
| 2052 |
case 6: /*OLE.Sf*/ |
|
| 2053 |
gen_compare(ole_s, RRR_R, RRR_S, RRR_T); |
|
| 2054 |
break; |
|
| 2055 |
|
|
| 2056 |
case 7: /*ULE.Sf*/ |
|
| 2057 |
gen_compare(ule_s, RRR_R, RRR_S, RRR_T); |
|
| 2058 |
break; |
|
| 2059 |
|
|
| 2060 |
#undef gen_compare |
|
| 2061 |
|
|
| 2062 |
case 8: /*MOVEQZ.Sf*/ |
|
| 2063 |
case 9: /*MOVNEZ.Sf*/ |
|
| 2064 |
case 10: /*MOVLTZ.Sf*/ |
|
| 2065 |
case 11: /*MOVGEZ.Sf*/ |
|
| 2066 |
gen_window_check1(dc, RRR_T); |
|
| 2067 |
{
|
|
| 2068 |
static const TCGCond cond[] = {
|
|
| 2069 |
TCG_COND_NE, |
|
| 2070 |
TCG_COND_EQ, |
|
| 2071 |
TCG_COND_GE, |
|
| 2072 |
TCG_COND_LT |
|
| 2073 |
}; |
|
| 2074 |
int label = gen_new_label(); |
|
| 2075 |
tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label); |
|
| 2076 |
tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]); |
|
| 2077 |
gen_set_label(label); |
|
| 2078 |
} |
|
| 2079 |
break; |
|
| 2080 |
|
|
| 2081 |
case 12: /*MOVF.Sf*/ |
|
| 2082 |
case 13: /*MOVT.Sf*/ |
|
| 2083 |
HAS_OPTION(XTENSA_OPTION_BOOLEAN); |
|
| 2084 |
{
|
|
| 2085 |
int label = gen_new_label(); |
|
| 2086 |
TCGv_i32 tmp = tcg_temp_new_i32(); |
|
| 2087 |
|
|
| 2088 |
tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T); |
|
| 2089 |
tcg_gen_brcondi_i32( |
|
| 2090 |
OP2 & 1 ? TCG_COND_EQ : TCG_COND_NE, |
|
| 2091 |
tmp, 0, label); |
|
| 2092 |
tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]); |
|
| 2093 |
gen_set_label(label); |
|
| 2094 |
tcg_temp_free(tmp); |
|
| 2095 |
} |
|
| 2096 |
break; |
|
| 2097 |
|
|
| 2098 |
default: /*reserved*/ |
|
| 2099 |
RESERVED(); |
|
| 2100 |
break; |
|
| 2101 |
} |
|
| 2023 | 2102 |
break; |
| 2024 | 2103 |
|
| 2025 | 2104 |
default: /*reserved*/ |
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