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/*
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* QEMU Cirrus VGA Emulator.
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*
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* Copyright (c) 2004 Fabrice Bellard
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* Copyright (c) 2004 Suzu
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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#include "vga_int.h" |
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//#define DEBUG_CIRRUS
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/***************************************
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*
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* definitions
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*
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***************************************/
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#define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
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// ID
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#define CIRRUS_ID_CLGD5422 (0x23<<2) |
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#define CIRRUS_ID_CLGD5426 (0x24<<2) |
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#define CIRRUS_ID_CLGD5424 (0x25<<2) |
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#define CIRRUS_ID_CLGD5428 (0x26<<2) |
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#define CIRRUS_ID_CLGD5430 (0x28<<2) |
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#define CIRRUS_ID_CLGD5434 (0x2A<<2) |
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#define CIRRUS_ID_CLGD5446 (0x2E<<2) |
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// sequencer 0x07
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#define CIRRUS_SR7_BPP_VGA 0x00 |
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#define CIRRUS_SR7_BPP_SVGA 0x01 |
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#define CIRRUS_SR7_BPP_MASK 0x0e |
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#define CIRRUS_SR7_BPP_8 0x00 |
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#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02 |
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#define CIRRUS_SR7_BPP_24 0x04 |
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#define CIRRUS_SR7_BPP_16 0x06 |
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#define CIRRUS_SR7_BPP_32 0x08 |
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#define CIRRUS_SR7_ISAADDR_MASK 0xe0 |
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// sequencer 0x0f
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#define CIRRUS_MEMSIZE_512k 0x08 |
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#define CIRRUS_MEMSIZE_1M 0x10 |
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#define CIRRUS_MEMSIZE_2M 0x18 |
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#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled. |
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// sequencer 0x12
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#define CIRRUS_CURSOR_SHOW 0x01 |
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#define CIRRUS_CURSOR_HIDDENPEL 0x02 |
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#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear |
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// sequencer 0x17
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#define CIRRUS_BUSTYPE_VLBFAST 0x10 |
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#define CIRRUS_BUSTYPE_PCI 0x20 |
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#define CIRRUS_BUSTYPE_VLBSLOW 0x30 |
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#define CIRRUS_BUSTYPE_ISA 0x38 |
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#define CIRRUS_MMIO_ENABLE 0x04 |
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#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared. |
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#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80 |
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// control 0x0b
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#define CIRRUS_BANKING_DUAL 0x01 |
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#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k |
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// control 0x30
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#define CIRRUS_BLTMODE_BACKWARDS 0x01 |
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#define CIRRUS_BLTMODE_MEMSYSDEST 0x02 |
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#define CIRRUS_BLTMODE_MEMSYSSRC 0x04 |
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#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08 |
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#define CIRRUS_BLTMODE_PATTERNCOPY 0x40 |
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#define CIRRUS_BLTMODE_COLOREXPAND 0x80 |
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#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30 |
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#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00 |
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#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10 |
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#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20 |
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#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30 |
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// control 0x31
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#define CIRRUS_BLT_BUSY 0x01 |
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#define CIRRUS_BLT_START 0x02 |
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#define CIRRUS_BLT_RESET 0x04 |
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#define CIRRUS_BLT_FIFOUSED 0x10 |
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// control 0x32
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#define CIRRUS_ROP_0 0x00 |
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#define CIRRUS_ROP_SRC_AND_DST 0x05 |
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#define CIRRUS_ROP_NOP 0x06 |
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#define CIRRUS_ROP_SRC_AND_NOTDST 0x09 |
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#define CIRRUS_ROP_NOTDST 0x0b |
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#define CIRRUS_ROP_SRC 0x0d |
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#define CIRRUS_ROP_1 0x0e |
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#define CIRRUS_ROP_NOTSRC_AND_DST 0x50 |
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#define CIRRUS_ROP_SRC_XOR_DST 0x59 |
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#define CIRRUS_ROP_SRC_OR_DST 0x6d |
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#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90 |
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#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95 |
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#define CIRRUS_ROP_SRC_OR_NOTDST 0xad |
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#define CIRRUS_ROP_NOTSRC 0xd0 |
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#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6 |
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#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda |
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// memory-mapped IO
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#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword |
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#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword |
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#define CIRRUS_MMIO_BLTWIDTH 0x08 // word |
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#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word |
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#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word |
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#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word |
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#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword |
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#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword |
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#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte |
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#define CIRRUS_MMIO_BLTMODE 0x18 // byte |
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#define CIRRUS_MMIO_BLTROP 0x1a // byte |
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#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte |
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#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word? |
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#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word? |
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#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word |
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#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word |
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#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word |
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#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word |
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte |
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte |
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte |
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte |
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#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word |
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#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word |
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#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word |
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#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word |
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#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte |
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#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte |
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#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte |
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// PCI 0x00: vendor, 0x02: device
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#define PCI_VENDOR_CIRRUS 0x1013 |
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#define PCI_DEVICE_CLGD5430 0x00a0 // CLGD5430 or CLGD5440 |
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#define PCI_DEVICE_CLGD5434 0x00a8 |
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#define PCI_DEVICE_CLGD5436 0x00ac |
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#define PCI_DEVICE_CLGD5446 0x00b8 |
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#define PCI_DEVICE_CLGD5462 0x00d0 |
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#define PCI_DEVICE_CLGD5465 0x00d6 |
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// PCI 0x04: command(word), 0x06(word): status
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#define PCI_COMMAND_IOACCESS 0x0001 |
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#define PCI_COMMAND_MEMACCESS 0x0002 |
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#define PCI_COMMAND_BUSMASTER 0x0004 |
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#define PCI_COMMAND_SPECIALCYCLE 0x0008 |
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#define PCI_COMMAND_MEMWRITEINVALID 0x0010 |
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#define PCI_COMMAND_PALETTESNOOPING 0x0020 |
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#define PCI_COMMAND_PARITYDETECTION 0x0040 |
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#define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080 |
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#define PCI_COMMAND_SERR 0x0100 |
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#define PCI_COMMAND_BACKTOBACKTRANS 0x0200 |
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// PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
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#define PCI_CLASS_BASE_DISPLAY 0x03 |
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// PCI 0x08, 0x00ff0000
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#define PCI_CLASS_SUB_VGA 0x00 |
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// PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
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#define PCI_CLASS_HEADERTYPE_00h 0x00 |
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// 0x10-0x3f (headertype 00h)
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// PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
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// 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
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#define PCI_MAP_MEM 0x0 |
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#define PCI_MAP_IO 0x1 |
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#define PCI_MAP_MEM_ADDR_MASK (~0xf) |
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#define PCI_MAP_IO_ADDR_MASK (~0x3) |
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#define PCI_MAP_MEMFLAGS_32BIT 0x0 |
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#define PCI_MAP_MEMFLAGS_32BIT_1M 0x1 |
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#define PCI_MAP_MEMFLAGS_64BIT 0x4 |
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#define PCI_MAP_MEMFLAGS_CACHEABLE 0x8 |
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// PCI 0x28: cardbus CIS pointer
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// PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
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// PCI 0x30: expansion ROM base address
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#define PCI_ROMBIOS_ENABLED 0x1 |
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// PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
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// PCI 0x38: reserved
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// PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
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#define CIRRUS_PNPMMIO_SIZE 0x800 |
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/* I/O and memory hook */
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#define CIRRUS_HOOK_NOT_HANDLED 0 |
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#define CIRRUS_HOOK_HANDLED 1 |
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typedef void (*cirrus_bitblt_rop_t) (uint8_t * dst, const uint8_t * src, |
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int dstpitch, int srcpitch, |
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int bltwidth, int bltheight); |
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typedef void (*cirrus_bitblt_handler_t) (void *opaque); |
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typedef struct CirrusVGAState { |
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VGA_STATE_COMMON |
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int cirrus_linear_io_addr;
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int cirrus_mmio_io_addr;
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uint32_t cirrus_addr_mask; |
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uint8_t cirrus_shadow_gr0; |
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uint8_t cirrus_shadow_gr1; |
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uint8_t cirrus_hidden_dac_lockindex; |
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uint8_t cirrus_hidden_dac_data; |
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uint32_t cirrus_bank_base[2];
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uint32_t cirrus_bank_limit[2];
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uint8_t cirrus_hidden_palette[48];
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uint32_t cirrus_hw_cursor_x; |
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uint32_t cirrus_hw_cursor_y; |
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int cirrus_blt_pixelwidth;
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int cirrus_blt_width;
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int cirrus_blt_height;
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int cirrus_blt_dstpitch;
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int cirrus_blt_srcpitch;
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uint32_t cirrus_blt_dstaddr; |
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uint32_t cirrus_blt_srcaddr; |
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uint8_t cirrus_blt_mode; |
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cirrus_bitblt_rop_t cirrus_rop; |
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#define CIRRUS_BLTBUFSIZE 256 |
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uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE]; |
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uint8_t *cirrus_srcptr; |
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uint8_t *cirrus_srcptr_end; |
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uint32_t cirrus_srccounter; |
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uint8_t *cirrus_dstptr; |
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uint8_t *cirrus_dstptr_end; |
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uint32_t cirrus_dstcounter; |
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cirrus_bitblt_handler_t cirrus_blt_handler; |
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int cirrus_blt_horz_counter;
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} CirrusVGAState; |
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typedef struct PCICirrusVGAState { |
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PCIDevice dev; |
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CirrusVGAState cirrus_vga; |
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} PCICirrusVGAState; |
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/***************************************
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*
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* prototypes.
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*
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***************************************/
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static void cirrus_bitblt_reset(CirrusVGAState * s); |
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/***************************************
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*
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* raster operations
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*
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***************************************/
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#define IMPLEMENT_FORWARD_BITBLT(name,opline) \
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static void \ |
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cirrus_bitblt_rop_fwd_##name( \ |
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uint8_t *dst,const uint8_t *src, \
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int dstpitch,int srcpitch, \ |
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int bltwidth,int bltheight) \ |
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{ \ |
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int x,y; \
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dstpitch -= bltwidth; \ |
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srcpitch -= bltwidth; \ |
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for (y = 0; y < bltheight; y++) { \ |
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for (x = 0; x < bltwidth; x++) { \ |
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opline; \ |
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dst++; \ |
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src++; \ |
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} \ |
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dst += dstpitch; \ |
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src += srcpitch; \ |
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} \ |
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} |
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#define IMPLEMENT_BACKWARD_BITBLT(name,opline) \
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static void \ |
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cirrus_bitblt_rop_bkwd_##name( \ |
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uint8_t *dst,const uint8_t *src, \
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int dstpitch,int srcpitch, \ |
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int bltwidth,int bltheight) \ |
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{ \ |
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int x,y; \
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dstpitch += bltwidth; \ |
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srcpitch += bltwidth; \ |
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for (y = 0; y < bltheight; y++) { \ |
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for (x = 0; x < bltwidth; x++) { \ |
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opline; \ |
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dst--; \ |
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src--; \ |
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} \ |
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dst += dstpitch; \ |
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src += srcpitch; \ |
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} \ |
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} |
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IMPLEMENT_FORWARD_BITBLT(0, *dst = 0) |
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IMPLEMENT_FORWARD_BITBLT(src_and_dst, *dst = (*src) & (*dst)) |
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IMPLEMENT_FORWARD_BITBLT(nop, (void) 0) |
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IMPLEMENT_FORWARD_BITBLT(src_and_notdst, *dst = (*src) & (~(*dst))) |
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IMPLEMENT_FORWARD_BITBLT(notdst, *dst = ~(*dst)) |
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IMPLEMENT_FORWARD_BITBLT(src, *dst = *src) |
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IMPLEMENT_FORWARD_BITBLT(1, *dst = 0xff) |
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IMPLEMENT_FORWARD_BITBLT(notsrc_and_dst, *dst = (~(*src)) & (*dst)) |
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IMPLEMENT_FORWARD_BITBLT(src_xor_dst, *dst = (*src) ^ (*dst)) |
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IMPLEMENT_FORWARD_BITBLT(src_or_dst, *dst = (*src) | (*dst)) |
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IMPLEMENT_FORWARD_BITBLT(notsrc_or_notdst, *dst = (~(*src)) | (~(*dst))) |
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IMPLEMENT_FORWARD_BITBLT(src_notxor_dst, *dst = ~((*src) ^ (*dst))) |
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IMPLEMENT_FORWARD_BITBLT(src_or_notdst, *dst = (*src) | (~(*dst))) |
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IMPLEMENT_FORWARD_BITBLT(notsrc, *dst = (~(*src))) |
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IMPLEMENT_FORWARD_BITBLT(notsrc_or_dst, *dst = (~(*src)) | (*dst)) |
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IMPLEMENT_FORWARD_BITBLT(notsrc_and_notdst, *dst = (~(*src)) & (~(*dst))) |
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|
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IMPLEMENT_BACKWARD_BITBLT(0, *dst = 0) |
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IMPLEMENT_BACKWARD_BITBLT(src_and_dst, *dst = (*src) & (*dst)) |
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IMPLEMENT_BACKWARD_BITBLT(nop, (void) 0) |
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IMPLEMENT_BACKWARD_BITBLT(src_and_notdst, *dst = (*src) & (~(*dst))) |
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IMPLEMENT_BACKWARD_BITBLT(notdst, *dst = ~(*dst)) |
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IMPLEMENT_BACKWARD_BITBLT(src, *dst = *src) |
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IMPLEMENT_BACKWARD_BITBLT(1, *dst = 0xff) |
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IMPLEMENT_BACKWARD_BITBLT(notsrc_and_dst, *dst = (~(*src)) & (*dst)) |
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IMPLEMENT_BACKWARD_BITBLT(src_xor_dst, *dst = (*src) ^ (*dst)) |
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IMPLEMENT_BACKWARD_BITBLT(src_or_dst, *dst = (*src) | (*dst)) |
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IMPLEMENT_BACKWARD_BITBLT(notsrc_or_notdst, *dst = (~(*src)) | (~(*dst))) |
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IMPLEMENT_BACKWARD_BITBLT(src_notxor_dst, *dst = ~((*src) ^ (*dst))) |
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IMPLEMENT_BACKWARD_BITBLT(src_or_notdst, *dst = (*src) | (~(*dst))) |
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IMPLEMENT_BACKWARD_BITBLT(notsrc, *dst = (~(*src))) |
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IMPLEMENT_BACKWARD_BITBLT(notsrc_or_dst, *dst = (~(*src)) | (*dst)) |
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IMPLEMENT_BACKWARD_BITBLT(notsrc_and_notdst, *dst = (~(*src)) & (~(*dst))) |
338 |
|
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static cirrus_bitblt_rop_t cirrus_get_fwd_rop_handler(uint8_t rop)
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{ |
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cirrus_bitblt_rop_t rop_handler = cirrus_bitblt_rop_fwd_nop; |
342 |
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switch (rop) {
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case CIRRUS_ROP_0:
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rop_handler = cirrus_bitblt_rop_fwd_0; |
346 |
break;
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case CIRRUS_ROP_SRC_AND_DST:
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rop_handler = cirrus_bitblt_rop_fwd_src_and_dst; |
349 |
break;
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case CIRRUS_ROP_NOP:
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rop_handler = cirrus_bitblt_rop_fwd_nop; |
352 |
break;
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case CIRRUS_ROP_SRC_AND_NOTDST:
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rop_handler = cirrus_bitblt_rop_fwd_src_and_notdst; |
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break;
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case CIRRUS_ROP_NOTDST:
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rop_handler = cirrus_bitblt_rop_fwd_notdst; |
358 |
break;
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case CIRRUS_ROP_SRC:
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rop_handler = cirrus_bitblt_rop_fwd_src; |
361 |
break;
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case CIRRUS_ROP_1:
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rop_handler = cirrus_bitblt_rop_fwd_1; |
364 |
break;
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case CIRRUS_ROP_NOTSRC_AND_DST:
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rop_handler = cirrus_bitblt_rop_fwd_notsrc_and_dst; |
367 |
break;
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case CIRRUS_ROP_SRC_XOR_DST:
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rop_handler = cirrus_bitblt_rop_fwd_src_xor_dst; |
370 |
break;
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case CIRRUS_ROP_SRC_OR_DST:
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rop_handler = cirrus_bitblt_rop_fwd_src_or_dst; |
373 |
break;
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case CIRRUS_ROP_NOTSRC_OR_NOTDST:
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rop_handler = cirrus_bitblt_rop_fwd_notsrc_or_notdst; |
376 |
break;
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case CIRRUS_ROP_SRC_NOTXOR_DST:
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rop_handler = cirrus_bitblt_rop_fwd_src_notxor_dst; |
379 |
break;
|
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case CIRRUS_ROP_SRC_OR_NOTDST:
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rop_handler = cirrus_bitblt_rop_fwd_src_or_notdst; |
382 |
break;
|
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case CIRRUS_ROP_NOTSRC:
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rop_handler = cirrus_bitblt_rop_fwd_notsrc; |
385 |
break;
|
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case CIRRUS_ROP_NOTSRC_OR_DST:
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rop_handler = cirrus_bitblt_rop_fwd_notsrc_or_dst; |
388 |
break;
|
389 |
case CIRRUS_ROP_NOTSRC_AND_NOTDST:
|
390 |
rop_handler = cirrus_bitblt_rop_fwd_notsrc_and_notdst; |
391 |
break;
|
392 |
default:
|
393 |
#ifdef DEBUG_CIRRUS
|
394 |
printf("unknown ROP %02x\n", rop);
|
395 |
#endif
|
396 |
break;
|
397 |
} |
398 |
|
399 |
return rop_handler;
|
400 |
} |
401 |
|
402 |
static cirrus_bitblt_rop_t cirrus_get_bkwd_rop_handler(uint8_t rop)
|
403 |
{ |
404 |
cirrus_bitblt_rop_t rop_handler = cirrus_bitblt_rop_bkwd_nop; |
405 |
|
406 |
switch (rop) {
|
407 |
case CIRRUS_ROP_0:
|
408 |
rop_handler = cirrus_bitblt_rop_bkwd_0; |
409 |
break;
|
410 |
case CIRRUS_ROP_SRC_AND_DST:
|
411 |
rop_handler = cirrus_bitblt_rop_bkwd_src_and_dst; |
412 |
break;
|
413 |
case CIRRUS_ROP_NOP:
|
414 |
rop_handler = cirrus_bitblt_rop_bkwd_nop; |
415 |
break;
|
416 |
case CIRRUS_ROP_SRC_AND_NOTDST:
|
417 |
rop_handler = cirrus_bitblt_rop_bkwd_src_and_notdst; |
418 |
break;
|
419 |
case CIRRUS_ROP_NOTDST:
|
420 |
rop_handler = cirrus_bitblt_rop_bkwd_notdst; |
421 |
break;
|
422 |
case CIRRUS_ROP_SRC:
|
423 |
rop_handler = cirrus_bitblt_rop_bkwd_src; |
424 |
break;
|
425 |
case CIRRUS_ROP_1:
|
426 |
rop_handler = cirrus_bitblt_rop_bkwd_1; |
427 |
break;
|
428 |
case CIRRUS_ROP_NOTSRC_AND_DST:
|
429 |
rop_handler = cirrus_bitblt_rop_bkwd_notsrc_and_dst; |
430 |
break;
|
431 |
case CIRRUS_ROP_SRC_XOR_DST:
|
432 |
rop_handler = cirrus_bitblt_rop_bkwd_src_xor_dst; |
433 |
break;
|
434 |
case CIRRUS_ROP_SRC_OR_DST:
|
435 |
rop_handler = cirrus_bitblt_rop_bkwd_src_or_dst; |
436 |
break;
|
437 |
case CIRRUS_ROP_NOTSRC_OR_NOTDST:
|
438 |
rop_handler = cirrus_bitblt_rop_bkwd_notsrc_or_notdst; |
439 |
break;
|
440 |
case CIRRUS_ROP_SRC_NOTXOR_DST:
|
441 |
rop_handler = cirrus_bitblt_rop_bkwd_src_notxor_dst; |
442 |
break;
|
443 |
case CIRRUS_ROP_SRC_OR_NOTDST:
|
444 |
rop_handler = cirrus_bitblt_rop_bkwd_src_or_notdst; |
445 |
break;
|
446 |
case CIRRUS_ROP_NOTSRC:
|
447 |
rop_handler = cirrus_bitblt_rop_bkwd_notsrc; |
448 |
break;
|
449 |
case CIRRUS_ROP_NOTSRC_OR_DST:
|
450 |
rop_handler = cirrus_bitblt_rop_bkwd_notsrc_or_dst; |
451 |
break;
|
452 |
case CIRRUS_ROP_NOTSRC_AND_NOTDST:
|
453 |
rop_handler = cirrus_bitblt_rop_bkwd_notsrc_and_notdst; |
454 |
break;
|
455 |
default:
|
456 |
#ifdef DEBUG_CIRRUS
|
457 |
printf("unknown ROP %02x\n", rop);
|
458 |
#endif
|
459 |
break;
|
460 |
} |
461 |
|
462 |
return rop_handler;
|
463 |
} |
464 |
|
465 |
/***************************************
|
466 |
*
|
467 |
* color expansion
|
468 |
*
|
469 |
***************************************/
|
470 |
|
471 |
static void |
472 |
cirrus_colorexpand_8(CirrusVGAState * s, uint8_t * dst, |
473 |
const uint8_t * src, int count) |
474 |
{ |
475 |
int x;
|
476 |
uint8_t colors[2];
|
477 |
unsigned bits;
|
478 |
unsigned bitmask;
|
479 |
int srcskipleft = 0; |
480 |
|
481 |
colors[0] = s->gr[0x00]; |
482 |
colors[1] = s->gr[0x01]; |
483 |
|
484 |
bitmask = 0x80 >> srcskipleft;
|
485 |
bits = *src++; |
486 |
for (x = 0; x < count; x++) { |
487 |
if ((bitmask & 0xff) == 0) { |
488 |
bitmask = 0x80;
|
489 |
bits = *src++; |
490 |
} |
491 |
*dst++ = colors[!!(bits & bitmask)]; |
492 |
bitmask >>= 1;
|
493 |
} |
494 |
} |
495 |
|
496 |
static void |
497 |
cirrus_colorexpand_16(CirrusVGAState * s, uint8_t * dst, |
498 |
const uint8_t * src, int count) |
499 |
{ |
500 |
int x;
|
501 |
uint8_t colors[2][2]; |
502 |
unsigned bits;
|
503 |
unsigned bitmask;
|
504 |
unsigned index;
|
505 |
int srcskipleft = 0; |
506 |
|
507 |
colors[0][0] = s->gr[0x00]; |
508 |
colors[0][1] = s->gr[0x10]; |
509 |
colors[1][0] = s->gr[0x01]; |
510 |
colors[1][1] = s->gr[0x11]; |
511 |
|
512 |
bitmask = 0x80 >> srcskipleft;
|
513 |
bits = *src++; |
514 |
for (x = 0; x < count; x++) { |
515 |
if ((bitmask & 0xff) == 0) { |
516 |
bitmask = 0x80;
|
517 |
bits = *src++; |
518 |
} |
519 |
index = !!(bits & bitmask); |
520 |
*dst++ = colors[index][0];
|
521 |
*dst++ = colors[index][1];
|
522 |
bitmask >>= 1;
|
523 |
} |
524 |
} |
525 |
|
526 |
static void |
527 |
cirrus_colorexpand_24(CirrusVGAState * s, uint8_t * dst, |
528 |
const uint8_t * src, int count) |
529 |
{ |
530 |
int x;
|
531 |
uint8_t colors[2][3]; |
532 |
unsigned bits;
|
533 |
unsigned bitmask;
|
534 |
unsigned index;
|
535 |
int srcskipleft = 0; |
536 |
|
537 |
colors[0][0] = s->gr[0x00]; |
538 |
colors[0][1] = s->gr[0x10]; |
539 |
colors[0][2] = s->gr[0x12]; |
540 |
colors[1][0] = s->gr[0x01]; |
541 |
colors[1][1] = s->gr[0x11]; |
542 |
colors[1][2] = s->gr[0x13]; |
543 |
|
544 |
bitmask = 0x80 << srcskipleft;
|
545 |
bits = *src++; |
546 |
for (x = 0; x < count; x++) { |
547 |
if ((bitmask & 0xff) == 0) { |
548 |
bitmask = 0x80;
|
549 |
bits = *src++; |
550 |
} |
551 |
index = !!(bits & bitmask); |
552 |
*dst++ = colors[index][0];
|
553 |
*dst++ = colors[index][1];
|
554 |
*dst++ = colors[index][2];
|
555 |
bitmask >>= 1;
|
556 |
} |
557 |
} |
558 |
|
559 |
static void |
560 |
cirrus_colorexpand_32(CirrusVGAState * s, uint8_t * dst, |
561 |
const uint8_t * src, int count) |
562 |
{ |
563 |
int x;
|
564 |
uint8_t colors[2][4]; |
565 |
unsigned bits;
|
566 |
unsigned bitmask;
|
567 |
unsigned index;
|
568 |
int srcskipleft = 0; |
569 |
|
570 |
colors[0][0] = s->gr[0x00]; |
571 |
colors[0][1] = s->gr[0x10]; |
572 |
colors[0][2] = s->gr[0x12]; |
573 |
colors[0][3] = s->gr[0x14]; |
574 |
colors[1][0] = s->gr[0x01]; |
575 |
colors[1][1] = s->gr[0x11]; |
576 |
colors[1][2] = s->gr[0x13]; |
577 |
colors[1][3] = s->gr[0x15]; |
578 |
|
579 |
bitmask = 0x80 << srcskipleft;
|
580 |
bits = *src++; |
581 |
for (x = 0; x < count; x++) { |
582 |
if ((bitmask & 0xff) == 0) { |
583 |
bitmask = 0x80;
|
584 |
bits = *src++; |
585 |
} |
586 |
index = !!(bits & bitmask); |
587 |
*dst++ = colors[index][0];
|
588 |
*dst++ = colors[index][1];
|
589 |
*dst++ = colors[index][2];
|
590 |
*dst++ = colors[index][3];
|
591 |
bitmask >>= 1;
|
592 |
} |
593 |
} |
594 |
|
595 |
static void |
596 |
cirrus_colorexpand(CirrusVGAState * s, uint8_t * dst, const uint8_t * src,
|
597 |
int count)
|
598 |
{ |
599 |
switch (s->cirrus_blt_pixelwidth) {
|
600 |
case 1: |
601 |
cirrus_colorexpand_8(s, dst, src, count); |
602 |
break;
|
603 |
case 2: |
604 |
cirrus_colorexpand_16(s, dst, src, count); |
605 |
break;
|
606 |
case 3: |
607 |
cirrus_colorexpand_24(s, dst, src, count); |
608 |
break;
|
609 |
case 4: |
610 |
cirrus_colorexpand_32(s, dst, src, count); |
611 |
break;
|
612 |
default:
|
613 |
#ifdef DEBUG_CIRRUS
|
614 |
printf("cirrus: COLOREXPAND pixelwidth %d - unimplemented\n",
|
615 |
s->cirrus_blt_pixelwidth); |
616 |
#endif
|
617 |
break;
|
618 |
} |
619 |
} |
620 |
|
621 |
static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin, |
622 |
int off_pitch, int bytesperline, |
623 |
int lines)
|
624 |
{ |
625 |
int y;
|
626 |
int off_cur;
|
627 |
int off_cur_end;
|
628 |
|
629 |
for (y = 0; y < lines; y++) { |
630 |
off_cur = off_begin; |
631 |
off_cur_end = off_cur + bytesperline; |
632 |
off_cur &= TARGET_PAGE_MASK; |
633 |
while (off_cur < off_cur_end) {
|
634 |
cpu_physical_memory_set_dirty(s->vram_offset + off_cur); |
635 |
off_cur += TARGET_PAGE_SIZE; |
636 |
} |
637 |
off_begin += off_pitch; |
638 |
} |
639 |
} |
640 |
|
641 |
|
642 |
|
643 |
static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s, |
644 |
const uint8_t * src)
|
645 |
{ |
646 |
uint8_t work_colorexp[256];
|
647 |
uint8_t *dst; |
648 |
uint8_t *dstc; |
649 |
int x, y;
|
650 |
int tilewidth, tileheight;
|
651 |
int patternbytes = s->cirrus_blt_pixelwidth * 8; |
652 |
|
653 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
654 |
cirrus_colorexpand(s, work_colorexp, src, 8 * 8); |
655 |
src = work_colorexp; |
656 |
s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_COLOREXPAND; |
657 |
} |
658 |
if (s->cirrus_blt_mode & ~CIRRUS_BLTMODE_PATTERNCOPY) {
|
659 |
#ifdef DEBUG_CIRRUS
|
660 |
printf("cirrus: blt mode %02x (pattercopy) - unimplemented\n",
|
661 |
s->cirrus_blt_mode); |
662 |
#endif
|
663 |
return 0; |
664 |
} |
665 |
|
666 |
dst = s->vram_ptr + s->cirrus_blt_dstaddr; |
667 |
for (y = 0; y < s->cirrus_blt_height; y += 8) { |
668 |
dstc = dst; |
669 |
tileheight = qemu_MIN(8, s->cirrus_blt_height - y);
|
670 |
for (x = 0; x < s->cirrus_blt_width; x += patternbytes) { |
671 |
tilewidth = qemu_MIN(patternbytes, s->cirrus_blt_width - x); |
672 |
(*s->cirrus_rop) (dstc, src, |
673 |
s->cirrus_blt_dstpitch, patternbytes, |
674 |
tilewidth, tileheight); |
675 |
dstc += patternbytes; |
676 |
} |
677 |
dst += s->cirrus_blt_dstpitch * 8;
|
678 |
} |
679 |
cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
680 |
s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
681 |
s->cirrus_blt_height); |
682 |
return 1; |
683 |
} |
684 |
|
685 |
/***************************************
|
686 |
*
|
687 |
* bitblt (video-to-video)
|
688 |
*
|
689 |
***************************************/
|
690 |
|
691 |
static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s) |
692 |
{ |
693 |
return cirrus_bitblt_common_patterncopy(s,
|
694 |
s->vram_ptr + |
695 |
s->cirrus_blt_srcaddr); |
696 |
} |
697 |
|
698 |
static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s) |
699 |
{ |
700 |
if ((s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) != 0) { |
701 |
#ifdef DEBUG_CIRRUS
|
702 |
printf("cirrus: CIRRUS_BLTMODE_COLOREXPAND - unimplemented\n");
|
703 |
#endif
|
704 |
return 0; |
705 |
} |
706 |
if ((s->cirrus_blt_mode & (~CIRRUS_BLTMODE_BACKWARDS)) != 0) { |
707 |
#ifdef DEBUG_CIRRUS
|
708 |
printf("cirrus: blt mode %02x - unimplemented\n",
|
709 |
s->cirrus_blt_mode); |
710 |
#endif
|
711 |
return 0; |
712 |
} |
713 |
|
714 |
(*s->cirrus_rop) (s->vram_ptr + s->cirrus_blt_dstaddr, |
715 |
s->vram_ptr + s->cirrus_blt_srcaddr, |
716 |
s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch, |
717 |
s->cirrus_blt_width, s->cirrus_blt_height); |
718 |
cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
719 |
s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
720 |
s->cirrus_blt_height); |
721 |
return 1; |
722 |
} |
723 |
|
724 |
/***************************************
|
725 |
*
|
726 |
* bitblt (cpu-to-video)
|
727 |
*
|
728 |
***************************************/
|
729 |
|
730 |
static void cirrus_bitblt_cputovideo_patterncopy(void *opaque) |
731 |
{ |
732 |
CirrusVGAState *s = (CirrusVGAState *) opaque; |
733 |
int data_count;
|
734 |
|
735 |
data_count = s->cirrus_srcptr - &s->cirrus_bltbuf[0];
|
736 |
|
737 |
if (data_count > 0) { |
738 |
if (data_count != s->cirrus_srccounter) {
|
739 |
#ifdef DEBUG_CIRRUS
|
740 |
printf("cirrus: internal error\n");
|
741 |
#endif
|
742 |
} else {
|
743 |
cirrus_bitblt_common_patterncopy(s, &s->cirrus_bltbuf[0]);
|
744 |
} |
745 |
cirrus_bitblt_reset(s); |
746 |
} |
747 |
} |
748 |
|
749 |
static void cirrus_bitblt_cputovideo_copy(void *opaque) |
750 |
{ |
751 |
CirrusVGAState *s = (CirrusVGAState *) opaque; |
752 |
int data_count;
|
753 |
int data_avail;
|
754 |
uint8_t work_colorexp[256];
|
755 |
uint8_t *src_ptr = NULL;
|
756 |
int src_avail = 0; |
757 |
int src_processing;
|
758 |
int src_linepad = 0; |
759 |
|
760 |
if (s->cirrus_blt_height <= 0) { |
761 |
s->cirrus_srcptr = s->cirrus_srcptr_end; |
762 |
return;
|
763 |
} |
764 |
|
765 |
s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
766 |
while (1) { |
767 |
/* get BLT source. */
|
768 |
if (src_avail <= 0) { |
769 |
data_count = s->cirrus_srcptr_end - s->cirrus_srcptr; |
770 |
if (data_count <= 0) |
771 |
break;
|
772 |
|
773 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
774 |
if (s->cirrus_blt_mode & ~CIRRUS_BLTMODE_COLOREXPAND) {
|
775 |
#ifdef DEBUG_CIRRUS
|
776 |
printf("cirrus: unsupported\n");
|
777 |
#endif
|
778 |
cirrus_bitblt_reset(s); |
779 |
return;
|
780 |
} |
781 |
data_avail = qemu_MIN(data_count, 256 / 32); |
782 |
cirrus_colorexpand(s, work_colorexp, s->cirrus_srcptr, |
783 |
data_avail * 8);
|
784 |
src_ptr = &work_colorexp[0];
|
785 |
src_avail = data_avail * 8 * s->cirrus_blt_pixelwidth;
|
786 |
s->cirrus_srcptr += data_avail; |
787 |
src_linepad = |
788 |
((s->cirrus_blt_width + 7) / 8) * 8 - |
789 |
s->cirrus_blt_width; |
790 |
src_linepad *= s->cirrus_blt_pixelwidth; |
791 |
} else {
|
792 |
if (s->cirrus_blt_mode != 0) { |
793 |
#ifdef DEBUG_CIRRUS
|
794 |
printf("cirrus: unsupported\n");
|
795 |
#endif
|
796 |
cirrus_bitblt_reset(s); |
797 |
return;
|
798 |
} |
799 |
src_ptr = s->cirrus_srcptr; |
800 |
src_avail = |
801 |
data_count / s->cirrus_blt_pixelwidth * |
802 |
s->cirrus_blt_pixelwidth; |
803 |
s->cirrus_srcptr += src_avail; |
804 |
} |
805 |
if (src_avail <= 0) |
806 |
break;
|
807 |
} |
808 |
|
809 |
/* 1-line BLT */
|
810 |
src_processing = |
811 |
s->cirrus_blt_srcpitch - s->cirrus_blt_horz_counter; |
812 |
src_processing = qemu_MIN(src_avail, src_processing); |
813 |
(*s->cirrus_rop) (s->vram_ptr + s->cirrus_blt_dstaddr, |
814 |
src_ptr, 0, 0, src_processing, 1); |
815 |
cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
|
816 |
src_processing, 1);
|
817 |
|
818 |
s->cirrus_blt_dstaddr += src_processing; |
819 |
src_ptr += src_processing; |
820 |
src_avail -= src_processing; |
821 |
s->cirrus_blt_horz_counter += src_processing; |
822 |
if (s->cirrus_blt_horz_counter >= s->cirrus_blt_srcpitch) {
|
823 |
src_ptr += src_linepad; |
824 |
src_avail -= src_linepad; |
825 |
s->cirrus_blt_dstaddr += |
826 |
s->cirrus_blt_dstpitch - s->cirrus_blt_srcpitch; |
827 |
s->cirrus_blt_horz_counter = 0;
|
828 |
s->cirrus_blt_height--; |
829 |
if (s->cirrus_blt_height <= 0) { |
830 |
s->cirrus_srcptr = s->cirrus_srcptr_end; |
831 |
return;
|
832 |
} |
833 |
} |
834 |
} |
835 |
} |
836 |
|
837 |
static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s) |
838 |
{ |
839 |
int copy_count;
|
840 |
int avail_count;
|
841 |
|
842 |
s->cirrus_blt_handler(s); |
843 |
|
844 |
if (s->cirrus_srccounter > 0) { |
845 |
s->cirrus_srccounter -= s->cirrus_srcptr - &s->cirrus_bltbuf[0];
|
846 |
copy_count = s->cirrus_srcptr_end - s->cirrus_srcptr; |
847 |
memmove(&s->cirrus_bltbuf[0], s->cirrus_srcptr, copy_count);
|
848 |
avail_count = qemu_MIN(CIRRUS_BLTBUFSIZE, s->cirrus_srccounter); |
849 |
s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
850 |
s->cirrus_srcptr_end = s->cirrus_srcptr + avail_count; |
851 |
if (s->cirrus_srccounter <= 0) { |
852 |
cirrus_bitblt_reset(s); |
853 |
} |
854 |
} |
855 |
} |
856 |
|
857 |
/***************************************
|
858 |
*
|
859 |
* bitblt wrapper
|
860 |
*
|
861 |
***************************************/
|
862 |
|
863 |
static void cirrus_bitblt_reset(CirrusVGAState * s) |
864 |
{ |
865 |
s->gr[0x31] &=
|
866 |
~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED); |
867 |
s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
868 |
s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
|
869 |
s->cirrus_srccounter = 0;
|
870 |
s->cirrus_dstptr = &s->cirrus_bltbuf[0];
|
871 |
s->cirrus_dstptr_end = &s->cirrus_bltbuf[0];
|
872 |
s->cirrus_dstcounter = 0;
|
873 |
s->cirrus_blt_handler = NULL;
|
874 |
} |
875 |
|
876 |
static int cirrus_bitblt_cputovideo(CirrusVGAState * s) |
877 |
{ |
878 |
s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC; |
879 |
s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
880 |
s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
|
881 |
|
882 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
883 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
884 |
s->cirrus_srccounter = 8;
|
885 |
} else {
|
886 |
s->cirrus_srccounter = 8 * 8 * s->cirrus_blt_pixelwidth; |
887 |
} |
888 |
s->cirrus_blt_srcpitch = 0;
|
889 |
s->cirrus_blt_handler = cirrus_bitblt_cputovideo_patterncopy; |
890 |
} else {
|
891 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
892 |
s->cirrus_srccounter = |
893 |
((s->cirrus_blt_width + 7) / 8) * s->cirrus_blt_height; |
894 |
s->cirrus_blt_srcpitch = |
895 |
s->cirrus_blt_width * s->cirrus_blt_pixelwidth; |
896 |
} else {
|
897 |
s->cirrus_srccounter = |
898 |
s->cirrus_blt_width * s->cirrus_blt_height; |
899 |
s->cirrus_blt_srcpitch = s->cirrus_blt_width; |
900 |
} |
901 |
/* 4-byte alignment */
|
902 |
s->cirrus_srccounter = (s->cirrus_srccounter + 3) & (~3); |
903 |
|
904 |
s->cirrus_blt_handler = cirrus_bitblt_cputovideo_copy; |
905 |
s->cirrus_blt_horz_counter = 0;
|
906 |
} |
907 |
|
908 |
cirrus_bitblt_cputovideo_next(s); |
909 |
return 1; |
910 |
} |
911 |
|
912 |
static int cirrus_bitblt_videotocpu(CirrusVGAState * s) |
913 |
{ |
914 |
/* XXX */
|
915 |
#ifdef DEBUG_CIRRUS
|
916 |
printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
|
917 |
#endif
|
918 |
return 0; |
919 |
} |
920 |
|
921 |
static int cirrus_bitblt_videotovideo(CirrusVGAState * s) |
922 |
{ |
923 |
int ret;
|
924 |
|
925 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
926 |
ret = cirrus_bitblt_videotovideo_patterncopy(s); |
927 |
} else {
|
928 |
ret = cirrus_bitblt_videotovideo_copy(s); |
929 |
} |
930 |
|
931 |
if (ret)
|
932 |
cirrus_bitblt_reset(s); |
933 |
return ret;
|
934 |
} |
935 |
|
936 |
static void cirrus_bitblt_start(CirrusVGAState * s) |
937 |
{ |
938 |
uint8_t blt_rop; |
939 |
|
940 |
s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1; |
941 |
s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1; |
942 |
s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8)); |
943 |
s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8)); |
944 |
s->cirrus_blt_dstaddr = |
945 |
(s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16)); |
946 |
s->cirrus_blt_srcaddr = |
947 |
(s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16)); |
948 |
s->cirrus_blt_mode = s->gr[0x30];
|
949 |
blt_rop = s->gr[0x32];
|
950 |
|
951 |
switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
|
952 |
case CIRRUS_BLTMODE_PIXELWIDTH8:
|
953 |
s->cirrus_blt_pixelwidth = 1;
|
954 |
break;
|
955 |
case CIRRUS_BLTMODE_PIXELWIDTH16:
|
956 |
s->cirrus_blt_pixelwidth = 2;
|
957 |
break;
|
958 |
case CIRRUS_BLTMODE_PIXELWIDTH24:
|
959 |
s->cirrus_blt_pixelwidth = 3;
|
960 |
break;
|
961 |
case CIRRUS_BLTMODE_PIXELWIDTH32:
|
962 |
s->cirrus_blt_pixelwidth = 4;
|
963 |
break;
|
964 |
default:
|
965 |
#ifdef DEBUG_CIRRUS
|
966 |
printf("cirrus: bitblt - pixel width is unknown\n");
|
967 |
#endif
|
968 |
goto bitblt_ignore;
|
969 |
} |
970 |
s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK; |
971 |
|
972 |
if ((s->
|
973 |
cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC | |
974 |
CIRRUS_BLTMODE_MEMSYSDEST)) |
975 |
== (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) { |
976 |
#ifdef DEBUG_CIRRUS
|
977 |
printf("cirrus: bitblt - memory-to-memory copy is requested\n");
|
978 |
#endif
|
979 |
goto bitblt_ignore;
|
980 |
} |
981 |
|
982 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
|
983 |
s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; |
984 |
s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; |
985 |
s->cirrus_rop = cirrus_get_bkwd_rop_handler(blt_rop); |
986 |
} else {
|
987 |
s->cirrus_rop = cirrus_get_fwd_rop_handler(blt_rop); |
988 |
} |
989 |
|
990 |
// setup bitblt engine.
|
991 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
|
992 |
if (!cirrus_bitblt_cputovideo(s))
|
993 |
goto bitblt_ignore;
|
994 |
} else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) { |
995 |
if (!cirrus_bitblt_videotocpu(s))
|
996 |
goto bitblt_ignore;
|
997 |
} else {
|
998 |
if (!cirrus_bitblt_videotovideo(s))
|
999 |
goto bitblt_ignore;
|
1000 |
} |
1001 |
|
1002 |
return;
|
1003 |
bitblt_ignore:;
|
1004 |
cirrus_bitblt_reset(s); |
1005 |
} |
1006 |
|
1007 |
static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value) |
1008 |
{ |
1009 |
unsigned old_value;
|
1010 |
|
1011 |
old_value = s->gr[0x31];
|
1012 |
s->gr[0x31] = reg_value;
|
1013 |
|
1014 |
if (((old_value & CIRRUS_BLT_RESET) != 0) && |
1015 |
((reg_value & CIRRUS_BLT_RESET) == 0)) {
|
1016 |
cirrus_bitblt_reset(s); |
1017 |
} else if (((old_value & CIRRUS_BLT_START) == 0) && |
1018 |
((reg_value & CIRRUS_BLT_START) != 0)) {
|
1019 |
s->gr[0x31] |= CIRRUS_BLT_BUSY;
|
1020 |
cirrus_bitblt_start(s); |
1021 |
} |
1022 |
} |
1023 |
|
1024 |
|
1025 |
/***************************************
|
1026 |
*
|
1027 |
* basic parameters
|
1028 |
*
|
1029 |
***************************************/
|
1030 |
|
1031 |
static void cirrus_get_offsets(VGAState *s1, |
1032 |
uint32_t *pline_offset, |
1033 |
uint32_t *pstart_addr) |
1034 |
{ |
1035 |
CirrusVGAState * s = (CirrusVGAState *)s1; |
1036 |
uint32_t start_addr; |
1037 |
uint32_t line_offset; |
1038 |
|
1039 |
line_offset = s->cr[0x13]
|
1040 |
| ((s->cr[0x1b] & 0x10) << 4); |
1041 |
line_offset <<= 3;
|
1042 |
*pline_offset = line_offset; |
1043 |
|
1044 |
start_addr = (s->cr[0x0c] << 8) |
1045 |
| s->cr[0x0d]
|
1046 |
| ((s->cr[0x1b] & 0x01) << 16) |
1047 |
| ((s->cr[0x1b] & 0x0c) << 15) |
1048 |
| ((s->cr[0x1d] & 0x80) << 12); |
1049 |
*pstart_addr = start_addr; |
1050 |
} |
1051 |
|
1052 |
static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
|
1053 |
{ |
1054 |
uint32_t ret = 16;
|
1055 |
|
1056 |
switch (s->cirrus_hidden_dac_data & 0xf) { |
1057 |
case 0: |
1058 |
ret = 15;
|
1059 |
break; /* Sierra HiColor */ |
1060 |
case 1: |
1061 |
ret = 16;
|
1062 |
break; /* XGA HiColor */ |
1063 |
default:
|
1064 |
#ifdef DEBUG_CIRRUS
|
1065 |
printf("cirrus: invalid DAC value %x in 16bpp\n",
|
1066 |
(s->cirrus_hidden_dac_data & 0xf));
|
1067 |
#endif
|
1068 |
ret = 15; /* XXX */ |
1069 |
break;
|
1070 |
} |
1071 |
return ret;
|
1072 |
} |
1073 |
|
1074 |
static int cirrus_get_bpp(VGAState *s1) |
1075 |
{ |
1076 |
CirrusVGAState * s = (CirrusVGAState *)s1; |
1077 |
uint32_t ret = 8;
|
1078 |
|
1079 |
if ((s->sr[0x07] & 0x01) != 0) { |
1080 |
/* Cirrus SVGA */
|
1081 |
switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) { |
1082 |
case CIRRUS_SR7_BPP_8:
|
1083 |
ret = 8;
|
1084 |
break;
|
1085 |
case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
|
1086 |
ret = cirrus_get_bpp16_depth(s); |
1087 |
break;
|
1088 |
case CIRRUS_SR7_BPP_24:
|
1089 |
ret = 24;
|
1090 |
break;
|
1091 |
case CIRRUS_SR7_BPP_16:
|
1092 |
ret = cirrus_get_bpp16_depth(s); |
1093 |
break;
|
1094 |
case CIRRUS_SR7_BPP_32:
|
1095 |
ret = 32;
|
1096 |
break;
|
1097 |
default:
|
1098 |
#ifdef DEBUG_CIRRUS
|
1099 |
printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]); |
1100 |
#endif
|
1101 |
ret = 8;
|
1102 |
break;
|
1103 |
} |
1104 |
} else {
|
1105 |
/* VGA */
|
1106 |
ret = 8;
|
1107 |
} |
1108 |
|
1109 |
return ret;
|
1110 |
} |
1111 |
|
1112 |
/***************************************
|
1113 |
*
|
1114 |
* bank memory
|
1115 |
*
|
1116 |
***************************************/
|
1117 |
|
1118 |
static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index) |
1119 |
{ |
1120 |
unsigned offset;
|
1121 |
unsigned limit;
|
1122 |
|
1123 |
if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */ |
1124 |
offset = s->gr[0x09 + bank_index];
|
1125 |
else /* single bank */ |
1126 |
offset = s->gr[0x09];
|
1127 |
|
1128 |
if ((s->gr[0x0b] & 0x20) != 0) |
1129 |
offset <<= 14;
|
1130 |
else
|
1131 |
offset <<= 12;
|
1132 |
|
1133 |
if (s->vram_size <= offset)
|
1134 |
limit = 0;
|
1135 |
else
|
1136 |
limit = s->vram_size - offset; |
1137 |
|
1138 |
if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) { |
1139 |
if (limit > 0x8000) { |
1140 |
offset += 0x8000;
|
1141 |
limit -= 0x8000;
|
1142 |
} else {
|
1143 |
limit = 0;
|
1144 |
} |
1145 |
} |
1146 |
|
1147 |
if (limit > 0) { |
1148 |
s->cirrus_bank_base[bank_index] = offset; |
1149 |
s->cirrus_bank_limit[bank_index] = limit; |
1150 |
} else {
|
1151 |
s->cirrus_bank_base[bank_index] = 0;
|
1152 |
s->cirrus_bank_limit[bank_index] = 0;
|
1153 |
} |
1154 |
} |
1155 |
|
1156 |
/***************************************
|
1157 |
*
|
1158 |
* I/O access between 0x3c4-0x3c5
|
1159 |
*
|
1160 |
***************************************/
|
1161 |
|
1162 |
static int |
1163 |
cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value) |
1164 |
{ |
1165 |
switch (reg_index) {
|
1166 |
case 0x00: // Standard VGA |
1167 |
case 0x01: // Standard VGA |
1168 |
case 0x02: // Standard VGA |
1169 |
case 0x03: // Standard VGA |
1170 |
case 0x04: // Standard VGA |
1171 |
return CIRRUS_HOOK_NOT_HANDLED;
|
1172 |
case 0x06: // Unlock Cirrus extensions |
1173 |
*reg_value = s->sr[reg_index]; |
1174 |
break;
|
1175 |
case 0x05: // ??? |
1176 |
case 0x07: // Extended Sequencer Mode |
1177 |
case 0x08: // EEPROM Control |
1178 |
case 0x09: // Scratch Register 0 |
1179 |
case 0x0a: // Scratch Register 1 |
1180 |
case 0x0b: // VCLK 0 |
1181 |
case 0x0c: // VCLK 1 |
1182 |
case 0x0d: // VCLK 2 |
1183 |
case 0x0e: // VCLK 3 |
1184 |
case 0x0f: // DRAM Control |
1185 |
case 0x10: |
1186 |
case 0x30: |
1187 |
case 0x50: |
1188 |
case 0x70: // Graphics Cursor X |
1189 |
case 0x90: |
1190 |
case 0xb0: |
1191 |
case 0xd0: |
1192 |
case 0xf0: // Graphics Cursor X |
1193 |
case 0x11: |
1194 |
case 0x31: |
1195 |
case 0x51: |
1196 |
case 0x71: // Graphics Cursor Y |
1197 |
case 0x91: |
1198 |
case 0xb1: |
1199 |
case 0xd1: |
1200 |
case 0xf1: // Graphics Cursor Y |
1201 |
case 0x12: // Graphics Cursor Attribute |
1202 |
case 0x13: // Graphics Cursor Pattern Address |
1203 |
case 0x14: // Scratch Register 2 |
1204 |
case 0x15: // Scratch Register 3 |
1205 |
case 0x16: // Performance Tuning Register |
1206 |
case 0x17: // Configuration Readback and Extended Control |
1207 |
case 0x18: // Signature Generator Control |
1208 |
case 0x19: // Signal Generator Result |
1209 |
case 0x1a: // Signal Generator Result |
1210 |
case 0x1b: // VCLK 0 Denominator & Post |
1211 |
case 0x1c: // VCLK 1 Denominator & Post |
1212 |
case 0x1d: // VCLK 2 Denominator & Post |
1213 |
case 0x1e: // VCLK 3 Denominator & Post |
1214 |
case 0x1f: // BIOS Write Enable and MCLK select |
1215 |
#ifdef DEBUG_CIRRUS
|
1216 |
printf("cirrus: handled inport sr_index %02x\n", reg_index);
|
1217 |
#endif
|
1218 |
*reg_value = s->sr[reg_index]; |
1219 |
break;
|
1220 |
default:
|
1221 |
#ifdef DEBUG_CIRRUS
|
1222 |
printf("cirrus: inport sr_index %02x\n", reg_index);
|
1223 |
#endif
|
1224 |
*reg_value = 0xff;
|
1225 |
break;
|
1226 |
} |
1227 |
|
1228 |
return CIRRUS_HOOK_HANDLED;
|
1229 |
} |
1230 |
|
1231 |
static int |
1232 |
cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value) |
1233 |
{ |
1234 |
switch (reg_index) {
|
1235 |
case 0x00: // Standard VGA |
1236 |
case 0x01: // Standard VGA |
1237 |
case 0x02: // Standard VGA |
1238 |
case 0x03: // Standard VGA |
1239 |
case 0x04: // Standard VGA |
1240 |
return CIRRUS_HOOK_NOT_HANDLED;
|
1241 |
case 0x06: // Unlock Cirrus extensions |
1242 |
reg_value &= 0x17;
|
1243 |
if (reg_value == 0x12) { |
1244 |
s->sr[reg_index] = 0x12;
|
1245 |
} else {
|
1246 |
s->sr[reg_index] = 0x0f;
|
1247 |
} |
1248 |
break;
|
1249 |
case 0x10: |
1250 |
case 0x30: |
1251 |
case 0x50: |
1252 |
case 0x70: // Graphics Cursor X |
1253 |
case 0x90: |
1254 |
case 0xb0: |
1255 |
case 0xd0: |
1256 |
case 0xf0: // Graphics Cursor X |
1257 |
s->sr[0x10] = reg_value;
|
1258 |
s->cirrus_hw_cursor_x = ((reg_index << 3) & 0x700) | reg_value; |
1259 |
break;
|
1260 |
case 0x11: |
1261 |
case 0x31: |
1262 |
case 0x51: |
1263 |
case 0x71: // Graphics Cursor Y |
1264 |
case 0x91: |
1265 |
case 0xb1: |
1266 |
case 0xd1: |
1267 |
case 0xf1: // Graphics Cursor Y |
1268 |
s->sr[0x11] = reg_value;
|
1269 |
s->cirrus_hw_cursor_y = ((reg_index << 3) & 0x700) | reg_value; |
1270 |
break;
|
1271 |
case 0x07: // Extended Sequencer Mode |
1272 |
case 0x08: // EEPROM Control |
1273 |
case 0x09: // Scratch Register 0 |
1274 |
case 0x0a: // Scratch Register 1 |
1275 |
case 0x0b: // VCLK 0 |
1276 |
case 0x0c: // VCLK 1 |
1277 |
case 0x0d: // VCLK 2 |
1278 |
case 0x0e: // VCLK 3 |
1279 |
case 0x0f: // DRAM Control |
1280 |
case 0x12: // Graphics Cursor Attribute |
1281 |
case 0x13: // Graphics Cursor Pattern Address |
1282 |
case 0x14: // Scratch Register 2 |
1283 |
case 0x15: // Scratch Register 3 |
1284 |
case 0x16: // Performance Tuning Register |
1285 |
case 0x17: // Configuration Readback and Extended Control |
1286 |
case 0x18: // Signature Generator Control |
1287 |
case 0x19: // Signature Generator Result |
1288 |
case 0x1a: // Signature Generator Result |
1289 |
case 0x1b: // VCLK 0 Denominator & Post |
1290 |
case 0x1c: // VCLK 1 Denominator & Post |
1291 |
case 0x1d: // VCLK 2 Denominator & Post |
1292 |
case 0x1e: // VCLK 3 Denominator & Post |
1293 |
case 0x1f: // BIOS Write Enable and MCLK select |
1294 |
s->sr[reg_index] = reg_value; |
1295 |
#ifdef DEBUG_CIRRUS
|
1296 |
printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
|
1297 |
reg_index, reg_value); |
1298 |
#endif
|
1299 |
break;
|
1300 |
default:
|
1301 |
#ifdef DEBUG_CIRRUS
|
1302 |
printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
|
1303 |
reg_value); |
1304 |
#endif
|
1305 |
break;
|
1306 |
} |
1307 |
|
1308 |
return CIRRUS_HOOK_HANDLED;
|
1309 |
} |
1310 |
|
1311 |
/***************************************
|
1312 |
*
|
1313 |
* I/O access at 0x3c6
|
1314 |
*
|
1315 |
***************************************/
|
1316 |
|
1317 |
static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value) |
1318 |
{ |
1319 |
*reg_value = 0xff;
|
1320 |
if (s->cirrus_hidden_dac_lockindex < 5) { |
1321 |
if (s->cirrus_hidden_dac_lockindex == 4) { |
1322 |
*reg_value = s->cirrus_hidden_dac_data; |
1323 |
} |
1324 |
s->cirrus_hidden_dac_lockindex++; |
1325 |
} |
1326 |
} |
1327 |
|
1328 |
static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value) |
1329 |
{ |
1330 |
if (s->cirrus_hidden_dac_lockindex == 4) { |
1331 |
s->cirrus_hidden_dac_data = reg_value; |
1332 |
#ifdef DEBUG_CIRRUS
|
1333 |
printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
|
1334 |
#endif
|
1335 |
} |
1336 |
s->cirrus_hidden_dac_lockindex = 0;
|
1337 |
} |
1338 |
|
1339 |
/***************************************
|
1340 |
*
|
1341 |
* I/O access at 0x3c9
|
1342 |
*
|
1343 |
***************************************/
|
1344 |
|
1345 |
static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value) |
1346 |
{ |
1347 |
if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) |
1348 |
return CIRRUS_HOOK_NOT_HANDLED;
|
1349 |
if (s->dac_read_index < 0x10) { |
1350 |
*reg_value = |
1351 |
s->cirrus_hidden_palette[s->dac_read_index * 3 +
|
1352 |
s->dac_sub_index]; |
1353 |
} else {
|
1354 |
*reg_value = 0xff; /* XXX */ |
1355 |
} |
1356 |
if (++s->dac_sub_index == 3) { |
1357 |
s->dac_sub_index = 0;
|
1358 |
s->dac_read_index++; |
1359 |
} |
1360 |
return CIRRUS_HOOK_HANDLED;
|
1361 |
} |
1362 |
|
1363 |
static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value) |
1364 |
{ |
1365 |
if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) |
1366 |
return CIRRUS_HOOK_NOT_HANDLED;
|
1367 |
s->dac_cache[s->dac_sub_index] = reg_value; |
1368 |
if (++s->dac_sub_index == 3) { |
1369 |
if (s->dac_read_index < 0x10) { |
1370 |
memcpy(&s->cirrus_hidden_palette[s->dac_write_index * 3],
|
1371 |
s->dac_cache, 3);
|
1372 |
/* XXX update cursor */
|
1373 |
} |
1374 |
s->dac_sub_index = 0;
|
1375 |
s->dac_write_index++; |
1376 |
} |
1377 |
return CIRRUS_HOOK_HANDLED;
|
1378 |
} |
1379 |
|
1380 |
/***************************************
|
1381 |
*
|
1382 |
* I/O access between 0x3ce-0x3cf
|
1383 |
*
|
1384 |
***************************************/
|
1385 |
|
1386 |
static int |
1387 |
cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value) |
1388 |
{ |
1389 |
switch (reg_index) {
|
1390 |
case 0x02: // Standard VGA |
1391 |
case 0x03: // Standard VGA |
1392 |
case 0x04: // Standard VGA |
1393 |
case 0x06: // Standard VGA |
1394 |
case 0x07: // Standard VGA |
1395 |
case 0x08: // Standard VGA |
1396 |
return CIRRUS_HOOK_NOT_HANDLED;
|
1397 |
case 0x05: // Standard VGA, Cirrus extended mode |
1398 |
default:
|
1399 |
break;
|
1400 |
} |
1401 |
|
1402 |
if (reg_index < 0x3a) { |
1403 |
*reg_value = s->gr[reg_index]; |
1404 |
} else {
|
1405 |
#ifdef DEBUG_CIRRUS
|
1406 |
printf("cirrus: inport gr_index %02x\n", reg_index);
|
1407 |
#endif
|
1408 |
*reg_value = 0xff;
|
1409 |
} |
1410 |
|
1411 |
return CIRRUS_HOOK_HANDLED;
|
1412 |
} |
1413 |
|
1414 |
static int |
1415 |
cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value) |
1416 |
{ |
1417 |
switch (reg_index) {
|
1418 |
case 0x00: // Standard VGA, BGCOLOR 0x000000ff |
1419 |
s->gr[0x00] = reg_value;
|
1420 |
return CIRRUS_HOOK_NOT_HANDLED;
|
1421 |
case 0x01: // Standard VGA, FGCOLOR 0x000000ff |
1422 |
s->gr[0x01] = reg_value;
|
1423 |
return CIRRUS_HOOK_NOT_HANDLED;
|
1424 |
case 0x02: // Standard VGA |
1425 |
case 0x03: // Standard VGA |
1426 |
case 0x04: // Standard VGA |
1427 |
case 0x06: // Standard VGA |
1428 |
case 0x07: // Standard VGA |
1429 |
case 0x08: // Standard VGA |
1430 |
return CIRRUS_HOOK_NOT_HANDLED;
|
1431 |
case 0x05: // Standard VGA, Cirrus extended mode |
1432 |
s->gr[reg_index] = reg_value & 0x7f;
|
1433 |
break;
|
1434 |
case 0x09: // bank offset #0 |
1435 |
case 0x0A: // bank offset #1 |
1436 |
case 0x0B: |
1437 |
s->gr[reg_index] = reg_value; |
1438 |
cirrus_update_bank_ptr(s, 0);
|
1439 |
cirrus_update_bank_ptr(s, 1);
|
1440 |
break;
|
1441 |
case 0x10: // BGCOLOR 0x0000ff00 |
1442 |
case 0x11: // FGCOLOR 0x0000ff00 |
1443 |
case 0x12: // BGCOLOR 0x00ff0000 |
1444 |
case 0x13: // FGCOLOR 0x00ff0000 |
1445 |
case 0x14: // BGCOLOR 0xff000000 |
1446 |
case 0x15: // FGCOLOR 0xff000000 |
1447 |
case 0x20: // BLT WIDTH 0x0000ff |
1448 |
case 0x22: // BLT HEIGHT 0x0000ff |
1449 |
case 0x24: // BLT DEST PITCH 0x0000ff |
1450 |
case 0x26: // BLT SRC PITCH 0x0000ff |
1451 |
case 0x28: // BLT DEST ADDR 0x0000ff |
1452 |
case 0x29: // BLT DEST ADDR 0x00ff00 |
1453 |
case 0x2c: // BLT SRC ADDR 0x0000ff |
1454 |
case 0x2d: // BLT SRC ADDR 0x00ff00 |
1455 |
case 0x30: // BLT MODE |
1456 |
case 0x32: // RASTER OP |
1457 |
case 0x34: // BLT TRANSPARENT COLOR 0x00ff |
1458 |
case 0x35: // BLT TRANSPARENT COLOR 0xff00 |
1459 |
case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff |
1460 |
case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00 |
1461 |
s->gr[reg_index] = reg_value; |
1462 |
break;
|
1463 |
case 0x21: // BLT WIDTH 0x001f00 |
1464 |
case 0x23: // BLT HEIGHT 0x001f00 |
1465 |
case 0x25: // BLT DEST PITCH 0x001f00 |
1466 |
case 0x27: // BLT SRC PITCH 0x001f00 |
1467 |
s->gr[reg_index] = reg_value & 0x1f;
|
1468 |
break;
|
1469 |
case 0x2a: // BLT DEST ADDR 0x3f0000 |
1470 |
case 0x2e: // BLT SRC ADDR 0x3f0000 |
1471 |
s->gr[reg_index] = reg_value & 0x3f;
|
1472 |
break;
|
1473 |
case 0x31: // BLT STATUS/START |
1474 |
cirrus_write_bitblt(s, reg_value); |
1475 |
break;
|
1476 |
default:
|
1477 |
#ifdef DEBUG_CIRRUS
|
1478 |
printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
|
1479 |
reg_value); |
1480 |
#endif
|
1481 |
break;
|
1482 |
} |
1483 |
|
1484 |
return CIRRUS_HOOK_HANDLED;
|
1485 |
} |
1486 |
|
1487 |
/***************************************
|
1488 |
*
|
1489 |
* I/O access between 0x3d4-0x3d5
|
1490 |
*
|
1491 |
***************************************/
|
1492 |
|
1493 |
static int |
1494 |
cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value) |
1495 |
{ |
1496 |
switch (reg_index) {
|
1497 |
case 0x00: // Standard VGA |
1498 |
case 0x01: // Standard VGA |
1499 |
case 0x02: // Standard VGA |
1500 |
case 0x03: // Standard VGA |
1501 |
case 0x04: // Standard VGA |
1502 |
case 0x05: // Standard VGA |
1503 |
case 0x06: // Standard VGA |
1504 |
case 0x07: // Standard VGA |
1505 |
case 0x08: // Standard VGA |
1506 |
case 0x09: // Standard VGA |
1507 |
case 0x0a: // Standard VGA |
1508 |
case 0x0b: // Standard VGA |
1509 |
case 0x0c: // Standard VGA |
1510 |
case 0x0d: // Standard VGA |
1511 |
case 0x0e: // Standard VGA |
1512 |
case 0x0f: // Standard VGA |
1513 |
case 0x10: // Standard VGA |
1514 |
case 0x11: // Standard VGA |
1515 |
case 0x12: // Standard VGA |
1516 |
case 0x13: // Standard VGA |
1517 |
case 0x14: // Standard VGA |
1518 |
case 0x15: // Standard VGA |
1519 |
case 0x16: // Standard VGA |
1520 |
case 0x17: // Standard VGA |
1521 |
case 0x18: // Standard VGA |
1522 |
return CIRRUS_HOOK_NOT_HANDLED;
|
1523 |
case 0x19: // Interlace End |
1524 |
case 0x1a: // Miscellaneous Control |
1525 |
case 0x1b: // Extended Display Control |
1526 |
case 0x1c: // Sync Adjust and Genlock |
1527 |
case 0x1d: // Overlay Extended Control |
1528 |
case 0x22: // Graphics Data Latches Readback (R) |
1529 |
case 0x24: // Attribute Controller Toggle Readback (R) |
1530 |
case 0x25: // Part Status |
1531 |
case 0x27: // Part ID (R) |
1532 |
*reg_value = s->cr[reg_index]; |
1533 |
break;
|
1534 |
case 0x26: // Attribute Controller Index Readback (R) |
1535 |
*reg_value = s->ar_index & 0x3f;
|
1536 |
break;
|
1537 |
default:
|
1538 |
#ifdef DEBUG_CIRRUS
|
1539 |
printf("cirrus: inport cr_index %02x\n", reg_index);
|
1540 |
*reg_value = 0xff;
|
1541 |
#endif
|
1542 |
break;
|
1543 |
} |
1544 |
|
1545 |
return CIRRUS_HOOK_HANDLED;
|
1546 |
} |
1547 |
|
1548 |
static int |
1549 |
cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value) |
1550 |
{ |
1551 |
switch (reg_index) {
|
1552 |
case 0x00: // Standard VGA |
1553 |
case 0x01: // Standard VGA |
1554 |
case 0x02: // Standard VGA |
1555 |
case 0x03: // Standard VGA |
1556 |
case 0x04: // Standard VGA |
1557 |
case 0x05: // Standard VGA |
1558 |
case 0x06: // Standard VGA |
1559 |
case 0x07: // Standard VGA |
1560 |
case 0x08: // Standard VGA |
1561 |
case 0x09: // Standard VGA |
1562 |
case 0x0a: // Standard VGA |
1563 |
case 0x0b: // Standard VGA |
1564 |
case 0x0c: // Standard VGA |
1565 |
case 0x0d: // Standard VGA |
1566 |
case 0x0e: // Standard VGA |
1567 |
case 0x0f: // Standard VGA |
1568 |
case 0x10: // Standard VGA |
1569 |
case 0x11: // Standard VGA |
1570 |
case 0x12: // Standard VGA |
1571 |
case 0x13: // Standard VGA |
1572 |
case 0x14: // Standard VGA |
1573 |
case 0x15: // Standard VGA |
1574 |
case 0x16: // Standard VGA |
1575 |
case 0x17: // Standard VGA |
1576 |
case 0x18: // Standard VGA |
1577 |
return CIRRUS_HOOK_NOT_HANDLED;
|
1578 |
case 0x19: // Interlace End |
1579 |
case 0x1a: // Miscellaneous Control |
1580 |
case 0x1b: // Extended Display Control |
1581 |
case 0x1c: // Sync Adjust and Genlock |
1582 |
s->cr[reg_index] = reg_value; |
1583 |
#ifdef DEBUG_CIRRUS
|
1584 |
printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
|
1585 |
reg_index, reg_value); |
1586 |
#endif
|
1587 |
break;
|
1588 |
case 0x22: // Graphics Data Latches Readback (R) |
1589 |
case 0x24: // Attribute Controller Toggle Readback (R) |
1590 |
case 0x26: // Attribute Controller Index Readback (R) |
1591 |
case 0x27: // Part ID (R) |
1592 |
break;
|
1593 |
case 0x1d: // Overlay Extended Control |
1594 |
case 0x25: // Part Status |
1595 |
default:
|
1596 |
#ifdef DEBUG_CIRRUS
|
1597 |
printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
|
1598 |
reg_value); |
1599 |
#endif
|
1600 |
break;
|
1601 |
} |
1602 |
|
1603 |
return CIRRUS_HOOK_HANDLED;
|
1604 |
} |
1605 |
|
1606 |
/***************************************
|
1607 |
*
|
1608 |
* memory-mapped I/O (bitblt)
|
1609 |
*
|
1610 |
***************************************/
|
1611 |
|
1612 |
static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address) |
1613 |
{ |
1614 |
int value = 0xff; |
1615 |
|
1616 |
switch (address) {
|
1617 |
case (CIRRUS_MMIO_BLTBGCOLOR + 0): |
1618 |
cirrus_hook_read_gr(s, 0x00, &value);
|
1619 |
break;
|
1620 |
case (CIRRUS_MMIO_BLTBGCOLOR + 1): |
1621 |
cirrus_hook_read_gr(s, 0x10, &value);
|
1622 |
break;
|
1623 |
case (CIRRUS_MMIO_BLTBGCOLOR + 2): |
1624 |
cirrus_hook_read_gr(s, 0x12, &value);
|
1625 |
break;
|
1626 |
case (CIRRUS_MMIO_BLTBGCOLOR + 3): |
1627 |
cirrus_hook_read_gr(s, 0x14, &value);
|
1628 |
break;
|
1629 |
case (CIRRUS_MMIO_BLTFGCOLOR + 0): |
1630 |
cirrus_hook_read_gr(s, 0x01, &value);
|
1631 |
break;
|
1632 |
case (CIRRUS_MMIO_BLTFGCOLOR + 1): |
1633 |
cirrus_hook_read_gr(s, 0x11, &value);
|
1634 |
break;
|
1635 |
case (CIRRUS_MMIO_BLTFGCOLOR + 2): |
1636 |
cirrus_hook_read_gr(s, 0x13, &value);
|
1637 |
break;
|
1638 |
case (CIRRUS_MMIO_BLTFGCOLOR + 3): |
1639 |
cirrus_hook_read_gr(s, 0x15, &value);
|
1640 |
break;
|
1641 |
case (CIRRUS_MMIO_BLTWIDTH + 0): |
1642 |
cirrus_hook_read_gr(s, 0x20, &value);
|
1643 |
break;
|
1644 |
case (CIRRUS_MMIO_BLTWIDTH + 1): |
1645 |
cirrus_hook_read_gr(s, 0x21, &value);
|
1646 |
break;
|
1647 |
case (CIRRUS_MMIO_BLTHEIGHT + 0): |
1648 |
cirrus_hook_read_gr(s, 0x22, &value);
|
1649 |
break;
|
1650 |
case (CIRRUS_MMIO_BLTHEIGHT + 1): |
1651 |
cirrus_hook_read_gr(s, 0x23, &value);
|
1652 |
break;
|
1653 |
case (CIRRUS_MMIO_BLTDESTPITCH + 0): |
1654 |
cirrus_hook_read_gr(s, 0x24, &value);
|
1655 |
break;
|
1656 |
case (CIRRUS_MMIO_BLTDESTPITCH + 1): |
1657 |
cirrus_hook_read_gr(s, 0x25, &value);
|
1658 |
break;
|
1659 |
case (CIRRUS_MMIO_BLTSRCPITCH + 0): |
1660 |
cirrus_hook_read_gr(s, 0x26, &value);
|
1661 |
break;
|
1662 |
case (CIRRUS_MMIO_BLTSRCPITCH + 1): |
1663 |
cirrus_hook_read_gr(s, 0x27, &value);
|
1664 |
break;
|
1665 |
case (CIRRUS_MMIO_BLTDESTADDR + 0): |
1666 |
cirrus_hook_read_gr(s, 0x28, &value);
|
1667 |
break;
|
1668 |
case (CIRRUS_MMIO_BLTDESTADDR + 1): |
1669 |
cirrus_hook_read_gr(s, 0x29, &value);
|
1670 |
break;
|
1671 |
case (CIRRUS_MMIO_BLTDESTADDR + 2): |
1672 |
cirrus_hook_read_gr(s, 0x2a, &value);
|
1673 |
break;
|
1674 |
case (CIRRUS_MMIO_BLTSRCADDR + 0): |
1675 |
cirrus_hook_read_gr(s, 0x2c, &value);
|
1676 |
break;
|
1677 |
case (CIRRUS_MMIO_BLTSRCADDR + 1): |
1678 |
cirrus_hook_read_gr(s, 0x2d, &value);
|
1679 |
break;
|
1680 |
case (CIRRUS_MMIO_BLTSRCADDR + 2): |
1681 |
cirrus_hook_read_gr(s, 0x2e, &value);
|
1682 |
break;
|
1683 |
case CIRRUS_MMIO_BLTWRITEMASK:
|
1684 |
cirrus_hook_read_gr(s, 0x2f, &value);
|
1685 |
break;
|
1686 |
case CIRRUS_MMIO_BLTMODE:
|
1687 |
cirrus_hook_read_gr(s, 0x30, &value);
|
1688 |
break;
|
1689 |
case CIRRUS_MMIO_BLTROP:
|
1690 |
cirrus_hook_read_gr(s, 0x32, &value);
|
1691 |
break;
|
1692 |
case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): |
1693 |
cirrus_hook_read_gr(s, 0x34, &value);
|
1694 |
break;
|
1695 |
case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): |
1696 |
cirrus_hook_read_gr(s, 0x35, &value);
|
1697 |
break;
|
1698 |
case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): |
1699 |
cirrus_hook_read_gr(s, 0x38, &value);
|
1700 |
break;
|
1701 |
case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): |
1702 |
cirrus_hook_read_gr(s, 0x39, &value);
|
1703 |
break;
|
1704 |
case CIRRUS_MMIO_BLTSTATUS:
|
1705 |
cirrus_hook_read_gr(s, 0x31, &value);
|
1706 |
break;
|
1707 |
default:
|
1708 |
#ifdef DEBUG_CIRRUS
|
1709 |
printf("cirrus: mmio read - address 0x%04x\n", address);
|
1710 |
#endif
|
1711 |
break;
|
1712 |
} |
1713 |
|
1714 |
return (uint8_t) value;
|
1715 |
} |
1716 |
|
1717 |
static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address, |
1718 |
uint8_t value) |
1719 |
{ |
1720 |
switch (address) {
|
1721 |
case (CIRRUS_MMIO_BLTBGCOLOR + 0): |
1722 |
cirrus_hook_write_gr(s, 0x00, value);
|
1723 |
break;
|
1724 |
case (CIRRUS_MMIO_BLTBGCOLOR + 1): |
1725 |
cirrus_hook_write_gr(s, 0x10, value);
|
1726 |
break;
|
1727 |
case (CIRRUS_MMIO_BLTBGCOLOR + 2): |
1728 |
cirrus_hook_write_gr(s, 0x12, value);
|
1729 |
break;
|
1730 |
case (CIRRUS_MMIO_BLTBGCOLOR + 3): |
1731 |
cirrus_hook_write_gr(s, 0x14, value);
|
1732 |
break;
|
1733 |
case (CIRRUS_MMIO_BLTFGCOLOR + 0): |
1734 |
cirrus_hook_write_gr(s, 0x01, value);
|
1735 |
break;
|
1736 |
case (CIRRUS_MMIO_BLTFGCOLOR + 1): |
1737 |
cirrus_hook_write_gr(s, 0x11, value);
|
1738 |
break;
|
1739 |
case (CIRRUS_MMIO_BLTFGCOLOR + 2): |
1740 |
cirrus_hook_write_gr(s, 0x13, value);
|
1741 |
break;
|
1742 |
case (CIRRUS_MMIO_BLTFGCOLOR + 3): |
1743 |
cirrus_hook_write_gr(s, 0x15, value);
|
1744 |
break;
|
1745 |
case (CIRRUS_MMIO_BLTWIDTH + 0): |
1746 |
cirrus_hook_write_gr(s, 0x20, value);
|
1747 |
break;
|
1748 |
case (CIRRUS_MMIO_BLTWIDTH + 1): |
1749 |
cirrus_hook_write_gr(s, 0x21, value);
|
1750 |
break;
|
1751 |
case (CIRRUS_MMIO_BLTHEIGHT + 0): |
1752 |
cirrus_hook_write_gr(s, 0x22, value);
|
1753 |
break;
|
1754 |
case (CIRRUS_MMIO_BLTHEIGHT + 1): |
1755 |
cirrus_hook_write_gr(s, 0x23, value);
|
1756 |
break;
|
1757 |
case (CIRRUS_MMIO_BLTDESTPITCH + 0): |
1758 |
cirrus_hook_write_gr(s, 0x24, value);
|
1759 |
break;
|
1760 |
case (CIRRUS_MMIO_BLTDESTPITCH + 1): |
1761 |
cirrus_hook_write_gr(s, 0x25, value);
|
1762 |
break;
|
1763 |
case (CIRRUS_MMIO_BLTSRCPITCH + 0): |
1764 |
cirrus_hook_write_gr(s, 0x26, value);
|
1765 |
break;
|
1766 |
case (CIRRUS_MMIO_BLTSRCPITCH + 1): |
1767 |
cirrus_hook_write_gr(s, 0x27, value);
|
1768 |
break;
|
1769 |
case (CIRRUS_MMIO_BLTDESTADDR + 0): |
1770 |
cirrus_hook_write_gr(s, 0x28, value);
|
1771 |
break;
|
1772 |
case (CIRRUS_MMIO_BLTDESTADDR + 1): |
1773 |
cirrus_hook_write_gr(s, 0x29, value);
|
1774 |
break;
|
1775 |
case (CIRRUS_MMIO_BLTDESTADDR + 2): |
1776 |
cirrus_hook_write_gr(s, 0x2a, value);
|
1777 |
break;
|
1778 |
case (CIRRUS_MMIO_BLTDESTADDR + 3): |
1779 |
/* ignored */
|
1780 |
break;
|
1781 |
case (CIRRUS_MMIO_BLTSRCADDR + 0): |
1782 |
cirrus_hook_write_gr(s, 0x2c, value);
|
1783 |
break;
|
1784 |
case (CIRRUS_MMIO_BLTSRCADDR + 1): |
1785 |
cirrus_hook_write_gr(s, 0x2d, value);
|
1786 |
break;
|
1787 |
case (CIRRUS_MMIO_BLTSRCADDR + 2): |
1788 |
cirrus_hook_write_gr(s, 0x2e, value);
|
1789 |
break;
|
1790 |
case CIRRUS_MMIO_BLTWRITEMASK:
|
1791 |
cirrus_hook_write_gr(s, 0x2f, value);
|
1792 |
break;
|
1793 |
case CIRRUS_MMIO_BLTMODE:
|
1794 |
cirrus_hook_write_gr(s, 0x30, value);
|
1795 |
break;
|
1796 |
case CIRRUS_MMIO_BLTROP:
|
1797 |
cirrus_hook_write_gr(s, 0x32, value);
|
1798 |
break;
|
1799 |
case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): |
1800 |
cirrus_hook_write_gr(s, 0x34, value);
|
1801 |
break;
|
1802 |
case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): |
1803 |
cirrus_hook_write_gr(s, 0x35, value);
|
1804 |
break;
|
1805 |
case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): |
1806 |
cirrus_hook_write_gr(s, 0x38, value);
|
1807 |
break;
|
1808 |
case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): |
1809 |
cirrus_hook_write_gr(s, 0x39, value);
|
1810 |
break;
|
1811 |
case CIRRUS_MMIO_BLTSTATUS:
|
1812 |
cirrus_hook_write_gr(s, 0x31, value);
|
1813 |
break;
|
1814 |
default:
|
1815 |
#ifdef DEBUG_CIRRUS
|
1816 |
printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
|
1817 |
address, value); |
1818 |
#endif
|
1819 |
break;
|
1820 |
} |
1821 |
} |
1822 |
|
1823 |
/***************************************
|
1824 |
*
|
1825 |
* write mode 4/5
|
1826 |
*
|
1827 |
* assume TARGET_PAGE_SIZE >= 16
|
1828 |
*
|
1829 |
***************************************/
|
1830 |
|
1831 |
static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s, |
1832 |
unsigned mode,
|
1833 |
unsigned offset,
|
1834 |
uint32_t mem_value) |
1835 |
{ |
1836 |
int x;
|
1837 |
unsigned val = mem_value;
|
1838 |
uint8_t *dst; |
1839 |
|
1840 |
dst = s->vram_ptr + offset; |
1841 |
for (x = 0; x < 8; x++) { |
1842 |
if (val & 0x80) { |
1843 |
*dst++ = s->gr[0x01];
|
1844 |
} else if (mode == 5) { |
1845 |
*dst++ = s->gr[0x00];
|
1846 |
} |
1847 |
val <<= 1;
|
1848 |
} |
1849 |
cpu_physical_memory_set_dirty(s->vram_offset + offset); |
1850 |
cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
|
1851 |
} |
1852 |
|
1853 |
static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, |
1854 |
unsigned mode,
|
1855 |
unsigned offset,
|
1856 |
uint32_t mem_value) |
1857 |
{ |
1858 |
int x;
|
1859 |
unsigned val = mem_value;
|
1860 |
uint8_t *dst; |
1861 |
|
1862 |
dst = s->vram_ptr + offset; |
1863 |
for (x = 0; x < 8; x++) { |
1864 |
if (val & 0x80) { |
1865 |
*dst++ = s->gr[0x01];
|
1866 |
*dst++ = s->gr[0x11];
|
1867 |
} else if (mode == 5) { |
1868 |
*dst++ = s->gr[0x00];
|
1869 |
*dst++ = s->gr[0x10];
|
1870 |
} |
1871 |
val <<= 1;
|
1872 |
} |
1873 |
cpu_physical_memory_set_dirty(s->vram_offset + offset); |
1874 |
cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
|
1875 |
} |
1876 |
|
1877 |
/***************************************
|
1878 |
*
|
1879 |
* memory access between 0xa0000-0xbffff
|
1880 |
*
|
1881 |
***************************************/
|
1882 |
|
1883 |
static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr) |
1884 |
{ |
1885 |
CirrusVGAState *s = opaque; |
1886 |
unsigned bank_index;
|
1887 |
unsigned bank_offset;
|
1888 |
uint32_t val; |
1889 |
|
1890 |
if ((s->sr[0x07] & 0x01) == 0) { |
1891 |
return vga_mem_readb(s, addr);
|
1892 |
} |
1893 |
|
1894 |
if (addr < 0x10000) { |
1895 |
/* XXX handle bitblt */
|
1896 |
/* video memory */
|
1897 |
bank_index = addr >> 15;
|
1898 |
bank_offset = addr & 0x7fff;
|
1899 |
if (bank_offset < s->cirrus_bank_limit[bank_index]) {
|
1900 |
bank_offset += s->cirrus_bank_base[bank_index]; |
1901 |
if ((s->gr[0x0B] & 0x14) == 0x14) { |
1902 |
bank_offset <<= 4;
|
1903 |
} else if (s->gr[0x0B] & 0x02) { |
1904 |
bank_offset <<= 3;
|
1905 |
} |
1906 |
bank_offset &= s->cirrus_addr_mask; |
1907 |
val = *(s->vram_ptr + bank_offset); |
1908 |
} else
|
1909 |
val = 0xff;
|
1910 |
} else if (addr >= 0x18000 && addr < 0x18100) { |
1911 |
/* memory-mapped I/O */
|
1912 |
val = 0xff;
|
1913 |
if ((s->sr[0x17] & 0x44) == 0x04) { |
1914 |
val = cirrus_mmio_blt_read(s, addr & 0xff);
|
1915 |
} |
1916 |
} else {
|
1917 |
val = 0xff;
|
1918 |
#ifdef DEBUG_CIRRUS
|
1919 |
printf("cirrus: mem_readb %06x\n", addr);
|
1920 |
#endif
|
1921 |
} |
1922 |
return val;
|
1923 |
} |
1924 |
|
1925 |
static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr) |
1926 |
{ |
1927 |
uint32_t v; |
1928 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1929 |
v = cirrus_vga_mem_readb(opaque, addr) << 8;
|
1930 |
v |= cirrus_vga_mem_readb(opaque, addr + 1);
|
1931 |
#else
|
1932 |
v = cirrus_vga_mem_readb(opaque, addr); |
1933 |
v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8; |
1934 |
#endif
|
1935 |
return v;
|
1936 |
} |
1937 |
|
1938 |
static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr) |
1939 |
{ |
1940 |
uint32_t v; |
1941 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1942 |
v = cirrus_vga_mem_readb(opaque, addr) << 24;
|
1943 |
v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16; |
1944 |
v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8; |
1945 |
v |= cirrus_vga_mem_readb(opaque, addr + 3);
|
1946 |
#else
|
1947 |
v = cirrus_vga_mem_readb(opaque, addr); |
1948 |
v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8; |
1949 |
v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16; |
1950 |
v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24; |
1951 |
#endif
|
1952 |
return v;
|
1953 |
} |
1954 |
|
1955 |
static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr, |
1956 |
uint32_t mem_value) |
1957 |
{ |
1958 |
CirrusVGAState *s = opaque; |
1959 |
unsigned bank_index;
|
1960 |
unsigned bank_offset;
|
1961 |
unsigned mode;
|
1962 |
|
1963 |
if ((s->sr[0x07] & 0x01) == 0) { |
1964 |
vga_mem_writeb(s, addr, mem_value); |
1965 |
return;
|
1966 |
} |
1967 |
|
1968 |
if (addr < 0x10000) { |
1969 |
if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
|
1970 |
/* bitblt */
|
1971 |
*s->cirrus_srcptr++ = (uint8_t) mem_value; |
1972 |
if (s->cirrus_srcptr == s->cirrus_srcptr_end) {
|
1973 |
cirrus_bitblt_cputovideo_next(s); |
1974 |
} |
1975 |
} else {
|
1976 |
/* video memory */
|
1977 |
bank_index = addr >> 15;
|
1978 |
bank_offset = addr & 0x7fff;
|
1979 |
if (bank_offset < s->cirrus_bank_limit[bank_index]) {
|
1980 |
bank_offset += s->cirrus_bank_base[bank_index]; |
1981 |
if ((s->gr[0x0B] & 0x14) == 0x14) { |
1982 |
bank_offset <<= 4;
|
1983 |
} else if (s->gr[0x0B] & 0x02) { |
1984 |
bank_offset <<= 3;
|
1985 |
} |
1986 |
bank_offset &= s->cirrus_addr_mask; |
1987 |
mode = s->gr[0x05] & 0x7; |
1988 |
if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) { |
1989 |
*(s->vram_ptr + bank_offset) = mem_value; |
1990 |
cpu_physical_memory_set_dirty(s->vram_offset + |
1991 |
bank_offset); |
1992 |
} else {
|
1993 |
if ((s->gr[0x0B] & 0x14) != 0x14) { |
1994 |
cirrus_mem_writeb_mode4and5_8bpp(s, mode, |
1995 |
bank_offset, |
1996 |
mem_value); |
1997 |
} else {
|
1998 |
cirrus_mem_writeb_mode4and5_16bpp(s, mode, |
1999 |
bank_offset, |
2000 |
mem_value); |
2001 |
} |
2002 |
} |
2003 |
} |
2004 |
} |
2005 |
} else if (addr >= 0x18000 && addr < 0x18100) { |
2006 |
/* memory-mapped I/O */
|
2007 |
if ((s->sr[0x17] & 0x44) == 0x04) { |
2008 |
cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
|
2009 |
} |
2010 |
} else {
|
2011 |
#ifdef DEBUG_CIRRUS
|
2012 |
printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
|
2013 |
#endif
|
2014 |
} |
2015 |
} |
2016 |
|
2017 |
static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
2018 |
{ |
2019 |
#ifdef TARGET_WORDS_BIGENDIAN
|
2020 |
cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff); |
2021 |
cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff); |
2022 |
#else
|
2023 |
cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
|
2024 |
cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2025 |
#endif
|
2026 |
} |
2027 |
|
2028 |
static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
2029 |
{ |
2030 |
#ifdef TARGET_WORDS_BIGENDIAN
|
2031 |
cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff); |
2032 |
cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
2033 |
cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
2034 |
cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff); |
2035 |
#else
|
2036 |
cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
|
2037 |
cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2038 |
cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2039 |
cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2040 |
#endif
|
2041 |
} |
2042 |
|
2043 |
static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = { |
2044 |
cirrus_vga_mem_readb, |
2045 |
cirrus_vga_mem_readw, |
2046 |
cirrus_vga_mem_readl, |
2047 |
}; |
2048 |
|
2049 |
static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = { |
2050 |
cirrus_vga_mem_writeb, |
2051 |
cirrus_vga_mem_writew, |
2052 |
cirrus_vga_mem_writel, |
2053 |
}; |
2054 |
|
2055 |
/***************************************
|
2056 |
*
|
2057 |
* LFB memory access
|
2058 |
*
|
2059 |
***************************************/
|
2060 |
|
2061 |
static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr) |
2062 |
{ |
2063 |
CirrusVGAState *s = (CirrusVGAState *) opaque; |
2064 |
uint32_t ret; |
2065 |
|
2066 |
/* XXX: s->vram_size must be a power of two */
|
2067 |
addr &= s->cirrus_addr_mask; |
2068 |
|
2069 |
if (((s->sr[0x17] & 0x44) == 0x44) && ((addr & 0x1fff00) == 0x1fff00)) { |
2070 |
/* memory-mapped I/O */
|
2071 |
ret = cirrus_mmio_blt_read(s, addr & 0xff);
|
2072 |
} else if (0) { |
2073 |
/* XXX handle bitblt */
|
2074 |
ret = 0xff;
|
2075 |
} else {
|
2076 |
/* video memory */
|
2077 |
if ((s->gr[0x0B] & 0x14) == 0x14) { |
2078 |
addr <<= 4;
|
2079 |
} else if (s->gr[0x0B] & 0x02) { |
2080 |
addr <<= 3;
|
2081 |
} |
2082 |
addr &= s->cirrus_addr_mask; |
2083 |
ret = *(s->vram_ptr + addr); |
2084 |
} |
2085 |
|
2086 |
return ret;
|
2087 |
} |
2088 |
|
2089 |
static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr) |
2090 |
{ |
2091 |
uint32_t v; |
2092 |
#ifdef TARGET_WORDS_BIGENDIAN
|
2093 |
v = cirrus_linear_readb(opaque, addr) << 8;
|
2094 |
v |= cirrus_linear_readb(opaque, addr + 1);
|
2095 |
#else
|
2096 |
v = cirrus_linear_readb(opaque, addr); |
2097 |
v |= cirrus_linear_readb(opaque, addr + 1) << 8; |
2098 |
#endif
|
2099 |
return v;
|
2100 |
} |
2101 |
|
2102 |
static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr) |
2103 |
{ |
2104 |
uint32_t v; |
2105 |
#ifdef TARGET_WORDS_BIGENDIAN
|
2106 |
v = cirrus_linear_readb(opaque, addr) << 24;
|
2107 |
v |= cirrus_linear_readb(opaque, addr + 1) << 16; |
2108 |
v |= cirrus_linear_readb(opaque, addr + 2) << 8; |
2109 |
v |= cirrus_linear_readb(opaque, addr + 3);
|
2110 |
#else
|
2111 |
v = cirrus_linear_readb(opaque, addr); |
2112 |
v |= cirrus_linear_readb(opaque, addr + 1) << 8; |
2113 |
v |= cirrus_linear_readb(opaque, addr + 2) << 16; |
2114 |
v |= cirrus_linear_readb(opaque, addr + 3) << 24; |
2115 |
#endif
|
2116 |
return v;
|
2117 |
} |
2118 |
|
2119 |
static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr, |
2120 |
uint32_t val) |
2121 |
{ |
2122 |
CirrusVGAState *s = (CirrusVGAState *) opaque; |
2123 |
unsigned mode;
|
2124 |
|
2125 |
addr &= s->cirrus_addr_mask; |
2126 |
|
2127 |
if (((s->sr[0x17] & 0x44) == 0x44) && ((addr & 0x1fff00) == 0x1fff00)) { |
2128 |
/* memory-mapped I/O */
|
2129 |
cirrus_mmio_blt_write(s, addr & 0xff, val);
|
2130 |
} else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { |
2131 |
/* bitblt */
|
2132 |
*s->cirrus_srcptr++ = (uint8_t) val; |
2133 |
if (s->cirrus_srcptr == s->cirrus_srcptr_end) {
|
2134 |
cirrus_bitblt_cputovideo_next(s); |
2135 |
} |
2136 |
} else {
|
2137 |
/* video memory */
|
2138 |
if ((s->gr[0x0B] & 0x14) == 0x14) { |
2139 |
addr <<= 4;
|
2140 |
} else if (s->gr[0x0B] & 0x02) { |
2141 |
addr <<= 3;
|
2142 |
} |
2143 |
addr &= s->cirrus_addr_mask; |
2144 |
|
2145 |
mode = s->gr[0x05] & 0x7; |
2146 |
if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) { |
2147 |
*(s->vram_ptr + addr) = (uint8_t) val; |
2148 |
cpu_physical_memory_set_dirty(s->vram_offset + addr); |
2149 |
} else {
|
2150 |
if ((s->gr[0x0B] & 0x14) != 0x14) { |
2151 |
cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val); |
2152 |
} else {
|
2153 |
cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val); |
2154 |
} |
2155 |
} |
2156 |
} |
2157 |
} |
2158 |
|
2159 |
static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr, |
2160 |
uint32_t val) |
2161 |
{ |
2162 |
#ifdef TARGET_WORDS_BIGENDIAN
|
2163 |
cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff); |
2164 |
cirrus_linear_writeb(opaque, addr + 1, val & 0xff); |
2165 |
#else
|
2166 |
cirrus_linear_writeb(opaque, addr, val & 0xff);
|
2167 |
cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2168 |
#endif
|
2169 |
} |
2170 |
|
2171 |
static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr, |
2172 |
uint32_t val) |
2173 |
{ |
2174 |
#ifdef TARGET_WORDS_BIGENDIAN
|
2175 |
cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff); |
2176 |
cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
2177 |
cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
2178 |
cirrus_linear_writeb(opaque, addr + 3, val & 0xff); |
2179 |
#else
|
2180 |
cirrus_linear_writeb(opaque, addr, val & 0xff);
|
2181 |
cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2182 |
cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2183 |
cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2184 |
#endif
|
2185 |
} |
2186 |
|
2187 |
|
2188 |
static CPUReadMemoryFunc *cirrus_linear_read[3] = { |
2189 |
cirrus_linear_readb, |
2190 |
cirrus_linear_readw, |
2191 |
cirrus_linear_readl, |
2192 |
}; |
2193 |
|
2194 |
static CPUWriteMemoryFunc *cirrus_linear_write[3] = { |
2195 |
cirrus_linear_writeb, |
2196 |
cirrus_linear_writew, |
2197 |
cirrus_linear_writel, |
2198 |
}; |
2199 |
|
2200 |
/* I/O ports */
|
2201 |
|
2202 |
static uint32_t vga_ioport_read(void *opaque, uint32_t addr) |
2203 |
{ |
2204 |
CirrusVGAState *s = opaque; |
2205 |
int val, index;
|
2206 |
|
2207 |
/* check port range access depending on color/monochrome mode */
|
2208 |
if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) |
2209 |
|| (addr >= 0x3d0 && addr <= 0x3df |
2210 |
&& !(s->msr & MSR_COLOR_EMULATION))) { |
2211 |
val = 0xff;
|
2212 |
} else {
|
2213 |
switch (addr) {
|
2214 |
case 0x3c0: |
2215 |
if (s->ar_flip_flop == 0) { |
2216 |
val = s->ar_index; |
2217 |
} else {
|
2218 |
val = 0;
|
2219 |
} |
2220 |
break;
|
2221 |
case 0x3c1: |
2222 |
index = s->ar_index & 0x1f;
|
2223 |
if (index < 21) |
2224 |
val = s->ar[index]; |
2225 |
else
|
2226 |
val = 0;
|
2227 |
break;
|
2228 |
case 0x3c2: |
2229 |
val = s->st00; |
2230 |
break;
|
2231 |
case 0x3c4: |
2232 |
val = s->sr_index; |
2233 |
break;
|
2234 |
case 0x3c5: |
2235 |
if (cirrus_hook_read_sr(s, s->sr_index, &val))
|
2236 |
break;
|
2237 |
val = s->sr[s->sr_index]; |
2238 |
#ifdef DEBUG_VGA_REG
|
2239 |
printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
|
2240 |
#endif
|
2241 |
break;
|
2242 |
case 0x3c6: |
2243 |
cirrus_read_hidden_dac(s, &val); |
2244 |
break;
|
2245 |
case 0x3c7: |
2246 |
val = s->dac_state; |
2247 |
break;
|
2248 |
case 0x3c9: |
2249 |
if (cirrus_hook_read_palette(s, &val))
|
2250 |
break;
|
2251 |
val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
|
2252 |
if (++s->dac_sub_index == 3) { |
2253 |
s->dac_sub_index = 0;
|
2254 |
s->dac_read_index++; |
2255 |
} |
2256 |
break;
|
2257 |
case 0x3ca: |
2258 |
val = s->fcr; |
2259 |
break;
|
2260 |
case 0x3cc: |
2261 |
val = s->msr; |
2262 |
break;
|
2263 |
case 0x3ce: |
2264 |
val = s->gr_index; |
2265 |
break;
|
2266 |
case 0x3cf: |
2267 |
if (cirrus_hook_read_gr(s, s->gr_index, &val))
|
2268 |
break;
|
2269 |
val = s->gr[s->gr_index]; |
2270 |
#ifdef DEBUG_VGA_REG
|
2271 |
printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
|
2272 |
#endif
|
2273 |
break;
|
2274 |
case 0x3b4: |
2275 |
case 0x3d4: |
2276 |
val = s->cr_index; |
2277 |
break;
|
2278 |
case 0x3b5: |
2279 |
case 0x3d5: |
2280 |
if (cirrus_hook_read_cr(s, s->cr_index, &val))
|
2281 |
break;
|
2282 |
val = s->cr[s->cr_index]; |
2283 |
#ifdef DEBUG_VGA_REG
|
2284 |
printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
|
2285 |
#endif
|
2286 |
#ifdef DEBUG_S3
|
2287 |
if (s->cr_index >= 0x20) |
2288 |
printf("S3: CR read index=0x%x val=0x%x\n",
|
2289 |
s->cr_index, val); |
2290 |
#endif
|
2291 |
break;
|
2292 |
case 0x3ba: |
2293 |
case 0x3da: |
2294 |
/* just toggle to fool polling */
|
2295 |
s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE; |
2296 |
val = s->st01; |
2297 |
s->ar_flip_flop = 0;
|
2298 |
break;
|
2299 |
default:
|
2300 |
val = 0x00;
|
2301 |
break;
|
2302 |
} |
2303 |
} |
2304 |
#if defined(DEBUG_VGA)
|
2305 |
printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
|
2306 |
#endif
|
2307 |
return val;
|
2308 |
} |
2309 |
|
2310 |
static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
2311 |
{ |
2312 |
CirrusVGAState *s = opaque; |
2313 |
int index;
|
2314 |
|
2315 |
/* check port range access depending on color/monochrome mode */
|
2316 |
if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) |
2317 |
|| (addr >= 0x3d0 && addr <= 0x3df |
2318 |
&& !(s->msr & MSR_COLOR_EMULATION))) |
2319 |
return;
|
2320 |
|
2321 |
#ifdef DEBUG_VGA
|
2322 |
printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
|
2323 |
#endif
|
2324 |
|
2325 |
switch (addr) {
|
2326 |
case 0x3c0: |
2327 |
if (s->ar_flip_flop == 0) { |
2328 |
val &= 0x3f;
|
2329 |
s->ar_index = val; |
2330 |
} else {
|
2331 |
index = s->ar_index & 0x1f;
|
2332 |
switch (index) {
|
2333 |
case 0x00 ... 0x0f: |
2334 |
s->ar[index] = val & 0x3f;
|
2335 |
break;
|
2336 |
case 0x10: |
2337 |
s->ar[index] = val & ~0x10;
|
2338 |
break;
|
2339 |
case 0x11: |
2340 |
s->ar[index] = val; |
2341 |
break;
|
2342 |
case 0x12: |
2343 |
s->ar[index] = val & ~0xc0;
|
2344 |
break;
|
2345 |
case 0x13: |
2346 |
s->ar[index] = val & ~0xf0;
|
2347 |
break;
|
2348 |
case 0x14: |
2349 |
s->ar[index] = val & ~0xf0;
|
2350 |
break;
|
2351 |
default:
|
2352 |
break;
|
2353 |
} |
2354 |
} |
2355 |
s->ar_flip_flop ^= 1;
|
2356 |
break;
|
2357 |
case 0x3c2: |
2358 |
s->msr = val & ~0x10;
|
2359 |
break;
|
2360 |
case 0x3c4: |
2361 |
s->sr_index = val; |
2362 |
break;
|
2363 |
case 0x3c5: |
2364 |
if (cirrus_hook_write_sr(s, s->sr_index, val))
|
2365 |
break;
|
2366 |
#ifdef DEBUG_VGA_REG
|
2367 |
printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
|
2368 |
#endif
|
2369 |
s->sr[s->sr_index] = val & sr_mask[s->sr_index]; |
2370 |
break;
|
2371 |
case 0x3c6: |
2372 |
cirrus_write_hidden_dac(s, val); |
2373 |
break;
|
2374 |
case 0x3c7: |
2375 |
s->dac_read_index = val; |
2376 |
s->dac_sub_index = 0;
|
2377 |
s->dac_state = 3;
|
2378 |
break;
|
2379 |
case 0x3c8: |
2380 |
s->dac_write_index = val; |
2381 |
s->dac_sub_index = 0;
|
2382 |
s->dac_state = 0;
|
2383 |
break;
|
2384 |
case 0x3c9: |
2385 |
if (cirrus_hook_write_palette(s, val))
|
2386 |
break;
|
2387 |
s->dac_cache[s->dac_sub_index] = val; |
2388 |
if (++s->dac_sub_index == 3) { |
2389 |
memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3); |
2390 |
s->dac_sub_index = 0;
|
2391 |
s->dac_write_index++; |
2392 |
} |
2393 |
break;
|
2394 |
case 0x3ce: |
2395 |
s->gr_index = val; |
2396 |
break;
|
2397 |
case 0x3cf: |
2398 |
if (cirrus_hook_write_gr(s, s->gr_index, val))
|
2399 |
break;
|
2400 |
#ifdef DEBUG_VGA_REG
|
2401 |
printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
|
2402 |
#endif
|
2403 |
s->gr[s->gr_index] = val & gr_mask[s->gr_index]; |
2404 |
break;
|
2405 |
case 0x3b4: |
2406 |
case 0x3d4: |
2407 |
s->cr_index = val; |
2408 |
break;
|
2409 |
case 0x3b5: |
2410 |
case 0x3d5: |
2411 |
if (cirrus_hook_write_cr(s, s->cr_index, val))
|
2412 |
break;
|
2413 |
#ifdef DEBUG_VGA_REG
|
2414 |
printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
|
2415 |
#endif
|
2416 |
/* handle CR0-7 protection */
|
2417 |
if ((s->cr[11] & 0x80) && s->cr_index <= 7) { |
2418 |
/* can always write bit 4 of CR7 */
|
2419 |
if (s->cr_index == 7) |
2420 |
s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10); |
2421 |
return;
|
2422 |
} |
2423 |
switch (s->cr_index) {
|
2424 |
case 0x01: /* horizontal display end */ |
2425 |
case 0x07: |
2426 |
case 0x09: |
2427 |
case 0x0c: |
2428 |
case 0x0d: |
2429 |
case 0x12: /* veritcal display end */ |
2430 |
s->cr[s->cr_index] = val; |
2431 |
break;
|
2432 |
|
2433 |
default:
|
2434 |
s->cr[s->cr_index] = val; |
2435 |
break;
|
2436 |
} |
2437 |
break;
|
2438 |
case 0x3ba: |
2439 |
case 0x3da: |
2440 |
s->fcr = val & 0x10;
|
2441 |
break;
|
2442 |
} |
2443 |
} |
2444 |
|
2445 |
/***************************************
|
2446 |
*
|
2447 |
* memory-mapped I/O access
|
2448 |
*
|
2449 |
***************************************/
|
2450 |
|
2451 |
static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr) |
2452 |
{ |
2453 |
CirrusVGAState *s = (CirrusVGAState *) opaque; |
2454 |
|
2455 |
addr &= CIRRUS_PNPMMIO_SIZE - 1;
|
2456 |
|
2457 |
if (addr >= 0x100) { |
2458 |
return cirrus_mmio_blt_read(s, addr - 0x100); |
2459 |
} else {
|
2460 |
return vga_ioport_read(s, addr + 0x3c0); |
2461 |
} |
2462 |
} |
2463 |
|
2464 |
static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr) |
2465 |
{ |
2466 |
uint32_t v; |
2467 |
#ifdef TARGET_WORDS_BIGENDIAN
|
2468 |
v = cirrus_mmio_readb(opaque, addr) << 8;
|
2469 |
v |= cirrus_mmio_readb(opaque, addr + 1);
|
2470 |
#else
|
2471 |
v = cirrus_mmio_readb(opaque, addr); |
2472 |
v |= cirrus_mmio_readb(opaque, addr + 1) << 8; |
2473 |
#endif
|
2474 |
return v;
|
2475 |
} |
2476 |
|
2477 |
static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr) |
2478 |
{ |
2479 |
uint32_t v; |
2480 |
#ifdef TARGET_WORDS_BIGENDIAN
|
2481 |
v = cirrus_mmio_readb(opaque, addr) << 24;
|
2482 |
v |= cirrus_mmio_readb(opaque, addr + 1) << 16; |
2483 |
v |= cirrus_mmio_readb(opaque, addr + 2) << 8; |
2484 |
v |= cirrus_mmio_readb(opaque, addr + 3);
|
2485 |
#else
|
2486 |
v = cirrus_mmio_readb(opaque, addr); |
2487 |
v |= cirrus_mmio_readb(opaque, addr + 1) << 8; |
2488 |
v |= cirrus_mmio_readb(opaque, addr + 2) << 16; |
2489 |
v |= cirrus_mmio_readb(opaque, addr + 3) << 24; |
2490 |
#endif
|
2491 |
return v;
|
2492 |
} |
2493 |
|
2494 |
static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr, |
2495 |
uint32_t val) |
2496 |
{ |
2497 |
CirrusVGAState *s = (CirrusVGAState *) opaque; |
2498 |
|
2499 |
addr &= CIRRUS_PNPMMIO_SIZE - 1;
|
2500 |
|
2501 |
if (addr >= 0x100) { |
2502 |
cirrus_mmio_blt_write(s, addr - 0x100, val);
|
2503 |
} else {
|
2504 |
vga_ioport_write(s, addr + 0x3c0, val);
|
2505 |
} |
2506 |
} |
2507 |
|
2508 |
static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr, |
2509 |
uint32_t val) |
2510 |
{ |
2511 |
#ifdef TARGET_WORDS_BIGENDIAN
|
2512 |
cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff); |
2513 |
cirrus_mmio_writeb(opaque, addr + 1, val & 0xff); |
2514 |
#else
|
2515 |
cirrus_mmio_writeb(opaque, addr, val & 0xff);
|
2516 |
cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2517 |
#endif
|
2518 |
} |
2519 |
|
2520 |
static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr, |
2521 |
uint32_t val) |
2522 |
{ |
2523 |
#ifdef TARGET_WORDS_BIGENDIAN
|
2524 |
cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff); |
2525 |
cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
2526 |
cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
2527 |
cirrus_mmio_writeb(opaque, addr + 3, val & 0xff); |
2528 |
#else
|
2529 |
cirrus_mmio_writeb(opaque, addr, val & 0xff);
|
2530 |
cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2531 |
cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2532 |
cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2533 |
#endif
|
2534 |
} |
2535 |
|
2536 |
|
2537 |
static CPUReadMemoryFunc *cirrus_mmio_read[3] = { |
2538 |
cirrus_mmio_readb, |
2539 |
cirrus_mmio_readw, |
2540 |
cirrus_mmio_readl, |
2541 |
}; |
2542 |
|
2543 |
static CPUWriteMemoryFunc *cirrus_mmio_write[3] = { |
2544 |
cirrus_mmio_writeb, |
2545 |
cirrus_mmio_writew, |
2546 |
cirrus_mmio_writel, |
2547 |
}; |
2548 |
|
2549 |
/***************************************
|
2550 |
*
|
2551 |
* initialize
|
2552 |
*
|
2553 |
***************************************/
|
2554 |
|
2555 |
static void cirrus_init_common(CirrusVGAState * s) |
2556 |
{ |
2557 |
int vga_io_memory;
|
2558 |
|
2559 |
register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s); |
2560 |
|
2561 |
register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s); |
2562 |
register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s); |
2563 |
register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s); |
2564 |
register_ioport_write(0x3da, 1, 1, vga_ioport_write, s); |
2565 |
|
2566 |
register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s); |
2567 |
|
2568 |
register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s); |
2569 |
register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s); |
2570 |
register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s); |
2571 |
register_ioport_read(0x3da, 1, 1, vga_ioport_read, s); |
2572 |
|
2573 |
vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
|
2574 |
cirrus_vga_mem_write, s); |
2575 |
cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000, |
2576 |
vga_io_memory); |
2577 |
|
2578 |
s->sr[0x06] = 0x0f; |
2579 |
s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
|
2580 |
s->sr[0x1F] = 0x22; // MemClock |
2581 |
|
2582 |
s->cr[0x27] = CIRRUS_ID_CLGD5430;
|
2583 |
|
2584 |
s->cirrus_hidden_dac_lockindex = 5;
|
2585 |
s->cirrus_hidden_dac_data = 0;
|
2586 |
|
2587 |
/* I/O handler for LFB */
|
2588 |
s->cirrus_linear_io_addr = |
2589 |
cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
|
2590 |
s); |
2591 |
/* I/O handler for memory-mapped I/O */
|
2592 |
s->cirrus_mmio_io_addr = |
2593 |
cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
|
2594 |
|
2595 |
/* XXX: s->vram_size must be a power of two */
|
2596 |
s->cirrus_addr_mask = s->vram_size - 1;
|
2597 |
|
2598 |
s->get_bpp = cirrus_get_bpp; |
2599 |
s->get_offsets = cirrus_get_offsets; |
2600 |
} |
2601 |
|
2602 |
/***************************************
|
2603 |
*
|
2604 |
* ISA bus support
|
2605 |
*
|
2606 |
***************************************/
|
2607 |
|
2608 |
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
2609 |
unsigned long vga_ram_offset, int vga_ram_size) |
2610 |
{ |
2611 |
CirrusVGAState *s; |
2612 |
|
2613 |
s = qemu_mallocz(sizeof(CirrusVGAState));
|
2614 |
|
2615 |
vga_common_init((VGAState *)s, |
2616 |
ds, vga_ram_base, vga_ram_offset, vga_ram_size); |
2617 |
cirrus_init_common(s); |
2618 |
s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
|
2619 |
/* XXX ISA-LFB support */
|
2620 |
} |
2621 |
|
2622 |
/***************************************
|
2623 |
*
|
2624 |
* PCI bus support
|
2625 |
*
|
2626 |
***************************************/
|
2627 |
|
2628 |
static void cirrus_pci_lfb_map(PCIDevice *d, int region_num, |
2629 |
uint32_t addr, uint32_t size, int type)
|
2630 |
{ |
2631 |
CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga; |
2632 |
|
2633 |
cpu_register_physical_memory(addr, s->vram_size, |
2634 |
s->cirrus_linear_io_addr); |
2635 |
} |
2636 |
|
2637 |
static void cirrus_pci_mmio_map(PCIDevice *d, int region_num, |
2638 |
uint32_t addr, uint32_t size, int type)
|
2639 |
{ |
2640 |
CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga; |
2641 |
|
2642 |
cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE, |
2643 |
s->cirrus_mmio_io_addr); |
2644 |
} |
2645 |
|
2646 |
void pci_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
2647 |
unsigned long vga_ram_offset, int vga_ram_size) |
2648 |
{ |
2649 |
PCICirrusVGAState *d; |
2650 |
uint8_t *pci_conf; |
2651 |
CirrusVGAState *s; |
2652 |
|
2653 |
/* setup PCI configuration registers */
|
2654 |
d = (PCICirrusVGAState *)pci_register_device("Cirrus VGA",
|
2655 |
sizeof(PCICirrusVGAState),
|
2656 |
0, -1, NULL, NULL); |
2657 |
pci_conf = d->dev.config; |
2658 |
pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff); |
2659 |
pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8); |
2660 |
pci_conf[0x02] = (uint8_t) (PCI_DEVICE_CLGD5430 & 0xff); |
2661 |
pci_conf[0x03] = (uint8_t) (PCI_DEVICE_CLGD5430 >> 8); |
2662 |
pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
|
2663 |
pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
|
2664 |
pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
|
2665 |
pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
|
2666 |
|
2667 |
/* setup VGA */
|
2668 |
s = &d->cirrus_vga; |
2669 |
vga_common_init((VGAState *)s, |
2670 |
ds, vga_ram_base, vga_ram_offset, vga_ram_size); |
2671 |
cirrus_init_common(s); |
2672 |
s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
|
2673 |
|
2674 |
/* setup memory space */
|
2675 |
/* memory #0 LFB */
|
2676 |
/* memory #1 memory-mapped I/O */
|
2677 |
/* XXX: s->vram_size must be a power of two */
|
2678 |
pci_register_io_region((PCIDevice *)d, 0, s->vram_size,
|
2679 |
PCI_ADDRESS_SPACE_MEM, cirrus_pci_lfb_map); |
2680 |
pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
|
2681 |
PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map); |
2682 |
/* XXX: ROM BIOS */
|
2683 |
} |