root / hw / mcf5208.c @ 4e4fa398
History | View | Annotate | Download (8.2 kB)
1 | 5fafdf24 | ths | /*
|
---|---|---|---|
2 | 20dcee94 | pbrook | * Motorola ColdFire MCF5208 SoC emulation.
|
3 | 20dcee94 | pbrook | *
|
4 | 20dcee94 | pbrook | * Copyright (c) 2007 CodeSourcery.
|
5 | 20dcee94 | pbrook | *
|
6 | 8e31bf38 | Matthew Fernandez | * This code is licensed under the GPL
|
7 | 20dcee94 | pbrook | */
|
8 | 87ecb68b | pbrook | #include "hw.h" |
9 | 87ecb68b | pbrook | #include "mcf.h" |
10 | 87ecb68b | pbrook | #include "qemu-timer.h" |
11 | 49d4d9b6 | Paolo Bonzini | #include "ptimer.h" |
12 | 87ecb68b | pbrook | #include "sysemu.h" |
13 | 87ecb68b | pbrook | #include "net.h" |
14 | 87ecb68b | pbrook | #include "boards.h" |
15 | ca20cf32 | Blue Swirl | #include "loader.h" |
16 | ca20cf32 | Blue Swirl | #include "elf.h" |
17 | c378b364 | Avi Kivity | #include "exec-memory.h" |
18 | 20dcee94 | pbrook | |
19 | 20dcee94 | pbrook | #define SYS_FREQ 66000000 |
20 | 20dcee94 | pbrook | |
21 | 20dcee94 | pbrook | #define PCSR_EN 0x0001 |
22 | 20dcee94 | pbrook | #define PCSR_RLD 0x0002 |
23 | 20dcee94 | pbrook | #define PCSR_PIF 0x0004 |
24 | 20dcee94 | pbrook | #define PCSR_PIE 0x0008 |
25 | 20dcee94 | pbrook | #define PCSR_OVW 0x0010 |
26 | 20dcee94 | pbrook | #define PCSR_DBG 0x0020 |
27 | 20dcee94 | pbrook | #define PCSR_DOZE 0x0040 |
28 | 20dcee94 | pbrook | #define PCSR_PRE_SHIFT 8 |
29 | 20dcee94 | pbrook | #define PCSR_PRE_MASK 0x0f00 |
30 | 20dcee94 | pbrook | |
31 | 20dcee94 | pbrook | typedef struct { |
32 | c378b364 | Avi Kivity | MemoryRegion iomem; |
33 | 20dcee94 | pbrook | qemu_irq irq; |
34 | 20dcee94 | pbrook | ptimer_state *timer; |
35 | 20dcee94 | pbrook | uint16_t pcsr; |
36 | 20dcee94 | pbrook | uint16_t pmr; |
37 | 20dcee94 | pbrook | uint16_t pcntr; |
38 | 20dcee94 | pbrook | } m5208_timer_state; |
39 | 20dcee94 | pbrook | |
40 | 20dcee94 | pbrook | static void m5208_timer_update(m5208_timer_state *s) |
41 | 20dcee94 | pbrook | { |
42 | 20dcee94 | pbrook | if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF))
|
43 | 20dcee94 | pbrook | qemu_irq_raise(s->irq); |
44 | 20dcee94 | pbrook | else
|
45 | 20dcee94 | pbrook | qemu_irq_lower(s->irq); |
46 | 20dcee94 | pbrook | } |
47 | 20dcee94 | pbrook | |
48 | c227f099 | Anthony Liguori | static void m5208_timer_write(void *opaque, target_phys_addr_t offset, |
49 | c378b364 | Avi Kivity | uint64_t value, unsigned size)
|
50 | 20dcee94 | pbrook | { |
51 | 8da3ff18 | pbrook | m5208_timer_state *s = (m5208_timer_state *)opaque; |
52 | 20dcee94 | pbrook | int prescale;
|
53 | 20dcee94 | pbrook | int limit;
|
54 | 20dcee94 | pbrook | switch (offset) {
|
55 | 20dcee94 | pbrook | case 0: |
56 | 20dcee94 | pbrook | /* The PIF bit is set-to-clear. */
|
57 | 20dcee94 | pbrook | if (value & PCSR_PIF) {
|
58 | 20dcee94 | pbrook | s->pcsr &= ~PCSR_PIF; |
59 | 20dcee94 | pbrook | value &= ~PCSR_PIF; |
60 | 20dcee94 | pbrook | } |
61 | 20dcee94 | pbrook | /* Avoid frobbing the timer if we're just twiddling IRQ bits. */
|
62 | 20dcee94 | pbrook | if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) { |
63 | 20dcee94 | pbrook | s->pcsr = value; |
64 | 20dcee94 | pbrook | m5208_timer_update(s); |
65 | 20dcee94 | pbrook | return;
|
66 | 20dcee94 | pbrook | } |
67 | 20dcee94 | pbrook | |
68 | 20dcee94 | pbrook | if (s->pcsr & PCSR_EN)
|
69 | 20dcee94 | pbrook | ptimer_stop(s->timer); |
70 | 20dcee94 | pbrook | |
71 | 20dcee94 | pbrook | s->pcsr = value; |
72 | 20dcee94 | pbrook | |
73 | 20dcee94 | pbrook | prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
|
74 | 20dcee94 | pbrook | ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
|
75 | 20dcee94 | pbrook | if (s->pcsr & PCSR_RLD)
|
76 | 20dcee94 | pbrook | limit = s->pmr; |
77 | 6d9db39c | pbrook | else
|
78 | 6d9db39c | pbrook | limit = 0xffff;
|
79 | 20dcee94 | pbrook | ptimer_set_limit(s->timer, limit, 0);
|
80 | 20dcee94 | pbrook | |
81 | 20dcee94 | pbrook | if (s->pcsr & PCSR_EN)
|
82 | 20dcee94 | pbrook | ptimer_run(s->timer, 0);
|
83 | 20dcee94 | pbrook | break;
|
84 | 20dcee94 | pbrook | case 2: |
85 | 20dcee94 | pbrook | s->pmr = value; |
86 | 20dcee94 | pbrook | s->pcsr &= ~PCSR_PIF; |
87 | 6d9db39c | pbrook | if ((s->pcsr & PCSR_RLD) == 0) { |
88 | 6d9db39c | pbrook | if (s->pcsr & PCSR_OVW)
|
89 | 6d9db39c | pbrook | ptimer_set_count(s->timer, value); |
90 | 6d9db39c | pbrook | } else {
|
91 | 6d9db39c | pbrook | ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW); |
92 | 6d9db39c | pbrook | } |
93 | 20dcee94 | pbrook | break;
|
94 | 20dcee94 | pbrook | case 4: |
95 | 20dcee94 | pbrook | break;
|
96 | 20dcee94 | pbrook | default:
|
97 | 2ac71179 | Paul Brook | hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset); |
98 | 8da3ff18 | pbrook | break;
|
99 | 20dcee94 | pbrook | } |
100 | 20dcee94 | pbrook | m5208_timer_update(s); |
101 | 20dcee94 | pbrook | } |
102 | 20dcee94 | pbrook | |
103 | 20dcee94 | pbrook | static void m5208_timer_trigger(void *opaque) |
104 | 20dcee94 | pbrook | { |
105 | 20dcee94 | pbrook | m5208_timer_state *s = (m5208_timer_state *)opaque; |
106 | 20dcee94 | pbrook | s->pcsr |= PCSR_PIF; |
107 | 20dcee94 | pbrook | m5208_timer_update(s); |
108 | 20dcee94 | pbrook | } |
109 | 20dcee94 | pbrook | |
110 | c378b364 | Avi Kivity | static uint64_t m5208_timer_read(void *opaque, target_phys_addr_t addr, |
111 | c378b364 | Avi Kivity | unsigned size)
|
112 | 8da3ff18 | pbrook | { |
113 | 8da3ff18 | pbrook | m5208_timer_state *s = (m5208_timer_state *)opaque; |
114 | 8da3ff18 | pbrook | switch (addr) {
|
115 | 8da3ff18 | pbrook | case 0: |
116 | 8da3ff18 | pbrook | return s->pcsr;
|
117 | 8da3ff18 | pbrook | case 2: |
118 | 8da3ff18 | pbrook | return s->pmr;
|
119 | 8da3ff18 | pbrook | case 4: |
120 | 8da3ff18 | pbrook | return ptimer_get_count(s->timer);
|
121 | 8da3ff18 | pbrook | default:
|
122 | 2ac71179 | Paul Brook | hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr); |
123 | 8da3ff18 | pbrook | return 0; |
124 | 8da3ff18 | pbrook | } |
125 | 8da3ff18 | pbrook | } |
126 | 8da3ff18 | pbrook | |
127 | c378b364 | Avi Kivity | static const MemoryRegionOps m5208_timer_ops = { |
128 | c378b364 | Avi Kivity | .read = m5208_timer_read, |
129 | c378b364 | Avi Kivity | .write = m5208_timer_write, |
130 | c378b364 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
131 | 8da3ff18 | pbrook | }; |
132 | 8da3ff18 | pbrook | |
133 | c378b364 | Avi Kivity | static uint64_t m5208_sys_read(void *opaque, target_phys_addr_t addr, |
134 | c378b364 | Avi Kivity | unsigned size)
|
135 | 20dcee94 | pbrook | { |
136 | 20dcee94 | pbrook | switch (addr) {
|
137 | 8da3ff18 | pbrook | case 0x110: /* SDCS0 */ |
138 | 20dcee94 | pbrook | { |
139 | 20dcee94 | pbrook | int n;
|
140 | 20dcee94 | pbrook | for (n = 0; n < 32; n++) { |
141 | 20dcee94 | pbrook | if (ram_size < (2u << n)) |
142 | 20dcee94 | pbrook | break;
|
143 | 20dcee94 | pbrook | } |
144 | 20dcee94 | pbrook | return (n - 1) | 0x40000000; |
145 | 20dcee94 | pbrook | } |
146 | 8da3ff18 | pbrook | case 0x114: /* SDCS1 */ |
147 | 20dcee94 | pbrook | return 0; |
148 | 20dcee94 | pbrook | |
149 | 20dcee94 | pbrook | default:
|
150 | 2ac71179 | Paul Brook | hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr); |
151 | 20dcee94 | pbrook | return 0; |
152 | 20dcee94 | pbrook | } |
153 | 20dcee94 | pbrook | } |
154 | 20dcee94 | pbrook | |
155 | c227f099 | Anthony Liguori | static void m5208_sys_write(void *opaque, target_phys_addr_t addr, |
156 | c378b364 | Avi Kivity | uint64_t value, unsigned size)
|
157 | 20dcee94 | pbrook | { |
158 | 2ac71179 | Paul Brook | hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr); |
159 | 20dcee94 | pbrook | } |
160 | 20dcee94 | pbrook | |
161 | c378b364 | Avi Kivity | static const MemoryRegionOps m5208_sys_ops = { |
162 | c378b364 | Avi Kivity | .read = m5208_sys_read, |
163 | c378b364 | Avi Kivity | .write = m5208_sys_write, |
164 | c378b364 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
165 | 20dcee94 | pbrook | }; |
166 | 20dcee94 | pbrook | |
167 | c378b364 | Avi Kivity | static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic) |
168 | 20dcee94 | pbrook | { |
169 | c378b364 | Avi Kivity | MemoryRegion *iomem = g_new(MemoryRegion, 1);
|
170 | 8da3ff18 | pbrook | m5208_timer_state *s; |
171 | 20dcee94 | pbrook | QEMUBH *bh; |
172 | 20dcee94 | pbrook | int i;
|
173 | 20dcee94 | pbrook | |
174 | 20dcee94 | pbrook | /* SDRAMC. */
|
175 | c378b364 | Avi Kivity | memory_region_init_io(iomem, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000); |
176 | c378b364 | Avi Kivity | memory_region_add_subregion(address_space, 0xfc0a8000, iomem);
|
177 | 20dcee94 | pbrook | /* Timers. */
|
178 | 20dcee94 | pbrook | for (i = 0; i < 2; i++) { |
179 | 7267c094 | Anthony Liguori | s = (m5208_timer_state *)g_malloc0(sizeof(m5208_timer_state));
|
180 | 8da3ff18 | pbrook | bh = qemu_bh_new(m5208_timer_trigger, s); |
181 | 8da3ff18 | pbrook | s->timer = ptimer_init(bh); |
182 | c378b364 | Avi Kivity | memory_region_init_io(&s->iomem, &m5208_timer_ops, s, |
183 | c378b364 | Avi Kivity | "m5208-timer", 0x00004000); |
184 | c378b364 | Avi Kivity | memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i, |
185 | c378b364 | Avi Kivity | &s->iomem); |
186 | 8da3ff18 | pbrook | s->irq = pic[4 + i];
|
187 | 20dcee94 | pbrook | } |
188 | 20dcee94 | pbrook | } |
189 | 20dcee94 | pbrook | |
190 | c227f099 | Anthony Liguori | static void mcf5208evb_init(ram_addr_t ram_size, |
191 | 3023f332 | aliguori | const char *boot_device, |
192 | 20dcee94 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
193 | 20dcee94 | pbrook | const char *initrd_filename, const char *cpu_model) |
194 | 20dcee94 | pbrook | { |
195 | 20dcee94 | pbrook | CPUState *env; |
196 | 20dcee94 | pbrook | int kernel_size;
|
197 | 20dcee94 | pbrook | uint64_t elf_entry; |
198 | c227f099 | Anthony Liguori | target_phys_addr_t entry; |
199 | 20dcee94 | pbrook | qemu_irq *pic; |
200 | c378b364 | Avi Kivity | MemoryRegion *address_space_mem = get_system_memory(); |
201 | c378b364 | Avi Kivity | MemoryRegion *ram = g_new(MemoryRegion, 1);
|
202 | c378b364 | Avi Kivity | MemoryRegion *sram = g_new(MemoryRegion, 1);
|
203 | 20dcee94 | pbrook | |
204 | 20dcee94 | pbrook | if (!cpu_model)
|
205 | 20dcee94 | pbrook | cpu_model = "m5208";
|
206 | aaed909a | bellard | env = cpu_init(cpu_model); |
207 | aaed909a | bellard | if (!env) {
|
208 | aaed909a | bellard | fprintf(stderr, "Unable to find m68k CPU definition\n");
|
209 | aaed909a | bellard | exit(1);
|
210 | 20dcee94 | pbrook | } |
211 | 20dcee94 | pbrook | |
212 | 20dcee94 | pbrook | /* Initialize CPU registers. */
|
213 | 20dcee94 | pbrook | env->vbr = 0;
|
214 | 20dcee94 | pbrook | /* TODO: Configure BARs. */
|
215 | 20dcee94 | pbrook | |
216 | dcac9679 | pbrook | /* DRAM at 0x40000000 */
|
217 | c5705a77 | Avi Kivity | memory_region_init_ram(ram, "mcf5208.ram", ram_size);
|
218 | c5705a77 | Avi Kivity | vmstate_register_ram_global(ram); |
219 | c378b364 | Avi Kivity | memory_region_add_subregion(address_space_mem, 0x40000000, ram);
|
220 | 20dcee94 | pbrook | |
221 | 20dcee94 | pbrook | /* Internal SRAM. */
|
222 | c5705a77 | Avi Kivity | memory_region_init_ram(sram, "mcf5208.sram", 16384); |
223 | c5705a77 | Avi Kivity | vmstate_register_ram_global(sram); |
224 | c378b364 | Avi Kivity | memory_region_add_subregion(address_space_mem, 0x80000000, sram);
|
225 | 20dcee94 | pbrook | |
226 | 20dcee94 | pbrook | /* Internal peripherals. */
|
227 | 663d9446 | Benoît Canet | pic = mcf_intc_init(address_space_mem, 0xfc048000, env);
|
228 | 20dcee94 | pbrook | |
229 | aa6e4986 | Benoît Canet | mcf_uart_mm_init(address_space_mem, 0xfc060000, pic[26], serial_hds[0]); |
230 | aa6e4986 | Benoît Canet | mcf_uart_mm_init(address_space_mem, 0xfc064000, pic[27], serial_hds[1]); |
231 | aa6e4986 | Benoît Canet | mcf_uart_mm_init(address_space_mem, 0xfc068000, pic[28], serial_hds[2]); |
232 | 20dcee94 | pbrook | |
233 | c378b364 | Avi Kivity | mcf5208_sys_init(address_space_mem, pic); |
234 | 20dcee94 | pbrook | |
235 | 7e049b8a | pbrook | if (nb_nics > 1) { |
236 | 7e049b8a | pbrook | fprintf(stderr, "Too many NICs\n");
|
237 | 7e049b8a | pbrook | exit(1);
|
238 | 7e049b8a | pbrook | } |
239 | 0ae18cee | aliguori | if (nd_table[0].vlan) |
240 | c65fc1df | Benoît Canet | mcf_fec_init(address_space_mem, &nd_table[0],
|
241 | c65fc1df | Benoît Canet | 0xfc030000, pic + 36); |
242 | 7e049b8a | pbrook | |
243 | 20dcee94 | pbrook | /* 0xfc000000 SCM. */
|
244 | 20dcee94 | pbrook | /* 0xfc004000 XBS. */
|
245 | 20dcee94 | pbrook | /* 0xfc008000 FlexBus CS. */
|
246 | 7e049b8a | pbrook | /* 0xfc030000 FEC. */
|
247 | 20dcee94 | pbrook | /* 0xfc040000 SCM + Power management. */
|
248 | 20dcee94 | pbrook | /* 0xfc044000 eDMA. */
|
249 | 20dcee94 | pbrook | /* 0xfc048000 INTC. */
|
250 | 20dcee94 | pbrook | /* 0xfc058000 I2C. */
|
251 | 20dcee94 | pbrook | /* 0xfc05c000 QSPI. */
|
252 | 20dcee94 | pbrook | /* 0xfc060000 UART0. */
|
253 | 20dcee94 | pbrook | /* 0xfc064000 UART0. */
|
254 | 20dcee94 | pbrook | /* 0xfc068000 UART0. */
|
255 | 20dcee94 | pbrook | /* 0xfc070000 DMA timers. */
|
256 | 20dcee94 | pbrook | /* 0xfc080000 PIT0. */
|
257 | 20dcee94 | pbrook | /* 0xfc084000 PIT1. */
|
258 | 20dcee94 | pbrook | /* 0xfc088000 EPORT. */
|
259 | 20dcee94 | pbrook | /* 0xfc08c000 Watchdog. */
|
260 | 20dcee94 | pbrook | /* 0xfc090000 clock module. */
|
261 | 20dcee94 | pbrook | /* 0xfc0a0000 CCM + reset. */
|
262 | 20dcee94 | pbrook | /* 0xfc0a4000 GPIO. */
|
263 | 20dcee94 | pbrook | /* 0xfc0a8000 SDRAM controller. */
|
264 | 20dcee94 | pbrook | |
265 | 20dcee94 | pbrook | /* Load kernel. */
|
266 | 20dcee94 | pbrook | if (!kernel_filename) {
|
267 | 20dcee94 | pbrook | fprintf(stderr, "Kernel image must be specified\n");
|
268 | 20dcee94 | pbrook | exit(1);
|
269 | 20dcee94 | pbrook | } |
270 | 20dcee94 | pbrook | |
271 | 409dbce5 | Aurelien Jarno | kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry, |
272 | 409dbce5 | Aurelien Jarno | NULL, NULL, 1, ELF_MACHINE, 0); |
273 | 20dcee94 | pbrook | entry = elf_entry; |
274 | 20dcee94 | pbrook | if (kernel_size < 0) { |
275 | 5a9154e0 | aliguori | kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL); |
276 | 20dcee94 | pbrook | } |
277 | 20dcee94 | pbrook | if (kernel_size < 0) { |
278 | dcac9679 | pbrook | kernel_size = load_image_targphys(kernel_filename, 0x40000000,
|
279 | dcac9679 | pbrook | ram_size); |
280 | dcac9679 | pbrook | entry = 0x40000000;
|
281 | 20dcee94 | pbrook | } |
282 | 20dcee94 | pbrook | if (kernel_size < 0) { |
283 | 20dcee94 | pbrook | fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
|
284 | 20dcee94 | pbrook | exit(1);
|
285 | 20dcee94 | pbrook | } |
286 | 20dcee94 | pbrook | |
287 | 20dcee94 | pbrook | env->pc = entry; |
288 | 20dcee94 | pbrook | } |
289 | 20dcee94 | pbrook | |
290 | f80f9ec9 | Anthony Liguori | static QEMUMachine mcf5208evb_machine = {
|
291 | 4b32e168 | aliguori | .name = "mcf5208evb",
|
292 | 4b32e168 | aliguori | .desc = "MCF5206EVB",
|
293 | 4b32e168 | aliguori | .init = mcf5208evb_init, |
294 | 0c257437 | Anthony Liguori | .is_default = 1,
|
295 | 20dcee94 | pbrook | }; |
296 | f80f9ec9 | Anthony Liguori | |
297 | f80f9ec9 | Anthony Liguori | static void mcf5208evb_machine_init(void) |
298 | f80f9ec9 | Anthony Liguori | { |
299 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&mcf5208evb_machine); |
300 | f80f9ec9 | Anthony Liguori | } |
301 | f80f9ec9 | Anthony Liguori | |
302 | f80f9ec9 | Anthony Liguori | machine_init(mcf5208evb_machine_init); |