Revision 4e9aec74 hw/esp.c
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/* |
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* QEMU ESP emulation |
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* |
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* Copyright (c) 2005 Fabrice Bellard |
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* Copyright (c) 2005-2006 Fabrice Bellard
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a copy |
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* of this software and associated documentation files (the "Software"), to deal |
| ... | ... | |
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#define ESPDMA_REGS 4 |
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#define ESPDMA_MAXADDR (ESPDMA_REGS * 4 - 1) |
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#define ESP_MAXREG 0x3f |
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#define TI_BUFSZ 65536
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#define TI_BUFSZ 1024*1024 // XXX
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#define DMA_VER 0xa0000000 |
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#define DMA_INTR 1 |
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#define DMA_INTREN 0x10 |
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#define DMA_LOADED 0x04000000 |
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typedef struct ESPState ESPState; |
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typedef struct ESPState {
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typedef int ESPDMAFunc(ESPState *s, |
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target_phys_addr_t phys_addr, |
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int transfer_size1); |
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struct ESPState {
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BlockDriverState **bd; |
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uint8_t rregs[ESP_MAXREG]; |
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uint8_t wregs[ESP_MAXREG]; |
| ... | ... | |
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int ti_dir; |
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uint8_t ti_buf[TI_BUFSZ]; |
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int dma; |
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} ESPState; |
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ESPDMAFunc *dma_cb; |
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int64_t offset, len; |
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int target; |
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}; |
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#define STAT_DO 0x00 |
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#define STAT_DI 0x01 |
| ... | ... | |
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return len; |
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} |
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static int esp_write_dma_cb(ESPState *s, |
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target_phys_addr_t phys_addr, |
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int transfer_size1) |
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{
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DPRINTF("Write callback (offset %lld len %lld size %d trans_size %d)\n",
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s->offset, s->len, s->ti_size, transfer_size1); |
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bdrv_write(s->bd[s->target], s->offset, s->ti_buf, s->len); |
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s->offset = 0; |
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s->len = 0; |
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s->target = 0; |
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return 0; |
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} |
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static void handle_satn(ESPState *s) |
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{
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uint8_t buf[32]; |
| ... | ... | |
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s->ti_size = len * 512; |
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} |
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DPRINTF("Read (10) (offset %lld len %lld)\n", offset, len);
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if (s->ti_size > TI_BUFSZ) {
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DPRINTF("size too large %d\n", s->ti_size);
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} |
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bdrv_read(s->bd[target], offset, s->ti_buf, len); |
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// XXX error handling |
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s->ti_dir = 1; |
| ... | ... | |
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s->ti_size = len * 512; |
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} |
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DPRINTF("Write (10) (offset %lld len %lld)\n", offset, len);
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bdrv_write(s->bd[target], offset, s->ti_buf, len); |
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if (s->ti_size > TI_BUFSZ) {
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DPRINTF("size too large %d\n", s->ti_size);
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} |
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s->dma_cb = esp_write_dma_cb; |
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s->offset = offset; |
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s->len = len; |
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s->target = target; |
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// XXX error handling |
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s->ti_dir = 0; |
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break; |
| ... | ... | |
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else |
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cpu_physical_memory_read(dmaptr, &s->ti_buf[i], 1); |
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} |
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if (s->dma_cb) {
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s->dma_cb(s, s->espdmaregs[1], dmalen); |
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s->dma_cb = NULL; |
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} |
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s->rregs[4] = STAT_IN | STAT_TC | STAT_ST; |
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s->rregs[5] = INTR_BS; |
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s->rregs[6] = 0; |
| ... | ... | |
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{
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ESPState *s = opaque; |
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memset(s->rregs, 0, ESP_MAXREG); |
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memset(s->wregs, 0, ESP_MAXREG); |
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s->rregs[0x0e] = 0x4; // Indicate fas100a |
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memset(s->espdmaregs, 0, ESPDMA_REGS * 4); |
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s->ti_size = 0; |
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s->ti_rptr = 0; |
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s->ti_wptr = 0; |
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s->ti_dir = 0; |
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s->dma = 0; |
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s->dma_cb = NULL; |
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} |
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static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
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