Revision 4ec1ce04 hw/cirrus_vga.c
| b/hw/cirrus_vga.c | ||
|---|---|---|
| 1634 | 1634 |
} |
| 1635 | 1635 |
} |
| 1636 | 1636 |
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| 1637 |
static int |
|
| 1638 |
cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value) |
|
| 1637 |
static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value) |
|
| 1639 | 1638 |
{
|
| 1640 |
switch (reg_index) {
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|
| 1639 |
switch (s->vga.cr_index) {
|
|
| 1641 | 1640 |
case 0x00: // Standard VGA |
| 1642 | 1641 |
case 0x01: // Standard VGA |
| 1643 | 1642 |
case 0x02: // Standard VGA |
| ... | ... | |
| 1663 | 1662 |
case 0x16: // Standard VGA |
| 1664 | 1663 |
case 0x17: // Standard VGA |
| 1665 | 1664 |
case 0x18: // Standard VGA |
| 1666 |
return CIRRUS_HOOK_NOT_HANDLED; |
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| 1665 |
/* handle CR0-7 protection */ |
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| 1666 |
if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
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| 1667 |
/* can always write bit 4 of CR7 */ |
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| 1668 |
if (s->vga.cr_index == 7) |
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s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10); |
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| 1670 |
return; |
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| 1671 |
} |
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| 1672 |
s->vga.cr[s->vga.cr_index] = reg_value; |
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| 1673 |
switch(s->vga.cr_index) {
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|
| 1674 |
case 0x00: |
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| 1675 |
case 0x04: |
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| 1676 |
case 0x05: |
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| 1677 |
case 0x06: |
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| 1678 |
case 0x07: |
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| 1679 |
case 0x11: |
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| 1680 |
case 0x17: |
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| 1681 |
s->vga.update_retrace_info(&s->vga); |
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| 1682 |
break; |
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| 1683 |
} |
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| 1684 |
break; |
|
| 1667 | 1685 |
case 0x19: // Interlace End |
| 1668 | 1686 |
case 0x1a: // Miscellaneous Control |
| 1669 | 1687 |
case 0x1b: // Extended Display Control |
| 1670 | 1688 |
case 0x1c: // Sync Adjust and Genlock |
| 1671 | 1689 |
case 0x1d: // Overlay Extended Control |
| 1672 |
s->vga.cr[reg_index] = reg_value;
|
|
| 1690 |
s->vga.cr[s->vga.cr_index] = reg_value;
|
|
| 1673 | 1691 |
#ifdef DEBUG_CIRRUS |
| 1674 | 1692 |
printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
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| 1675 |
reg_index, reg_value);
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| 1693 |
s->vga.cr_index, reg_value);
|
|
| 1676 | 1694 |
#endif |
| 1677 | 1695 |
break; |
| 1678 | 1696 |
case 0x22: // Graphics Data Latches Readback (R) |
| ... | ... | |
| 1683 | 1701 |
case 0x25: // Part Status |
| 1684 | 1702 |
default: |
| 1685 | 1703 |
#ifdef DEBUG_CIRRUS |
| 1686 |
printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
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| 1687 |
reg_value);
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| 1704 |
printf("cirrus: outport cr_index %02x, cr_value %02x\n",
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| 1705 |
s->vga.cr_index, reg_value);
|
|
| 1688 | 1706 |
#endif |
| 1689 | 1707 |
break; |
| 1690 | 1708 |
} |
| 1691 |
|
|
| 1692 |
return CIRRUS_HOOK_HANDLED; |
|
| 1693 | 1709 |
} |
| 1694 | 1710 |
|
| 1695 | 1711 |
/*************************************** |
| ... | ... | |
| 2826 | 2842 |
break; |
| 2827 | 2843 |
case 0x3b5: |
| 2828 | 2844 |
case 0x3d5: |
| 2829 |
if (cirrus_hook_write_cr(c, s->cr_index, val)) |
|
| 2830 |
break; |
|
| 2831 | 2845 |
#ifdef DEBUG_VGA_REG |
| 2832 | 2846 |
printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
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| 2833 | 2847 |
#endif |
| 2834 |
/* handle CR0-7 protection */ |
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| 2835 |
if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
|
|
| 2836 |
/* can always write bit 4 of CR7 */ |
|
| 2837 |
if (s->cr_index == 7) |
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| 2838 |
s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10); |
|
| 2839 |
return; |
|
| 2840 |
} |
|
| 2841 |
s->cr[s->cr_index] = val; |
|
| 2842 |
|
|
| 2843 |
switch(s->cr_index) {
|
|
| 2844 |
case 0x00: |
|
| 2845 |
case 0x04: |
|
| 2846 |
case 0x05: |
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| 2847 |
case 0x06: |
|
| 2848 |
case 0x07: |
|
| 2849 |
case 0x11: |
|
| 2850 |
case 0x17: |
|
| 2851 |
s->update_retrace_info(s); |
|
| 2852 |
break; |
|
| 2853 |
} |
|
| 2848 |
cirrus_vga_write_cr(c, val); |
|
| 2854 | 2849 |
break; |
| 2855 | 2850 |
case 0x3ba: |
| 2856 | 2851 |
case 0x3da: |
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