Archipelago » qemu

/*

 * QEMU Sun4m & Sun4d & Sun4c System Emulator

 *

 * Copyright (c) 2003-2005 Fabrice Bellard

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#include "sysbus.h"

#include "qemu-timer.h"

#include "sun4m.h"

#include "nvram.h"

#include "sparc32_dma.h"

#include "fdc.h"

#include "sysemu.h"

#include "net.h"

#include "boards.h"

#include "firmware_abi.h"

#include "esp.h"

#include "pc.h"

#include "isa.h"

#include "fw_cfg.h"

#include "escc.h"

#include "empty_slot.h"

#include "qdev-addr.h"

#include "loader.h"

#include "elf.h"

#include "blockdev.h"

#include "trace.h"

/*

 * Sun4m architecture was used in the following machines:

 *

 * SPARCserver 6xxMP/xx

 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),

 * SPARCclassic X (4/10)

 * SPARCstation LX/ZX (4/30)

 * SPARCstation Voyager

 * SPARCstation 10/xx, SPARCserver 10/xx

 * SPARCstation 5, SPARCserver 5

 * SPARCstation 20/xx, SPARCserver 20

 * SPARCstation 4

 *

 * Sun4d architecture was used in the following machines:

 *

 * SPARCcenter 2000

 * SPARCserver 1000

 *

 * Sun4c architecture was used in the following machines:

 * SPARCstation 1/1+, SPARCserver 1/1+

 * SPARCstation SLC

 * SPARCstation IPC

 * SPARCstation ELC

 * SPARCstation IPX

 *

 * See for example: http://www.sunhelp.org/faq/sunref1.html

 */

#define KERNEL_LOAD_ADDR     0x00004000

#define CMDLINE_ADDR         0x007ff000

#define INITRD_LOAD_ADDR     0x00800000

#define PROM_SIZE_MAX        (1024 * 1024)

#define PROM_VADDR           0xffd00000

#define PROM_FILENAME        "openbios-sparc32"

#define CFG_ADDR             0xd00000510ULL

#define FW_CFG_SUN4M_DEPTH   (FW_CFG_ARCH_LOCAL + 0x00)

#define MAX_CPUS 16

#define MAX_PILS 16

#define MAX_VSIMMS 4

#define ESCC_CLOCK 4915200

struct sun4m_hwdef {

    target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;

    target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;

    target_phys_addr_t serial_base, fd_base;

    target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;

    target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;

    target_phys_addr_t bpp_base, dbri_base, sx_base;

    struct {

        target_phys_addr_t reg_base, vram_base;

    } vsimm[MAX_VSIMMS];

    target_phys_addr_t ecc_base;

    uint32_t ecc_version;

    uint8_t nvram_machine_id;

    uint16_t machine_id;

    uint32_t iommu_version;

    uint64_t max_mem;

    const char * const default_cpu_model;

};

#define MAX_IOUNITS 5

struct sun4d_hwdef {

    target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;

    target_phys_addr_t counter_base, nvram_base, ms_kb_base;

    target_phys_addr_t serial_base;

    target_phys_addr_t espdma_base, esp_base;

    target_phys_addr_t ledma_base, le_base;

    target_phys_addr_t tcx_base;

    target_phys_addr_t sbi_base;

    uint8_t nvram_machine_id;

    uint16_t machine_id;

    uint32_t iounit_version;

    uint64_t max_mem;

    const char * const default_cpu_model;

};

struct sun4c_hwdef {

    target_phys_addr_t iommu_base, slavio_base;

    target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;

    target_phys_addr_t serial_base, fd_base;

    target_phys_addr_t idreg_base, dma_base, esp_base, le_base;

    target_phys_addr_t tcx_base, aux1_base;

    uint8_t nvram_machine_id;

    uint16_t machine_id;

    uint32_t iommu_version;

    uint64_t max_mem;

    const char * const default_cpu_model;

};

int DMA_get_channel_mode (int nchan)

{

    return 0;

}

int DMA_read_memory (int nchan, void *buf, int pos, int size)

{

    return 0;

}

int DMA_write_memory (int nchan, void *buf, int pos, int size)

{

    return 0;

}

void DMA_hold_DREQ (int nchan) {}

void DMA_release_DREQ (int nchan) {}

void DMA_schedule(int nchan) {}

void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)

{

}

void DMA_register_channel (int nchan,

                           DMA_transfer_handler transfer_handler,

                           void *opaque)

{

}

static int fw_cfg_boot_set(void *opaque, const char *boot_device)

{

    fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);

    return 0;

}

static void nvram_init(M48t59State *nvram, uint8_t *macaddr,

                       const char *cmdline, const char *boot_devices,

                       ram_addr_t RAM_size, uint32_t kernel_size,

                       int width, int height, int depth,

                       int nvram_machine_id, const char *arch)

{

    unsigned int i;

    uint32_t start, end;

    uint8_t image[0x1ff0];

    struct OpenBIOS_nvpart_v1 *part_header;

    memset(image, '\0', sizeof(image));

    start = 0;

    // OpenBIOS nvram variables

    // Variable partition

    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];

    part_header->signature = OPENBIOS_PART_SYSTEM;

    pstrcpy(part_header->name, sizeof(part_header->name), "system");

    end = start + sizeof(struct OpenBIOS_nvpart_v1);

    for (i = 0; i < nb_prom_envs; i++)

        end = OpenBIOS_set_var(image, end, prom_envs[i]);

    // End marker

    image[end++] = '\0';

    end = start + ((end - start + 15) & ~15);

    OpenBIOS_finish_partition(part_header, end - start);

    // free partition

    start = end;

    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];

    part_header->signature = OPENBIOS_PART_FREE;

    pstrcpy(part_header->name, sizeof(part_header->name), "free");

    end = 0x1fd0;

    OpenBIOS_finish_partition(part_header, end - start);

    Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,

                    nvram_machine_id);

    for (i = 0; i < sizeof(image); i++)

        m48t59_write(nvram, i, image[i]);

}

static DeviceState *slavio_intctl;

void pic_info(Monitor *mon)

{

    if (slavio_intctl)

        slavio_pic_info(mon, slavio_intctl);

}

void irq_info(Monitor *mon)

{

    if (slavio_intctl)

        slavio_irq_info(mon, slavio_intctl);

}

void cpu_check_irqs(CPUState *env)

{

    if (env->pil_in && (env->interrupt_index == 0 ||

                        (env->interrupt_index & ~15) == TT_EXTINT)) {

        unsigned int i;

        for (i = 15; i > 0; i--) {

            if (env->pil_in & (1 << i)) {

                int old_interrupt = env->interrupt_index;

                env->interrupt_index = TT_EXTINT | i;

                if (old_interrupt != env->interrupt_index) {

                    trace_sun4m_cpu_interrupt(i);

                    cpu_interrupt(env, CPU_INTERRUPT_HARD);

                }

                break;

            }

        }

    } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {

        trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);

        env->interrupt_index = 0;

        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);

    }

}

static void cpu_set_irq(void *opaque, int irq, int level)

{

    CPUState *env = opaque;

    if (level) {

        trace_sun4m_cpu_set_irq_raise(irq);

        env->halted = 0;

        env->pil_in |= 1 << irq;

        cpu_check_irqs(env);

    } else {

        trace_sun4m_cpu_set_irq_lower(irq);

        env->pil_in &= ~(1 << irq);

        cpu_check_irqs(env);

    }

}

static void dummy_cpu_set_irq(void *opaque, int irq, int level)

{

}

static void main_cpu_reset(void *opaque)

{

    CPUState *env = opaque;

    cpu_reset(env);

    env->halted = 0;

}

static void secondary_cpu_reset(void *opaque)

{

    CPUState *env = opaque;

    cpu_reset(env);

    env->halted = 1;

}

static void cpu_halt_signal(void *opaque, int irq, int level)

{

    if (level && cpu_single_env)

        cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);

}

static uint64_t translate_kernel_address(void *opaque, uint64_t addr)

{

    return addr - 0xf0000000ULL;

}

static unsigned long sun4m_load_kernel(const char *kernel_filename,

                                       const char *initrd_filename,

                                       ram_addr_t RAM_size)

{

    int linux_boot;

    unsigned int i;

    long initrd_size, kernel_size;

    uint8_t *ptr;

    linux_boot = (kernel_filename != NULL);

    kernel_size = 0;

    if (linux_boot) {

        int bswap_needed;

#ifdef BSWAP_NEEDED

        bswap_needed = 1;

#else

        bswap_needed = 0;

#endif

        kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,

                               NULL, NULL, NULL, 1, ELF_MACHINE, 0);

        if (kernel_size < 0)

            kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,

                                    RAM_size - KERNEL_LOAD_ADDR, bswap_needed,

                                    TARGET_PAGE_SIZE);

        if (kernel_size < 0)

            kernel_size = load_image_targphys(kernel_filename,

                                              KERNEL_LOAD_ADDR,

                                              RAM_size - KERNEL_LOAD_ADDR);

        if (kernel_size < 0) {

            fprintf(stderr, "qemu: could not load kernel '%s'\n",

                    kernel_filename);

            exit(1);

        }

        /* load initrd */

        initrd_size = 0;

        if (initrd_filename) {

            initrd_size = load_image_targphys(initrd_filename,

                                              INITRD_LOAD_ADDR,

                                              RAM_size - INITRD_LOAD_ADDR);

            if (initrd_size < 0) {

                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",

                        initrd_filename);

                exit(1);

            }

        }

        if (initrd_size > 0) {

            for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {

                ptr = rom_ptr(KERNEL_LOAD_ADDR + i);

                if (ldl_p(ptr) == 0x48647253) { // HdrS

                    stl_p(ptr + 16, INITRD_LOAD_ADDR);

                    stl_p(ptr + 20, initrd_size);

                    break;

                }

            }

        }

    }

    return kernel_size;

}

static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)

{

    DeviceState *dev;

    SysBusDevice *s;

    dev = qdev_create(NULL, "iommu");

    qdev_prop_set_uint32(dev, "version", version);

    qdev_init_nofail(dev);

    s = sysbus_from_qdev(dev);

    sysbus_connect_irq(s, 0, irq);

    sysbus_mmio_map(s, 0, addr);

    return s;

}

static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,

                              void *iommu, qemu_irq *dev_irq)

{

    DeviceState *dev;

    SysBusDevice *s;

    dev = qdev_create(NULL, "sparc32_dma");

    qdev_prop_set_ptr(dev, "iommu_opaque", iommu);

    qdev_init_nofail(dev);

    s = sysbus_from_qdev(dev);

    sysbus_connect_irq(s, 0, parent_irq);

    *dev_irq = qdev_get_gpio_in(dev, 0);

    sysbus_mmio_map(s, 0, daddr);

    return s;

}

static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,

                       void *dma_opaque, qemu_irq irq)

{

    DeviceState *dev;

    SysBusDevice *s;

    qemu_irq reset;

    qemu_check_nic_model(&nd_table[0], "lance");

    dev = qdev_create(NULL, "lance");

    qdev_set_nic_properties(dev, nd);

    qdev_prop_set_ptr(dev, "dma", dma_opaque);

    qdev_init_nofail(dev);

    s = sysbus_from_qdev(dev);

    sysbus_mmio_map(s, 0, leaddr);

    sysbus_connect_irq(s, 0, irq);

    reset = qdev_get_gpio_in(dev, 0);

    qdev_connect_gpio_out(dma_opaque, 0, reset);

}

static DeviceState *slavio_intctl_init(target_phys_addr_t addr,

                                       target_phys_addr_t addrg,

                                       qemu_irq **parent_irq)

{

    DeviceState *dev;

    SysBusDevice *s;

    unsigned int i, j;

    dev = qdev_create(NULL, "slavio_intctl");

    qdev_init_nofail(dev);

    s = sysbus_from_qdev(dev);

    for (i = 0; i < MAX_CPUS; i++) {

        for (j = 0; j < MAX_PILS; j++) {

            sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);

        }

    }

    sysbus_mmio_map(s, 0, addrg);

    for (i = 0; i < MAX_CPUS; i++) {

        sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);

    }

    return dev;

}

#define SYS_TIMER_OFFSET      0x10000ULL

#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)

static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,

                                  qemu_irq *cpu_irqs, unsigned int num_cpus)

{

    DeviceState *dev;

    SysBusDevice *s;

    unsigned int i;

    dev = qdev_create(NULL, "slavio_timer");

    qdev_prop_set_uint32(dev, "num_cpus", num_cpus);

    qdev_init_nofail(dev);

    s = sysbus_from_qdev(dev);

    sysbus_connect_irq(s, 0, master_irq);

    sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);

    for (i = 0; i < MAX_CPUS; i++) {

        sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));

        sysbus_connect_irq(s, i + 1, cpu_irqs[i]);

    }

}

#define MISC_LEDS 0x01600000

#define MISC_CFG  0x01800000

#define MISC_DIAG 0x01a00000

#define MISC_MDM  0x01b00000

#define MISC_SYS  0x01f00000

static void slavio_misc_init(target_phys_addr_t base,

                             target_phys_addr_t aux1_base,

                             target_phys_addr_t aux2_base, qemu_irq irq,

                             qemu_irq fdc_tc)

{

    DeviceState *dev;

    SysBusDevice *s;

    dev = qdev_create(NULL, "slavio_misc");

    qdev_init_nofail(dev);

    s = sysbus_from_qdev(dev);

    if (base) {

        /* 8 bit registers */

        /* Slavio control */

        sysbus_mmio_map(s, 0, base + MISC_CFG);

        /* Diagnostics */

        sysbus_mmio_map(s, 1, base + MISC_DIAG);

        /* Modem control */

        sysbus_mmio_map(s, 2, base + MISC_MDM);

        /* 16 bit registers */

        /* ss600mp diag LEDs */

        sysbus_mmio_map(s, 3, base + MISC_LEDS);

        /* 32 bit registers */

        /* System control */

        sysbus_mmio_map(s, 4, base + MISC_SYS);

    }

    if (aux1_base) {

        /* AUX 1 (Misc System Functions) */

        sysbus_mmio_map(s, 5, aux1_base);

    }

    if (aux2_base) {

        /* AUX 2 (Software Powerdown Control) */

        sysbus_mmio_map(s, 6, aux2_base);

    }

    sysbus_connect_irq(s, 0, irq);

    sysbus_connect_irq(s, 1, fdc_tc);

    qemu_system_powerdown = qdev_get_gpio_in(dev, 0);

}

static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)

{

    DeviceState *dev;

    SysBusDevice *s;

    dev = qdev_create(NULL, "eccmemctl");

    qdev_prop_set_uint32(dev, "version", version);

    qdev_init_nofail(dev);

    s = sysbus_from_qdev(dev);

    sysbus_connect_irq(s, 0, irq);

    sysbus_mmio_map(s, 0, base);

    if (version == 0) { // SS-600MP only

        sysbus_mmio_map(s, 1, base + 0x1000);

    }

}

static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)

{

    DeviceState *dev;

    SysBusDevice *s;

    dev = qdev_create(NULL, "apc");

    qdev_init_nofail(dev);

    s = sysbus_from_qdev(dev);

    /* Power management (APC) XXX: not a Slavio device */

    sysbus_mmio_map(s, 0, power_base);

    sysbus_connect_irq(s, 0, cpu_halt);

}

static void tcx_init(target_phys_addr_t addr, int vram_size, int width,

                     int height, int depth)

{

    DeviceState *dev;

    SysBusDevice *s;

    dev = qdev_create(NULL, "SUNW,tcx");

    qdev_prop_set_taddr(dev, "addr", addr);

    qdev_prop_set_uint32(dev, "vram_size", vram_size);

    qdev_prop_set_uint16(dev, "width", width);

    qdev_prop_set_uint16(dev, "height", height);

    qdev_prop_set_uint16(dev, "depth", depth);

    qdev_init_nofail(dev);

    s = sysbus_from_qdev(dev);

    /* 8-bit plane */

    sysbus_mmio_map(s, 0, addr + 0x00800000ULL);

    /* DAC */

    sysbus_mmio_map(s, 1, addr + 0x00200000ULL);

    /* TEC (dummy) */

    sysbus_mmio_map(s, 2, addr + 0x00700000ULL);

    /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */

    sysbus_mmio_map(s, 3, addr + 0x00301000ULL);

    if (depth == 24) {

        /* 24-bit plane */

        sysbus_mmio_map(s, 4, addr + 0x02000000ULL);

        /* Control plane */

        sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);

    } else {

        /* THC 8 bit (dummy) */

        sysbus_mmio_map(s, 4, addr + 0x00300000ULL);

    }

}

/* NCR89C100/MACIO Internal ID register */

static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };

static void idreg_init(target_phys_addr_t addr)

{

    DeviceState *dev;

    SysBusDevice *s;

    dev = qdev_create(NULL, "macio_idreg");

    qdev_init_nofail(dev);

    s = sysbus_from_qdev(dev);

    sysbus_mmio_map(s, 0, addr);

    cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));

}

static int idreg_init1(SysBusDevice *dev)

{

    ram_addr_t idreg_offset;

    idreg_offset = qemu_ram_alloc(NULL, "sun4m.idreg", sizeof(idreg_data));

    sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);

    return 0;

}

static SysBusDeviceInfo idreg_info = {

    .init = idreg_init1,

    .qdev.name  = "macio_idreg",

    .qdev.size  = sizeof(SysBusDevice),

};

static void idreg_register_devices(void)

{

    sysbus_register_withprop(&idreg_info);

}

device_init(idreg_register_devices);

/* SS-5 TCX AFX register */

static void afx_init(target_phys_addr_t addr)

{

    DeviceState *dev;

    SysBusDevice *s;

    dev = qdev_create(NULL, "tcx_afx");

    qdev_init_nofail(dev);

    s = sysbus_from_qdev(dev);

    sysbus_mmio_map(s, 0, addr);

}

static int afx_init1(SysBusDevice *dev)

{

    ram_addr_t afx_offset;

    afx_offset = qemu_ram_alloc(NULL, "sun4m.afx", 4);

    sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM);

    return 0;

}

static SysBusDeviceInfo afx_info = {

    .init = afx_init1,

    .qdev.name  = "tcx_afx",

    .qdev.size  = sizeof(SysBusDevice),

};

static void afx_register_devices(void)

{

    sysbus_register_withprop(&afx_info);

}

device_init(afx_register_devices);

/* Boot PROM (OpenBIOS) */

static uint64_t translate_prom_address(void *opaque, uint64_t addr)

{

    target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;

    return addr + *base_addr - PROM_VADDR;

}

static void prom_init(target_phys_addr_t addr, const char *bios_name)

{

    DeviceState *dev;

    SysBusDevice *s;

    char *filename;

    int ret;

    dev = qdev_create(NULL, "openprom");

    qdev_init_nofail(dev);

    s = sysbus_from_qdev(dev);

    sysbus_mmio_map(s, 0, addr);

    /* load boot prom */

    if (bios_name == NULL) {

        bios_name = PROM_FILENAME;

    }

    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);

    if (filename) {

        ret = load_elf(filename, translate_prom_address, &addr, NULL,

                       NULL, NULL, 1, ELF_MACHINE, 0);

        if (ret < 0 || ret > PROM_SIZE_MAX) {

            ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);

        }

        qemu_free(filename);

    } else {

        ret = -1;

    }

    if (ret < 0 || ret > PROM_SIZE_MAX) {

        fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);

        exit(1);

    }

}

static int prom_init1(SysBusDevice *dev)

{

    ram_addr_t prom_offset;

    prom_offset = qemu_ram_alloc(NULL, "sun4m.prom", PROM_SIZE_MAX);

    sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);

    return 0;

}

static SysBusDeviceInfo prom_info = {

    .init = prom_init1,

    .qdev.name  = "openprom",

    .qdev.size  = sizeof(SysBusDevice),

    .qdev.props = (Property[]) {

        {/* end of property list */}

    }

};

static void prom_register_devices(void)

{

    sysbus_register_withprop(&prom_info);

}

device_init(prom_register_devices);

typedef struct RamDevice

{

    SysBusDevice busdev;

    uint64_t size;

} RamDevice;

/* System RAM */

static int ram_init1(SysBusDevice *dev)

{

    ram_addr_t RAM_size, ram_offset;

    RamDevice *d = FROM_SYSBUS(RamDevice, dev);

    RAM_size = d->size;

    ram_offset = qemu_ram_alloc(NULL, "sun4m.ram", RAM_size);

    sysbus_init_mmio(dev, RAM_size, ram_offset);

    return 0;

}

static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,

                     uint64_t max_mem)

{

    DeviceState *dev;

    SysBusDevice *s;

    RamDevice *d;

    /* allocate RAM */

    if ((uint64_t)RAM_size > max_mem) {

        fprintf(stderr,

                "qemu: Too much memory for this machine: %d, maximum %d\n",

                (unsigned int)(RAM_size / (1024 * 1024)),

                (unsigned int)(max_mem / (1024 * 1024)));

        exit(1);

    }

    dev = qdev_create(NULL, "memory");

    s = sysbus_from_qdev(dev);

    d = FROM_SYSBUS(RamDevice, s);

    d->size = RAM_size;

    qdev_init_nofail(dev);

    sysbus_mmio_map(s, 0, addr);

}

static SysBusDeviceInfo ram_info = {

    .init = ram_init1,

    .qdev.name  = "memory",

    .qdev.size  = sizeof(RamDevice),

    .qdev.props = (Property[]) {

        DEFINE_PROP_UINT64("size", RamDevice, size, 0),

        DEFINE_PROP_END_OF_LIST(),

    }

};

static void ram_register_devices(void)

{

    sysbus_register_withprop(&ram_info);

}

device_init(ram_register_devices);

static void cpu_devinit(const char *cpu_model, unsigned int id,

                        uint64_t prom_addr, qemu_irq **cpu_irqs)

{

    CPUState *env;

    env = cpu_init(cpu_model);

    if (!env) {

        fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");

        exit(1);

    }

    cpu_sparc_set_id(env, id);

    if (id == 0) {

        qemu_register_reset(main_cpu_reset, env);

    } else {

        qemu_register_reset(secondary_cpu_reset, env);

        env->halted = 1;

    }

    *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);

    env->prom_addr = prom_addr;

}

static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,

                          const char *boot_device,

                          const char *kernel_filename,

                          const char *kernel_cmdline,

                          const char *initrd_filename, const char *cpu_model)

{

    unsigned int i;

    void *iommu, *espdma, *ledma, *nvram;

    qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],

        espdma_irq, ledma_irq;

    qemu_irq esp_reset, dma_enable;

    qemu_irq fdc_tc;

    qemu_irq *cpu_halt;

    unsigned long kernel_size;

    DriveInfo *fd[MAX_FD];

    void *fw_cfg;

    unsigned int num_vsimms;

    /* init CPUs */

    if (!cpu_model)

        cpu_model = hwdef->default_cpu_model;

    for(i = 0; i < smp_cpus; i++) {

        cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);

    }

    for (i = smp_cpus; i < MAX_CPUS; i++)

        cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);

    /* set up devices */

    ram_init(0, RAM_size, hwdef->max_mem);

    /* models without ECC don't trap when missing ram is accessed */

    if (!hwdef->ecc_base) {

        empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);

    }

    prom_init(hwdef->slavio_base, bios_name);

    slavio_intctl = slavio_intctl_init(hwdef->intctl_base,

                                       hwdef->intctl_base + 0x10000ULL,

                                       cpu_irqs);

    for (i = 0; i < 32; i++) {

        slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);

    }

    for (i = 0; i < MAX_CPUS; i++) {

        slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);

    }

    if (hwdef->idreg_base) {

        idreg_init(hwdef->idreg_base);

    }

    if (hwdef->afx_base) {

        afx_init(hwdef->afx_base);

    }

    iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,

                       slavio_irq[30]);

    if (hwdef->iommu_pad_base) {

        /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.

           Software shouldn't use aliased addresses, neither should it crash

           when does. Using empty_slot instead of aliasing can help with

           debugging such accesses */

        empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);

    }

    espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],

                              iommu, &espdma_irq);

    ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,

                             slavio_irq[16], iommu, &ledma_irq);

    if (graphic_depth != 8 && graphic_depth != 24) {

        fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);

        exit (1);

    }

    num_vsimms = 0;

    if (num_vsimms == 0) {

        tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,

                 graphic_depth);

    }

    for (i = num_vsimms; i < MAX_VSIMMS; i++) {

        /* vsimm registers probed by OBP */

        if (hwdef->vsimm[i].reg_base) {

            empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);

        }

    }

    if (hwdef->sx_base) {

        empty_slot_init(hwdef->sx_base, 0x2000);

    }