root / hw / usb / hcd-ehci.c @ 4ed1c57a
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/*
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* QEMU USB EHCI Emulation
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*
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* Copyright(c) 2008 Emutex Ltd. (address@hidden)
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*
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* EHCI project was started by Mark Burkley, with contributions by
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* Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
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* Jan Kiszka and Vincent Palatin contributed bugfixes.
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*
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or(at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/hw.h" |
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#include "qemu-timer.h" |
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#include "hw/usb.h" |
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#include "hw/pci.h" |
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#include "monitor.h" |
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#include "trace.h" |
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#include "dma.h" |
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#define EHCI_DEBUG 0 |
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#if EHCI_DEBUG
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#define DPRINTF printf
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#else
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#define DPRINTF(...)
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#endif
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/* internal processing - reset HC to try and recover */
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#define USB_RET_PROCERR (-99) |
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#define MMIO_SIZE 0x1000 |
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/* Capability Registers Base Address - section 2.2 */
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#define CAPREGBASE 0x0000 |
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#define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved |
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#define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version # |
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#define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params |
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#define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params |
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#define EECP HCCPARAMS + 1 |
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#define HCSPPORTROUTE1 CAPREGBASE + 0x000c |
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#define HCSPPORTROUTE2 CAPREGBASE + 0x0010 |
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#define OPREGBASE 0x0020 // Operational Registers Base Address |
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#define USBCMD OPREGBASE + 0x0000 |
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#define USBCMD_RUNSTOP (1 << 0) // run / Stop |
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#define USBCMD_HCRESET (1 << 1) // HC Reset |
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#define USBCMD_FLS (3 << 2) // Frame List Size |
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#define USBCMD_FLS_SH 2 // Frame List Size Shift |
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#define USBCMD_PSE (1 << 4) // Periodic Schedule Enable |
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#define USBCMD_ASE (1 << 5) // Asynch Schedule Enable |
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#define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell |
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#define USBCMD_LHCR (1 << 7) // Light Host Controller Reset |
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#define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count |
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#define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable |
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#define USBCMD_ITC (0x7f << 16) // Int Threshold Control |
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#define USBCMD_ITC_SH 16 // Int Threshold Control Shift |
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|
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#define USBSTS OPREGBASE + 0x0004 |
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#define USBSTS_RO_MASK 0x0000003f |
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#define USBSTS_INT (1 << 0) // USB Interrupt |
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#define USBSTS_ERRINT (1 << 1) // Error Interrupt |
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#define USBSTS_PCD (1 << 2) // Port Change Detect |
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#define USBSTS_FLR (1 << 3) // Frame List Rollover |
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#define USBSTS_HSE (1 << 4) // Host System Error |
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#define USBSTS_IAA (1 << 5) // Interrupt on Async Advance |
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#define USBSTS_HALT (1 << 12) // HC Halted |
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#define USBSTS_REC (1 << 13) // Reclamation |
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#define USBSTS_PSS (1 << 14) // Periodic Schedule Status |
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#define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status |
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/*
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* Interrupt enable bits correspond to the interrupt active bits in USBSTS
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* so no need to redefine here.
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*/
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#define USBINTR OPREGBASE + 0x0008 |
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#define USBINTR_MASK 0x0000003f |
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#define FRINDEX OPREGBASE + 0x000c |
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#define CTRLDSSEGMENT OPREGBASE + 0x0010 |
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#define PERIODICLISTBASE OPREGBASE + 0x0014 |
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#define ASYNCLISTADDR OPREGBASE + 0x0018 |
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#define ASYNCLISTADDR_MASK 0xffffffe0 |
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#define CONFIGFLAG OPREGBASE + 0x0040 |
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#define PORTSC (OPREGBASE + 0x0044) |
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#define PORTSC_BEGIN PORTSC
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#define PORTSC_END (PORTSC + 4 * NB_PORTS) |
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/*
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* Bits that are reserved or are read-only are masked out of values
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* written to us by software
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*/
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#define PORTSC_RO_MASK 0x007001c0 |
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#define PORTSC_RWC_MASK 0x0000002a |
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#define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable |
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#define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable |
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#define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable |
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#define PORTSC_PTC (15 << 16) // Port Test Control |
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#define PORTSC_PTC_SH 16 // Port Test Control shift |
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#define PORTSC_PIC (3 << 14) // Port Indicator Control |
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#define PORTSC_PIC_SH 14 // Port Indicator Control Shift |
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#define PORTSC_POWNER (1 << 13) // Port Owner |
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#define PORTSC_PPOWER (1 << 12) // Port Power |
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#define PORTSC_LINESTAT (3 << 10) // Port Line Status |
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#define PORTSC_LINESTAT_SH 10 // Port Line Status Shift |
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#define PORTSC_PRESET (1 << 8) // Port Reset |
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#define PORTSC_SUSPEND (1 << 7) // Port Suspend |
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#define PORTSC_FPRES (1 << 6) // Force Port Resume |
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#define PORTSC_OCC (1 << 5) // Over Current Change |
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#define PORTSC_OCA (1 << 4) // Over Current Active |
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#define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change |
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#define PORTSC_PED (1 << 2) // Port Enable/Disable |
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#define PORTSC_CSC (1 << 1) // Connect Status Change |
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#define PORTSC_CONNECT (1 << 0) // Current Connect Status |
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#define FRAME_TIMER_FREQ 1000 |
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#define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) |
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#define NB_MAXINTRATE 8 // Max rate at which controller issues ints |
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#define NB_PORTS 6 // Number of downstream ports |
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#define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction |
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#define MAX_QH 100 // Max allowable queue heads in a chain |
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/* Internal periodic / asynchronous schedule state machine states
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*/
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typedef enum { |
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EST_INACTIVE = 1000,
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EST_ACTIVE, |
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EST_EXECUTING, |
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EST_SLEEPING, |
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/* The following states are internal to the state machine function
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*/
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EST_WAITLISTHEAD, |
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EST_FETCHENTRY, |
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EST_FETCHQH, |
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EST_FETCHITD, |
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EST_FETCHSITD, |
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EST_ADVANCEQUEUE, |
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EST_FETCHQTD, |
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EST_EXECUTE, |
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EST_WRITEBACK, |
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EST_HORIZONTALQH |
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} EHCI_STATES; |
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/* macros for accessing fields within next link pointer entry */
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#define NLPTR_GET(x) ((x) & 0xffffffe0) |
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#define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) |
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#define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid |
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/* link pointer types */
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#define NLPTR_TYPE_ITD 0 // isoc xfer descriptor |
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#define NLPTR_TYPE_QH 1 // queue head |
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#define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor |
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#define NLPTR_TYPE_FSTN 3 // frame span traversal node |
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/* EHCI spec version 1.0 Section 3.3
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*/
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typedef struct EHCIitd { |
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uint32_t next; |
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uint32_t transact[8];
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#define ITD_XACT_ACTIVE (1 << 31) |
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#define ITD_XACT_DBERROR (1 << 30) |
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#define ITD_XACT_BABBLE (1 << 29) |
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#define ITD_XACT_XACTERR (1 << 28) |
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#define ITD_XACT_LENGTH_MASK 0x0fff0000 |
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#define ITD_XACT_LENGTH_SH 16 |
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#define ITD_XACT_IOC (1 << 15) |
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#define ITD_XACT_PGSEL_MASK 0x00007000 |
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#define ITD_XACT_PGSEL_SH 12 |
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#define ITD_XACT_OFFSET_MASK 0x00000fff |
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uint32_t bufptr[7];
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#define ITD_BUFPTR_MASK 0xfffff000 |
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#define ITD_BUFPTR_SH 12 |
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#define ITD_BUFPTR_EP_MASK 0x00000f00 |
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#define ITD_BUFPTR_EP_SH 8 |
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#define ITD_BUFPTR_DEVADDR_MASK 0x0000007f |
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#define ITD_BUFPTR_DEVADDR_SH 0 |
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#define ITD_BUFPTR_DIRECTION (1 << 11) |
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#define ITD_BUFPTR_MAXPKT_MASK 0x000007ff |
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#define ITD_BUFPTR_MAXPKT_SH 0 |
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#define ITD_BUFPTR_MULT_MASK 0x00000003 |
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#define ITD_BUFPTR_MULT_SH 0 |
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} EHCIitd; |
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/* EHCI spec version 1.0 Section 3.4
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*/
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typedef struct EHCIsitd { |
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uint32_t next; // Standard next link pointer
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uint32_t epchar; |
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#define SITD_EPCHAR_IO (1 << 31) |
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#define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 |
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#define SITD_EPCHAR_PORTNUM_SH 24 |
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#define SITD_EPCHAR_HUBADD_MASK 0x007f0000 |
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#define SITD_EPCHAR_HUBADDR_SH 16 |
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#define SITD_EPCHAR_EPNUM_MASK 0x00000f00 |
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#define SITD_EPCHAR_EPNUM_SH 8 |
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#define SITD_EPCHAR_DEVADDR_MASK 0x0000007f |
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uint32_t uframe; |
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#define SITD_UFRAME_CMASK_MASK 0x0000ff00 |
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#define SITD_UFRAME_CMASK_SH 8 |
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#define SITD_UFRAME_SMASK_MASK 0x000000ff |
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uint32_t results; |
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#define SITD_RESULTS_IOC (1 << 31) |
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#define SITD_RESULTS_PGSEL (1 << 30) |
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#define SITD_RESULTS_TBYTES_MASK 0x03ff0000 |
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#define SITD_RESULTS_TYBYTES_SH 16 |
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#define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 |
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#define SITD_RESULTS_CPROGMASK_SH 8 |
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#define SITD_RESULTS_ACTIVE (1 << 7) |
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#define SITD_RESULTS_ERR (1 << 6) |
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#define SITD_RESULTS_DBERR (1 << 5) |
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#define SITD_RESULTS_BABBLE (1 << 4) |
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#define SITD_RESULTS_XACTERR (1 << 3) |
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#define SITD_RESULTS_MISSEDUF (1 << 2) |
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#define SITD_RESULTS_SPLITXSTATE (1 << 1) |
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uint32_t bufptr[2];
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#define SITD_BUFPTR_MASK 0xfffff000 |
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#define SITD_BUFPTR_CURROFF_MASK 0x00000fff |
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#define SITD_BUFPTR_TPOS_MASK 0x00000018 |
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#define SITD_BUFPTR_TPOS_SH 3 |
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#define SITD_BUFPTR_TCNT_MASK 0x00000007 |
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uint32_t backptr; // Standard next link pointer
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} EHCIsitd; |
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/* EHCI spec version 1.0 Section 3.5
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*/
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typedef struct EHCIqtd { |
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uint32_t next; // Standard next link pointer
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uint32_t altnext; // Standard next link pointer
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uint32_t token; |
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#define QTD_TOKEN_DTOGGLE (1 << 31) |
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#define QTD_TOKEN_TBYTES_MASK 0x7fff0000 |
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#define QTD_TOKEN_TBYTES_SH 16 |
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#define QTD_TOKEN_IOC (1 << 15) |
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#define QTD_TOKEN_CPAGE_MASK 0x00007000 |
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#define QTD_TOKEN_CPAGE_SH 12 |
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#define QTD_TOKEN_CERR_MASK 0x00000c00 |
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#define QTD_TOKEN_CERR_SH 10 |
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#define QTD_TOKEN_PID_MASK 0x00000300 |
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#define QTD_TOKEN_PID_SH 8 |
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#define QTD_TOKEN_ACTIVE (1 << 7) |
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#define QTD_TOKEN_HALT (1 << 6) |
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#define QTD_TOKEN_DBERR (1 << 5) |
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#define QTD_TOKEN_BABBLE (1 << 4) |
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#define QTD_TOKEN_XACTERR (1 << 3) |
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#define QTD_TOKEN_MISSEDUF (1 << 2) |
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#define QTD_TOKEN_SPLITXSTATE (1 << 1) |
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#define QTD_TOKEN_PING (1 << 0) |
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uint32_t bufptr[5]; // Standard buffer pointer |
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#define QTD_BUFPTR_MASK 0xfffff000 |
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#define QTD_BUFPTR_SH 12 |
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} EHCIqtd; |
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/* EHCI spec version 1.0 Section 3.6
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*/
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typedef struct EHCIqh { |
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uint32_t next; // Standard next link pointer
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/* endpoint characteristics */
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uint32_t epchar; |
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#define QH_EPCHAR_RL_MASK 0xf0000000 |
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#define QH_EPCHAR_RL_SH 28 |
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#define QH_EPCHAR_C (1 << 27) |
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#define QH_EPCHAR_MPLEN_MASK 0x07FF0000 |
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#define QH_EPCHAR_MPLEN_SH 16 |
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#define QH_EPCHAR_H (1 << 15) |
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#define QH_EPCHAR_DTC (1 << 14) |
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#define QH_EPCHAR_EPS_MASK 0x00003000 |
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#define QH_EPCHAR_EPS_SH 12 |
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#define EHCI_QH_EPS_FULL 0 |
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#define EHCI_QH_EPS_LOW 1 |
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#define EHCI_QH_EPS_HIGH 2 |
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#define EHCI_QH_EPS_RESERVED 3 |
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|
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#define QH_EPCHAR_EP_MASK 0x00000f00 |
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#define QH_EPCHAR_EP_SH 8 |
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#define QH_EPCHAR_I (1 << 7) |
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#define QH_EPCHAR_DEVADDR_MASK 0x0000007f |
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#define QH_EPCHAR_DEVADDR_SH 0 |
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|
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/* endpoint capabilities */
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uint32_t epcap; |
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#define QH_EPCAP_MULT_MASK 0xc0000000 |
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#define QH_EPCAP_MULT_SH 30 |
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#define QH_EPCAP_PORTNUM_MASK 0x3f800000 |
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#define QH_EPCAP_PORTNUM_SH 23 |
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#define QH_EPCAP_HUBADDR_MASK 0x007f0000 |
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#define QH_EPCAP_HUBADDR_SH 16 |
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#define QH_EPCAP_CMASK_MASK 0x0000ff00 |
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#define QH_EPCAP_CMASK_SH 8 |
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#define QH_EPCAP_SMASK_MASK 0x000000ff |
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#define QH_EPCAP_SMASK_SH 0 |
315 |
|
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uint32_t current_qtd; // Standard next link pointer
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uint32_t next_qtd; // Standard next link pointer
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uint32_t altnext_qtd; |
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#define QH_ALTNEXT_NAKCNT_MASK 0x0000001e |
320 |
#define QH_ALTNEXT_NAKCNT_SH 1 |
321 |
|
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uint32_t token; // Same as QTD token
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uint32_t bufptr[5]; // Standard buffer pointer |
324 |
#define BUFPTR_CPROGMASK_MASK 0x000000ff |
325 |
#define BUFPTR_FRAMETAG_MASK 0x0000001f |
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#define BUFPTR_SBYTES_MASK 0x00000fe0 |
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#define BUFPTR_SBYTES_SH 5 |
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} EHCIqh; |
329 |
|
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/* EHCI spec version 1.0 Section 3.7
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*/
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typedef struct EHCIfstn { |
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uint32_t next; // Standard next link pointer
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uint32_t backptr; // Standard next link pointer
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} EHCIfstn; |
336 |
|
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typedef struct EHCIPacket EHCIPacket; |
338 |
typedef struct EHCIQueue EHCIQueue; |
339 |
typedef struct EHCIState EHCIState; |
340 |
|
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enum async_state {
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EHCI_ASYNC_NONE = 0,
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EHCI_ASYNC_INFLIGHT, |
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EHCI_ASYNC_FINISHED, |
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}; |
346 |
|
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struct EHCIPacket {
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EHCIQueue *queue; |
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QTAILQ_ENTRY(EHCIPacket) next; |
350 |
|
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EHCIqtd qtd; /* copy of current QTD (being worked on) */
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uint32_t qtdaddr; /* address QTD read from */
|
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|
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USBPacket packet; |
355 |
QEMUSGList sgl; |
356 |
int pid;
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uint32_t tbytes; |
358 |
enum async_state async;
|
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int usb_status;
|
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}; |
361 |
|
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struct EHCIQueue {
|
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EHCIState *ehci; |
364 |
QTAILQ_ENTRY(EHCIQueue) next; |
365 |
uint32_t seen; |
366 |
uint64_t ts; |
367 |
int async;
|
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|
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/* cached data from guest - needs to be flushed
|
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* when guest removes an entry (doorbell, handshake sequence)
|
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*/
|
372 |
EHCIqh qh; /* copy of current QH (being worked on) */
|
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uint32_t qhaddr; /* address QH read from */
|
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uint32_t qtdaddr; /* address QTD read from */
|
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USBDevice *dev; |
376 |
QTAILQ_HEAD(, EHCIPacket) packets; |
377 |
}; |
378 |
|
379 |
typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;
|
380 |
|
381 |
struct EHCIState {
|
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PCIDevice dev; |
383 |
USBBus bus; |
384 |
qemu_irq irq; |
385 |
MemoryRegion mem; |
386 |
int companion_count;
|
387 |
|
388 |
/* properties */
|
389 |
uint32_t maxframes; |
390 |
|
391 |
/*
|
392 |
* EHCI spec version 1.0 Section 2.3
|
393 |
* Host Controller Operational Registers
|
394 |
*/
|
395 |
union {
|
396 |
uint8_t mmio[MMIO_SIZE]; |
397 |
struct {
|
398 |
uint8_t cap[OPREGBASE]; |
399 |
uint32_t usbcmd; |
400 |
uint32_t usbsts; |
401 |
uint32_t usbintr; |
402 |
uint32_t frindex; |
403 |
uint32_t ctrldssegment; |
404 |
uint32_t periodiclistbase; |
405 |
uint32_t asynclistaddr; |
406 |
uint32_t notused[9];
|
407 |
uint32_t configflag; |
408 |
uint32_t portsc[NB_PORTS]; |
409 |
}; |
410 |
}; |
411 |
|
412 |
/*
|
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* Internal states, shadow registers, etc
|
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*/
|
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QEMUTimer *frame_timer; |
416 |
QEMUBH *async_bh; |
417 |
uint32_t astate; /* Current state in asynchronous schedule */
|
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uint32_t pstate; /* Current state in periodic schedule */
|
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USBPort ports[NB_PORTS]; |
420 |
USBPort *companion_ports[NB_PORTS]; |
421 |
uint32_t usbsts_pending; |
422 |
EHCIQueueHead aqueues; |
423 |
EHCIQueueHead pqueues; |
424 |
|
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/* which address to look at next */
|
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uint32_t a_fetch_addr; |
427 |
uint32_t p_fetch_addr; |
428 |
|
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USBPacket ipacket; |
430 |
QEMUSGList isgl; |
431 |
|
432 |
uint64_t last_run_ns; |
433 |
uint32_t async_stepdown; |
434 |
}; |
435 |
|
436 |
#define SET_LAST_RUN_CLOCK(s) \
|
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(s)->last_run_ns = qemu_get_clock_ns(vm_clock); |
438 |
|
439 |
/* nifty macros from Arnon's EHCI version */
|
440 |
#define get_field(data, field) \
|
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(((data) & field##_MASK) >> field##_SH) |
442 |
|
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#define set_field(data, newval, field) do { \ |
444 |
uint32_t val = *data; \ |
445 |
val &= ~ field##_MASK; \ |
446 |
val |= ((newval) << field##_SH) & field##_MASK; \ |
447 |
*data = val; \ |
448 |
} while(0) |
449 |
|
450 |
static const char *ehci_state_names[] = { |
451 |
[EST_INACTIVE] = "INACTIVE",
|
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[EST_ACTIVE] = "ACTIVE",
|
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[EST_EXECUTING] = "EXECUTING",
|
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[EST_SLEEPING] = "SLEEPING",
|
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[EST_WAITLISTHEAD] = "WAITLISTHEAD",
|
456 |
[EST_FETCHENTRY] = "FETCH ENTRY",
|
457 |
[EST_FETCHQH] = "FETCH QH",
|
458 |
[EST_FETCHITD] = "FETCH ITD",
|
459 |
[EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
|
460 |
[EST_FETCHQTD] = "FETCH QTD",
|
461 |
[EST_EXECUTE] = "EXECUTE",
|
462 |
[EST_WRITEBACK] = "WRITEBACK",
|
463 |
[EST_HORIZONTALQH] = "HORIZONTALQH",
|
464 |
}; |
465 |
|
466 |
static const char *ehci_mmio_names[] = { |
467 |
[CAPLENGTH] = "CAPLENGTH",
|
468 |
[HCIVERSION] = "HCIVERSION",
|
469 |
[HCSPARAMS] = "HCSPARAMS",
|
470 |
[HCCPARAMS] = "HCCPARAMS",
|
471 |
[USBCMD] = "USBCMD",
|
472 |
[USBSTS] = "USBSTS",
|
473 |
[USBINTR] = "USBINTR",
|
474 |
[FRINDEX] = "FRINDEX",
|
475 |
[PERIODICLISTBASE] = "P-LIST BASE",
|
476 |
[ASYNCLISTADDR] = "A-LIST ADDR",
|
477 |
[PORTSC_BEGIN] = "PORTSC #0",
|
478 |
[PORTSC_BEGIN + 4] = "PORTSC #1", |
479 |
[PORTSC_BEGIN + 8] = "PORTSC #2", |
480 |
[PORTSC_BEGIN + 12] = "PORTSC #3", |
481 |
[PORTSC_BEGIN + 16] = "PORTSC #4", |
482 |
[PORTSC_BEGIN + 20] = "PORTSC #5", |
483 |
[CONFIGFLAG] = "CONFIGFLAG",
|
484 |
}; |
485 |
|
486 |
static const char *nr2str(const char **n, size_t len, uint32_t nr) |
487 |
{ |
488 |
if (nr < len && n[nr] != NULL) { |
489 |
return n[nr];
|
490 |
} else {
|
491 |
return "unknown"; |
492 |
} |
493 |
} |
494 |
|
495 |
static const char *state2str(uint32_t state) |
496 |
{ |
497 |
return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
|
498 |
} |
499 |
|
500 |
static const char *addr2str(target_phys_addr_t addr) |
501 |
{ |
502 |
return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
|
503 |
} |
504 |
|
505 |
static void ehci_trace_usbsts(uint32_t mask, int state) |
506 |
{ |
507 |
/* interrupts */
|
508 |
if (mask & USBSTS_INT) {
|
509 |
trace_usb_ehci_usbsts("INT", state);
|
510 |
} |
511 |
if (mask & USBSTS_ERRINT) {
|
512 |
trace_usb_ehci_usbsts("ERRINT", state);
|
513 |
} |
514 |
if (mask & USBSTS_PCD) {
|
515 |
trace_usb_ehci_usbsts("PCD", state);
|
516 |
} |
517 |
if (mask & USBSTS_FLR) {
|
518 |
trace_usb_ehci_usbsts("FLR", state);
|
519 |
} |
520 |
if (mask & USBSTS_HSE) {
|
521 |
trace_usb_ehci_usbsts("HSE", state);
|
522 |
} |
523 |
if (mask & USBSTS_IAA) {
|
524 |
trace_usb_ehci_usbsts("IAA", state);
|
525 |
} |
526 |
|
527 |
/* status */
|
528 |
if (mask & USBSTS_HALT) {
|
529 |
trace_usb_ehci_usbsts("HALT", state);
|
530 |
} |
531 |
if (mask & USBSTS_REC) {
|
532 |
trace_usb_ehci_usbsts("REC", state);
|
533 |
} |
534 |
if (mask & USBSTS_PSS) {
|
535 |
trace_usb_ehci_usbsts("PSS", state);
|
536 |
} |
537 |
if (mask & USBSTS_ASS) {
|
538 |
trace_usb_ehci_usbsts("ASS", state);
|
539 |
} |
540 |
} |
541 |
|
542 |
static inline void ehci_set_usbsts(EHCIState *s, int mask) |
543 |
{ |
544 |
if ((s->usbsts & mask) == mask) {
|
545 |
return;
|
546 |
} |
547 |
ehci_trace_usbsts(mask, 1);
|
548 |
s->usbsts |= mask; |
549 |
} |
550 |
|
551 |
static inline void ehci_clear_usbsts(EHCIState *s, int mask) |
552 |
{ |
553 |
if ((s->usbsts & mask) == 0) { |
554 |
return;
|
555 |
} |
556 |
ehci_trace_usbsts(mask, 0);
|
557 |
s->usbsts &= ~mask; |
558 |
} |
559 |
|
560 |
static inline void ehci_set_interrupt(EHCIState *s, int intr) |
561 |
{ |
562 |
int level = 0; |
563 |
|
564 |
// TODO honour interrupt threshold requests
|
565 |
|
566 |
ehci_set_usbsts(s, intr); |
567 |
|
568 |
if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
|
569 |
level = 1;
|
570 |
} |
571 |
|
572 |
trace_usb_ehci_interrupt(level, s->usbsts, s->usbintr); |
573 |
qemu_set_irq(s->irq, level); |
574 |
} |
575 |
|
576 |
static inline void ehci_record_interrupt(EHCIState *s, int intr) |
577 |
{ |
578 |
s->usbsts_pending |= intr; |
579 |
} |
580 |
|
581 |
static inline void ehci_commit_interrupt(EHCIState *s) |
582 |
{ |
583 |
if (!s->usbsts_pending) {
|
584 |
return;
|
585 |
} |
586 |
ehci_set_interrupt(s, s->usbsts_pending); |
587 |
s->usbsts_pending = 0;
|
588 |
} |
589 |
|
590 |
static void ehci_update_halt(EHCIState *s) |
591 |
{ |
592 |
if (s->usbcmd & USBCMD_RUNSTOP) {
|
593 |
ehci_clear_usbsts(s, USBSTS_HALT); |
594 |
} else {
|
595 |
if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) {
|
596 |
ehci_set_usbsts(s, USBSTS_HALT); |
597 |
} |
598 |
} |
599 |
} |
600 |
|
601 |
static void ehci_set_state(EHCIState *s, int async, int state) |
602 |
{ |
603 |
if (async) {
|
604 |
trace_usb_ehci_state("async", state2str(state));
|
605 |
s->astate = state; |
606 |
if (s->astate == EST_INACTIVE) {
|
607 |
ehci_clear_usbsts(s, USBSTS_ASS); |
608 |
ehci_update_halt(s); |
609 |
} else {
|
610 |
ehci_set_usbsts(s, USBSTS_ASS); |
611 |
} |
612 |
} else {
|
613 |
trace_usb_ehci_state("periodic", state2str(state));
|
614 |
s->pstate = state; |
615 |
if (s->pstate == EST_INACTIVE) {
|
616 |
ehci_clear_usbsts(s, USBSTS_PSS); |
617 |
ehci_update_halt(s); |
618 |
} else {
|
619 |
ehci_set_usbsts(s, USBSTS_PSS); |
620 |
} |
621 |
} |
622 |
} |
623 |
|
624 |
static int ehci_get_state(EHCIState *s, int async) |
625 |
{ |
626 |
return async ? s->astate : s->pstate;
|
627 |
} |
628 |
|
629 |
static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) |
630 |
{ |
631 |
if (async) {
|
632 |
s->a_fetch_addr = addr; |
633 |
} else {
|
634 |
s->p_fetch_addr = addr; |
635 |
} |
636 |
} |
637 |
|
638 |
static int ehci_get_fetch_addr(EHCIState *s, int async) |
639 |
{ |
640 |
return async ? s->a_fetch_addr : s->p_fetch_addr;
|
641 |
} |
642 |
|
643 |
static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh) |
644 |
{ |
645 |
/* need three here due to argument count limits */
|
646 |
trace_usb_ehci_qh_ptrs(q, addr, qh->next, |
647 |
qh->current_qtd, qh->next_qtd, qh->altnext_qtd); |
648 |
trace_usb_ehci_qh_fields(addr, |
649 |
get_field(qh->epchar, QH_EPCHAR_RL), |
650 |
get_field(qh->epchar, QH_EPCHAR_MPLEN), |
651 |
get_field(qh->epchar, QH_EPCHAR_EPS), |
652 |
get_field(qh->epchar, QH_EPCHAR_EP), |
653 |
get_field(qh->epchar, QH_EPCHAR_DEVADDR)); |
654 |
trace_usb_ehci_qh_bits(addr, |
655 |
(bool)(qh->epchar & QH_EPCHAR_C),
|
656 |
(bool)(qh->epchar & QH_EPCHAR_H),
|
657 |
(bool)(qh->epchar & QH_EPCHAR_DTC),
|
658 |
(bool)(qh->epchar & QH_EPCHAR_I));
|
659 |
} |
660 |
|
661 |
static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd) |
662 |
{ |
663 |
/* need three here due to argument count limits */
|
664 |
trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); |
665 |
trace_usb_ehci_qtd_fields(addr, |
666 |
get_field(qtd->token, QTD_TOKEN_TBYTES), |
667 |
get_field(qtd->token, QTD_TOKEN_CPAGE), |
668 |
get_field(qtd->token, QTD_TOKEN_CERR), |
669 |
get_field(qtd->token, QTD_TOKEN_PID)); |
670 |
trace_usb_ehci_qtd_bits(addr, |
671 |
(bool)(qtd->token & QTD_TOKEN_IOC),
|
672 |
(bool)(qtd->token & QTD_TOKEN_ACTIVE),
|
673 |
(bool)(qtd->token & QTD_TOKEN_HALT),
|
674 |
(bool)(qtd->token & QTD_TOKEN_BABBLE),
|
675 |
(bool)(qtd->token & QTD_TOKEN_XACTERR));
|
676 |
} |
677 |
|
678 |
static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd) |
679 |
{ |
680 |
trace_usb_ehci_itd(addr, itd->next, |
681 |
get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
|
682 |
get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
|
683 |
get_field(itd->bufptr[0], ITD_BUFPTR_EP),
|
684 |
get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
|
685 |
} |
686 |
|
687 |
static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr, |
688 |
EHCIsitd *sitd) |
689 |
{ |
690 |
trace_usb_ehci_sitd(addr, sitd->next, |
691 |
(bool)(sitd->results & SITD_RESULTS_ACTIVE));
|
692 |
} |
693 |
|
694 |
static inline bool ehci_enabled(EHCIState *s) |
695 |
{ |
696 |
return s->usbcmd & USBCMD_RUNSTOP;
|
697 |
} |
698 |
|
699 |
static inline bool ehci_async_enabled(EHCIState *s) |
700 |
{ |
701 |
return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE);
|
702 |
} |
703 |
|
704 |
static inline bool ehci_periodic_enabled(EHCIState *s) |
705 |
{ |
706 |
return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE);
|
707 |
} |
708 |
|
709 |
/* packet management */
|
710 |
|
711 |
static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
|
712 |
{ |
713 |
EHCIPacket *p; |
714 |
|
715 |
p = g_new0(EHCIPacket, 1);
|
716 |
p->queue = q; |
717 |
usb_packet_init(&p->packet); |
718 |
QTAILQ_INSERT_TAIL(&q->packets, p, next); |
719 |
trace_usb_ehci_packet_action(p->queue, p, "alloc");
|
720 |
return p;
|
721 |
} |
722 |
|
723 |
static void ehci_free_packet(EHCIPacket *p) |
724 |
{ |
725 |
trace_usb_ehci_packet_action(p->queue, p, "free");
|
726 |
if (p->async == EHCI_ASYNC_INFLIGHT) {
|
727 |
usb_cancel_packet(&p->packet); |
728 |
} |
729 |
QTAILQ_REMOVE(&p->queue->packets, p, next); |
730 |
usb_packet_cleanup(&p->packet); |
731 |
g_free(p); |
732 |
} |
733 |
|
734 |
/* queue management */
|
735 |
|
736 |
static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async) |
737 |
{ |
738 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
739 |
EHCIQueue *q; |
740 |
|
741 |
q = g_malloc0(sizeof(*q));
|
742 |
q->ehci = ehci; |
743 |
q->qhaddr = addr; |
744 |
q->async = async; |
745 |
QTAILQ_INIT(&q->packets); |
746 |
QTAILQ_INSERT_HEAD(head, q, next); |
747 |
trace_usb_ehci_queue_action(q, "alloc");
|
748 |
return q;
|
749 |
} |
750 |
|
751 |
static void ehci_free_queue(EHCIQueue *q) |
752 |
{ |
753 |
EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues; |
754 |
EHCIPacket *p; |
755 |
|
756 |
trace_usb_ehci_queue_action(q, "free");
|
757 |
while ((p = QTAILQ_FIRST(&q->packets)) != NULL) { |
758 |
ehci_free_packet(p); |
759 |
} |
760 |
QTAILQ_REMOVE(head, q, next); |
761 |
g_free(q); |
762 |
} |
763 |
|
764 |
static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
|
765 |
int async)
|
766 |
{ |
767 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
768 |
EHCIQueue *q; |
769 |
|
770 |
QTAILQ_FOREACH(q, head, next) { |
771 |
if (addr == q->qhaddr) {
|
772 |
return q;
|
773 |
} |
774 |
} |
775 |
return NULL; |
776 |
} |
777 |
|
778 |
static void ehci_queues_rip_unused(EHCIState *ehci, int async, int flush) |
779 |
{ |
780 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
781 |
uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4;
|
782 |
EHCIQueue *q, *tmp; |
783 |
|
784 |
QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
785 |
if (q->seen) {
|
786 |
q->seen = 0;
|
787 |
q->ts = ehci->last_run_ns; |
788 |
continue;
|
789 |
} |
790 |
if (!flush && ehci->last_run_ns < q->ts + maxage) {
|
791 |
continue;
|
792 |
} |
793 |
ehci_free_queue(q); |
794 |
} |
795 |
} |
796 |
|
797 |
static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async) |
798 |
{ |
799 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
800 |
EHCIQueue *q, *tmp; |
801 |
|
802 |
QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
803 |
if (q->dev != dev) {
|
804 |
continue;
|
805 |
} |
806 |
ehci_free_queue(q); |
807 |
} |
808 |
} |
809 |
|
810 |
static void ehci_queues_rip_all(EHCIState *ehci, int async) |
811 |
{ |
812 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
813 |
EHCIQueue *q, *tmp; |
814 |
|
815 |
QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
816 |
ehci_free_queue(q); |
817 |
} |
818 |
} |
819 |
|
820 |
/* Attach or detach a device on root hub */
|
821 |
|
822 |
static void ehci_attach(USBPort *port) |
823 |
{ |
824 |
EHCIState *s = port->opaque; |
825 |
uint32_t *portsc = &s->portsc[port->index]; |
826 |
const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; |
827 |
|
828 |
trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc); |
829 |
|
830 |
if (*portsc & PORTSC_POWNER) {
|
831 |
USBPort *companion = s->companion_ports[port->index]; |
832 |
companion->dev = port->dev; |
833 |
companion->ops->attach(companion); |
834 |
return;
|
835 |
} |
836 |
|
837 |
*portsc |= PORTSC_CONNECT; |
838 |
*portsc |= PORTSC_CSC; |
839 |
|
840 |
ehci_set_interrupt(s, USBSTS_PCD); |
841 |
} |
842 |
|
843 |
static void ehci_detach(USBPort *port) |
844 |
{ |
845 |
EHCIState *s = port->opaque; |
846 |
uint32_t *portsc = &s->portsc[port->index]; |
847 |
const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; |
848 |
|
849 |
trace_usb_ehci_port_detach(port->index, owner); |
850 |
|
851 |
if (*portsc & PORTSC_POWNER) {
|
852 |
USBPort *companion = s->companion_ports[port->index]; |
853 |
companion->ops->detach(companion); |
854 |
companion->dev = NULL;
|
855 |
/*
|
856 |
* EHCI spec 4.2.2: "When a disconnect occurs... On the event,
|
857 |
* the port ownership is returned immediately to the EHCI controller."
|
858 |
*/
|
859 |
*portsc &= ~PORTSC_POWNER; |
860 |
return;
|
861 |
} |
862 |
|
863 |
ehci_queues_rip_device(s, port->dev, 0);
|
864 |
ehci_queues_rip_device(s, port->dev, 1);
|
865 |
|
866 |
*portsc &= ~(PORTSC_CONNECT|PORTSC_PED); |
867 |
*portsc |= PORTSC_CSC; |
868 |
|
869 |
ehci_set_interrupt(s, USBSTS_PCD); |
870 |
} |
871 |
|
872 |
static void ehci_child_detach(USBPort *port, USBDevice *child) |
873 |
{ |
874 |
EHCIState *s = port->opaque; |
875 |
uint32_t portsc = s->portsc[port->index]; |
876 |
|
877 |
if (portsc & PORTSC_POWNER) {
|
878 |
USBPort *companion = s->companion_ports[port->index]; |
879 |
companion->ops->child_detach(companion, child); |
880 |
return;
|
881 |
} |
882 |
|
883 |
ehci_queues_rip_device(s, child, 0);
|
884 |
ehci_queues_rip_device(s, child, 1);
|
885 |
} |
886 |
|
887 |
static void ehci_wakeup(USBPort *port) |
888 |
{ |
889 |
EHCIState *s = port->opaque; |
890 |
uint32_t portsc = s->portsc[port->index]; |
891 |
|
892 |
if (portsc & PORTSC_POWNER) {
|
893 |
USBPort *companion = s->companion_ports[port->index]; |
894 |
if (companion->ops->wakeup) {
|
895 |
companion->ops->wakeup(companion); |
896 |
} else {
|
897 |
qemu_bh_schedule(s->async_bh); |
898 |
} |
899 |
} |
900 |
} |
901 |
|
902 |
static int ehci_register_companion(USBBus *bus, USBPort *ports[], |
903 |
uint32_t portcount, uint32_t firstport) |
904 |
{ |
905 |
EHCIState *s = container_of(bus, EHCIState, bus); |
906 |
uint32_t i; |
907 |
|
908 |
if (firstport + portcount > NB_PORTS) {
|
909 |
qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
|
910 |
"firstport on masterbus");
|
911 |
error_printf_unless_qmp( |
912 |
"firstport value of %u makes companion take ports %u - %u, which "
|
913 |
"is outside of the valid range of 0 - %u\n", firstport, firstport,
|
914 |
firstport + portcount - 1, NB_PORTS - 1); |
915 |
return -1; |
916 |
} |
917 |
|
918 |
for (i = 0; i < portcount; i++) { |
919 |
if (s->companion_ports[firstport + i]) {
|
920 |
qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
|
921 |
"an USB masterbus");
|
922 |
error_printf_unless_qmp( |
923 |
"port %u on masterbus %s already has a companion assigned\n",
|
924 |
firstport + i, bus->qbus.name); |
925 |
return -1; |
926 |
} |
927 |
} |
928 |
|
929 |
for (i = 0; i < portcount; i++) { |
930 |
s->companion_ports[firstport + i] = ports[i]; |
931 |
s->ports[firstport + i].speedmask |= |
932 |
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL; |
933 |
/* Ensure devs attached before the initial reset go to the companion */
|
934 |
s->portsc[firstport + i] = PORTSC_POWNER; |
935 |
} |
936 |
|
937 |
s->companion_count++; |
938 |
s->mmio[0x05] = (s->companion_count << 4) | portcount; |
939 |
|
940 |
return 0; |
941 |
} |
942 |
|
943 |
static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
|
944 |
{ |
945 |
USBDevice *dev; |
946 |
USBPort *port; |
947 |
int i;
|
948 |
|
949 |
for (i = 0; i < NB_PORTS; i++) { |
950 |
port = &ehci->ports[i]; |
951 |
if (!(ehci->portsc[i] & PORTSC_PED)) {
|
952 |
DPRINTF("Port %d not enabled\n", i);
|
953 |
continue;
|
954 |
} |
955 |
dev = usb_find_device(port, addr); |
956 |
if (dev != NULL) { |
957 |
return dev;
|
958 |
} |
959 |
} |
960 |
return NULL; |
961 |
} |
962 |
|
963 |
/* 4.1 host controller initialization */
|
964 |
static void ehci_reset(void *opaque) |
965 |
{ |
966 |
EHCIState *s = opaque; |
967 |
int i;
|
968 |
USBDevice *devs[NB_PORTS]; |
969 |
|
970 |
trace_usb_ehci_reset(); |
971 |
|
972 |
/*
|
973 |
* Do the detach before touching portsc, so that it correctly gets send to
|
974 |
* us or to our companion based on PORTSC_POWNER before the reset.
|
975 |
*/
|
976 |
for(i = 0; i < NB_PORTS; i++) { |
977 |
devs[i] = s->ports[i].dev; |
978 |
if (devs[i] && devs[i]->attached) {
|
979 |
usb_detach(&s->ports[i]); |
980 |
} |
981 |
} |
982 |
|
983 |
memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
|
984 |
|
985 |
s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; |
986 |
s->usbsts = USBSTS_HALT; |
987 |
|
988 |
s->astate = EST_INACTIVE; |
989 |
s->pstate = EST_INACTIVE; |
990 |
|
991 |
for(i = 0; i < NB_PORTS; i++) { |
992 |
if (s->companion_ports[i]) {
|
993 |
s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; |
994 |
} else {
|
995 |
s->portsc[i] = PORTSC_PPOWER; |
996 |
} |
997 |
if (devs[i] && devs[i]->attached) {
|
998 |
usb_attach(&s->ports[i]); |
999 |
usb_device_reset(devs[i]); |
1000 |
} |
1001 |
} |
1002 |
ehci_queues_rip_all(s, 0);
|
1003 |
ehci_queues_rip_all(s, 1);
|
1004 |
qemu_del_timer(s->frame_timer); |
1005 |
qemu_bh_cancel(s->async_bh); |
1006 |
} |
1007 |
|
1008 |
static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr) |
1009 |
{ |
1010 |
EHCIState *s = ptr; |
1011 |
uint32_t val; |
1012 |
|
1013 |
val = s->mmio[addr]; |
1014 |
|
1015 |
return val;
|
1016 |
} |
1017 |
|
1018 |
static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr) |
1019 |
{ |
1020 |
EHCIState *s = ptr; |
1021 |
uint32_t val; |
1022 |
|
1023 |
val = s->mmio[addr] | (s->mmio[addr+1] << 8); |
1024 |
|
1025 |
return val;
|
1026 |
} |
1027 |
|
1028 |
static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr) |
1029 |
{ |
1030 |
EHCIState *s = ptr; |
1031 |
uint32_t val; |
1032 |
|
1033 |
val = s->mmio[addr] | (s->mmio[addr+1] << 8) | |
1034 |
(s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24); |
1035 |
|
1036 |
trace_usb_ehci_mmio_readl(addr, addr2str(addr), val); |
1037 |
return val;
|
1038 |
} |
1039 |
|
1040 |
static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val) |
1041 |
{ |
1042 |
fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
|
1043 |
exit(1);
|
1044 |
} |
1045 |
|
1046 |
static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val) |
1047 |
{ |
1048 |
fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
|
1049 |
exit(1);
|
1050 |
} |
1051 |
|
1052 |
static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner) |
1053 |
{ |
1054 |
USBDevice *dev = s->ports[port].dev; |
1055 |
uint32_t *portsc = &s->portsc[port]; |
1056 |
uint32_t orig; |
1057 |
|
1058 |
if (s->companion_ports[port] == NULL) |
1059 |
return;
|
1060 |
|
1061 |
owner = owner & PORTSC_POWNER; |
1062 |
orig = *portsc & PORTSC_POWNER; |
1063 |
|
1064 |
if (!(owner ^ orig)) {
|
1065 |
return;
|
1066 |
} |
1067 |
|
1068 |
if (dev && dev->attached) {
|
1069 |
usb_detach(&s->ports[port]); |
1070 |
} |
1071 |
|
1072 |
*portsc &= ~PORTSC_POWNER; |
1073 |
*portsc |= owner; |
1074 |
|
1075 |
if (dev && dev->attached) {
|
1076 |
usb_attach(&s->ports[port]); |
1077 |
} |
1078 |
} |
1079 |
|
1080 |
static void handle_port_status_write(EHCIState *s, int port, uint32_t val) |
1081 |
{ |
1082 |
uint32_t *portsc = &s->portsc[port]; |
1083 |
USBDevice *dev = s->ports[port].dev; |
1084 |
|
1085 |
/* Clear rwc bits */
|
1086 |
*portsc &= ~(val & PORTSC_RWC_MASK); |
1087 |
/* The guest may clear, but not set the PED bit */
|
1088 |
*portsc &= val | ~PORTSC_PED; |
1089 |
/* POWNER is masked out by RO_MASK as it is RO when we've no companion */
|
1090 |
handle_port_owner_write(s, port, val); |
1091 |
/* And finally apply RO_MASK */
|
1092 |
val &= PORTSC_RO_MASK; |
1093 |
|
1094 |
if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
|
1095 |
trace_usb_ehci_port_reset(port, 1);
|
1096 |
} |
1097 |
|
1098 |
if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
|
1099 |
trace_usb_ehci_port_reset(port, 0);
|
1100 |
if (dev && dev->attached) {
|
1101 |
usb_port_reset(&s->ports[port]); |
1102 |
*portsc &= ~PORTSC_CSC; |
1103 |
} |
1104 |
|
1105 |
/*
|
1106 |
* Table 2.16 Set the enable bit(and enable bit change) to indicate
|
1107 |
* to SW that this port has a high speed device attached
|
1108 |
*/
|
1109 |
if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
|
1110 |
val |= PORTSC_PED; |
1111 |
} |
1112 |
} |
1113 |
|
1114 |
*portsc &= ~PORTSC_RO_MASK; |
1115 |
*portsc |= val; |
1116 |
} |
1117 |
|
1118 |
static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val) |
1119 |
{ |
1120 |
EHCIState *s = ptr; |
1121 |
uint32_t *mmio = (uint32_t *)(&s->mmio[addr]); |
1122 |
uint32_t old = *mmio; |
1123 |
int i;
|
1124 |
|
1125 |
trace_usb_ehci_mmio_writel(addr, addr2str(addr), val); |
1126 |
|
1127 |
/* Only aligned reads are allowed on OHCI */
|
1128 |
if (addr & 3) { |
1129 |
fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
|
1130 |
TARGET_FMT_plx "\n", addr);
|
1131 |
return;
|
1132 |
} |
1133 |
|
1134 |
if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) { |
1135 |
handle_port_status_write(s, (addr-PORTSC)/4, val);
|
1136 |
trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); |
1137 |
return;
|
1138 |
} |
1139 |
|
1140 |
if (addr < OPREGBASE) {
|
1141 |
fprintf(stderr, "usb-ehci: write attempt to read-only register"
|
1142 |
TARGET_FMT_plx "\n", addr);
|
1143 |
return;
|
1144 |
} |
1145 |
|
1146 |
|
1147 |
/* Do any register specific pre-write processing here. */
|
1148 |
switch(addr) {
|
1149 |
case USBCMD:
|
1150 |
if (val & USBCMD_HCRESET) {
|
1151 |
ehci_reset(s); |
1152 |
val = s->usbcmd; |
1153 |
break;
|
1154 |
} |
1155 |
|
1156 |
if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=
|
1157 |
((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) { |
1158 |
if (s->pstate == EST_INACTIVE) {
|
1159 |
SET_LAST_RUN_CLOCK(s); |
1160 |
} |
1161 |
ehci_update_halt(s); |
1162 |
s->async_stepdown = 0;
|
1163 |
qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); |
1164 |
} |
1165 |
|
1166 |
/* not supporting dynamic frame list size at the moment */
|
1167 |
if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
|
1168 |
fprintf(stderr, "attempt to set frame list size -- value %d\n",
|
1169 |
val & USBCMD_FLS); |
1170 |
val &= ~USBCMD_FLS; |
1171 |
} |
1172 |
break;
|
1173 |
|
1174 |
case USBSTS:
|
1175 |
val &= USBSTS_RO_MASK; // bits 6 through 31 are RO
|
1176 |
ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC
|
1177 |
val = s->usbsts; |
1178 |
ehci_set_interrupt(s, 0);
|
1179 |
break;
|
1180 |
|
1181 |
case USBINTR:
|
1182 |
val &= USBINTR_MASK; |
1183 |
break;
|
1184 |
|
1185 |
case FRINDEX:
|
1186 |
val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */ |
1187 |
break;
|
1188 |
|
1189 |
case CONFIGFLAG:
|
1190 |
val &= 0x1;
|
1191 |
if (val) {
|
1192 |
for(i = 0; i < NB_PORTS; i++) |
1193 |
handle_port_owner_write(s, i, 0);
|
1194 |
} |
1195 |
break;
|
1196 |
|
1197 |
case PERIODICLISTBASE:
|
1198 |
if (ehci_periodic_enabled(s)) {
|
1199 |
fprintf(stderr, |
1200 |
"ehci: PERIODIC list base register set while periodic schedule\n"
|
1201 |
" is enabled and HC is enabled\n");
|
1202 |
} |
1203 |
break;
|
1204 |
|
1205 |
case ASYNCLISTADDR:
|
1206 |
if (ehci_async_enabled(s)) {
|
1207 |
fprintf(stderr, |
1208 |
"ehci: ASYNC list address register set while async schedule\n"
|
1209 |
" is enabled and HC is enabled\n");
|
1210 |
} |
1211 |
break;
|
1212 |
} |
1213 |
|
1214 |
*mmio = val; |
1215 |
trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); |
1216 |
} |
1217 |
|
1218 |
|
1219 |
// TODO : Put in common header file, duplication from usb-ohci.c
|
1220 |
|
1221 |
/* Get an array of dwords from main memory */
|
1222 |
static inline int get_dwords(EHCIState *ehci, uint32_t addr, |
1223 |
uint32_t *buf, int num)
|
1224 |
{ |
1225 |
int i;
|
1226 |
|
1227 |
for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
1228 |
pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf));
|
1229 |
*buf = le32_to_cpu(*buf); |
1230 |
} |
1231 |
|
1232 |
return 1; |
1233 |
} |
1234 |
|
1235 |
/* Put an array of dwords in to main memory */
|
1236 |
static inline int put_dwords(EHCIState *ehci, uint32_t addr, |
1237 |
uint32_t *buf, int num)
|
1238 |
{ |
1239 |
int i;
|
1240 |
|
1241 |
for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
1242 |
uint32_t tmp = cpu_to_le32(*buf); |
1243 |
pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp));
|
1244 |
} |
1245 |
|
1246 |
return 1; |
1247 |
} |
1248 |
|
1249 |
/*
|
1250 |
* Write the qh back to guest physical memory. This step isn't
|
1251 |
* in the EHCI spec but we need to do it since we don't share
|
1252 |
* physical memory with our guest VM.
|
1253 |
*
|
1254 |
* The first three dwords are read-only for the EHCI, so skip them
|
1255 |
* when writing back the qh.
|
1256 |
*/
|
1257 |
static void ehci_flush_qh(EHCIQueue *q) |
1258 |
{ |
1259 |
uint32_t *qh = (uint32_t *) &q->qh; |
1260 |
uint32_t dwords = sizeof(EHCIqh) >> 2; |
1261 |
uint32_t addr = NLPTR_GET(q->qhaddr); |
1262 |
|
1263 |
put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); |
1264 |
} |
1265 |
|
1266 |
// 4.10.2
|
1267 |
|
1268 |
static int ehci_qh_do_overlay(EHCIQueue *q) |
1269 |
{ |
1270 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
1271 |
int i;
|
1272 |
int dtoggle;
|
1273 |
int ping;
|
1274 |
int eps;
|
1275 |
int reload;
|
1276 |
|
1277 |
assert(p != NULL);
|
1278 |
assert(p->qtdaddr == q->qtdaddr); |
1279 |
|
1280 |
// remember values in fields to preserve in qh after overlay
|
1281 |
|
1282 |
dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; |
1283 |
ping = q->qh.token & QTD_TOKEN_PING; |
1284 |
|
1285 |
q->qh.current_qtd = p->qtdaddr; |
1286 |
q->qh.next_qtd = p->qtd.next; |
1287 |
q->qh.altnext_qtd = p->qtd.altnext; |
1288 |
q->qh.token = p->qtd.token; |
1289 |
|
1290 |
|
1291 |
eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); |
1292 |
if (eps == EHCI_QH_EPS_HIGH) {
|
1293 |
q->qh.token &= ~QTD_TOKEN_PING; |
1294 |
q->qh.token |= ping; |
1295 |
} |
1296 |
|
1297 |
reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1298 |
set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); |
1299 |
|
1300 |
for (i = 0; i < 5; i++) { |
1301 |
q->qh.bufptr[i] = p->qtd.bufptr[i]; |
1302 |
} |
1303 |
|
1304 |
if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
|
1305 |
// preserve QH DT bit
|
1306 |
q->qh.token &= ~QTD_TOKEN_DTOGGLE; |
1307 |
q->qh.token |= dtoggle; |
1308 |
} |
1309 |
|
1310 |
q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
|
1311 |
q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
|
1312 |
|
1313 |
ehci_flush_qh(q); |
1314 |
|
1315 |
return 0; |
1316 |
} |
1317 |
|
1318 |
static int ehci_init_transfer(EHCIPacket *p) |
1319 |
{ |
1320 |
uint32_t cpage, offset, bytes, plen; |
1321 |
dma_addr_t page; |
1322 |
|
1323 |
cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE); |
1324 |
bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES); |
1325 |
offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
|
1326 |
pci_dma_sglist_init(&p->sgl, &p->queue->ehci->dev, 5);
|
1327 |
|
1328 |
while (bytes > 0) { |
1329 |
if (cpage > 4) { |
1330 |
fprintf(stderr, "cpage out of range (%d)\n", cpage);
|
1331 |
return USB_RET_PROCERR;
|
1332 |
} |
1333 |
|
1334 |
page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK; |
1335 |
page += offset; |
1336 |
plen = bytes; |
1337 |
if (plen > 4096 - offset) { |
1338 |
plen = 4096 - offset;
|
1339 |
offset = 0;
|
1340 |
cpage++; |
1341 |
} |
1342 |
|
1343 |
qemu_sglist_add(&p->sgl, page, plen); |
1344 |
bytes -= plen; |
1345 |
} |
1346 |
return 0; |
1347 |
} |
1348 |
|
1349 |
static void ehci_finish_transfer(EHCIQueue *q, int status) |
1350 |
{ |
1351 |
uint32_t cpage, offset; |
1352 |
|
1353 |
if (status > 0) { |
1354 |
/* update cpage & offset */
|
1355 |
cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); |
1356 |
offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
|
1357 |
|
1358 |
offset += status; |
1359 |
cpage += offset >> QTD_BUFPTR_SH; |
1360 |
offset &= ~QTD_BUFPTR_MASK; |
1361 |
|
1362 |
set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); |
1363 |
q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
|
1364 |
q->qh.bufptr[0] |= offset;
|
1365 |
} |
1366 |
} |
1367 |
|
1368 |
static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) |
1369 |
{ |
1370 |
EHCIPacket *p; |
1371 |
EHCIState *s = port->opaque; |
1372 |
uint32_t portsc = s->portsc[port->index]; |
1373 |
|
1374 |
if (portsc & PORTSC_POWNER) {
|
1375 |
USBPort *companion = s->companion_ports[port->index]; |
1376 |
companion->ops->complete(companion, packet); |
1377 |
return;
|
1378 |
} |
1379 |
|
1380 |
p = container_of(packet, EHCIPacket, packet); |
1381 |
trace_usb_ehci_packet_action(p->queue, p, "wakeup");
|
1382 |
assert(p->async == EHCI_ASYNC_INFLIGHT); |
1383 |
p->async = EHCI_ASYNC_FINISHED; |
1384 |
p->usb_status = packet->result; |
1385 |
|
1386 |
if (p->queue->async) {
|
1387 |
qemu_bh_schedule(p->queue->ehci->async_bh); |
1388 |
} |
1389 |
} |
1390 |
|
1391 |
static void ehci_execute_complete(EHCIQueue *q) |
1392 |
{ |
1393 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
1394 |
|
1395 |
assert(p != NULL);
|
1396 |
assert(p->qtdaddr == q->qtdaddr); |
1397 |
assert(p->async != EHCI_ASYNC_INFLIGHT); |
1398 |
p->async = EHCI_ASYNC_NONE; |
1399 |
|
1400 |
DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
|
1401 |
q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status); |
1402 |
|
1403 |
if (p->usb_status < 0) { |
1404 |
switch (p->usb_status) {
|
1405 |
case USB_RET_IOERROR:
|
1406 |
case USB_RET_NODEV:
|
1407 |
q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); |
1408 |
set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
|
1409 |
ehci_record_interrupt(q->ehci, USBSTS_ERRINT); |
1410 |
break;
|
1411 |
case USB_RET_STALL:
|
1412 |
q->qh.token |= QTD_TOKEN_HALT; |
1413 |
ehci_record_interrupt(q->ehci, USBSTS_ERRINT); |
1414 |
break;
|
1415 |
case USB_RET_NAK:
|
1416 |
set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
|
1417 |
return; /* We're not done yet with this transaction */ |
1418 |
case USB_RET_BABBLE:
|
1419 |
q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); |
1420 |
ehci_record_interrupt(q->ehci, USBSTS_ERRINT); |
1421 |
break;
|
1422 |
default:
|
1423 |
/* should not be triggerable */
|
1424 |
fprintf(stderr, "USB invalid response %d\n", p->usb_status);
|
1425 |
assert(0);
|
1426 |
break;
|
1427 |
} |
1428 |
} else if ((p->usb_status > p->tbytes) && (p->pid == USB_TOKEN_IN)) { |
1429 |
p->usb_status = USB_RET_BABBLE; |
1430 |
q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); |
1431 |
ehci_record_interrupt(q->ehci, USBSTS_ERRINT); |
1432 |
} else {
|
1433 |
// TODO check 4.12 for splits
|
1434 |
|
1435 |
if (p->tbytes && p->pid == USB_TOKEN_IN) {
|
1436 |
p->tbytes -= p->usb_status; |
1437 |
} else {
|
1438 |
p->tbytes = 0;
|
1439 |
} |
1440 |
|
1441 |
DPRINTF("updating tbytes to %d\n", p->tbytes);
|
1442 |
set_field(&q->qh.token, p->tbytes, QTD_TOKEN_TBYTES); |
1443 |
} |
1444 |
ehci_finish_transfer(q, p->usb_status); |
1445 |
usb_packet_unmap(&p->packet, &p->sgl); |
1446 |
qemu_sglist_destroy(&p->sgl); |
1447 |
|
1448 |
q->qh.token ^= QTD_TOKEN_DTOGGLE; |
1449 |
q->qh.token &= ~QTD_TOKEN_ACTIVE; |
1450 |
|
1451 |
if (q->qh.token & QTD_TOKEN_IOC) {
|
1452 |
ehci_record_interrupt(q->ehci, USBSTS_INT); |
1453 |
} |
1454 |
} |
1455 |
|
1456 |
// 4.10.3
|
1457 |
|
1458 |
static int ehci_execute(EHCIPacket *p, const char *action) |
1459 |
{ |
1460 |
USBEndpoint *ep; |
1461 |
int ret;
|
1462 |
int endp;
|
1463 |
|
1464 |
if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) {
|
1465 |
fprintf(stderr, "Attempting to execute inactive qtd\n");
|
1466 |
return USB_RET_PROCERR;
|
1467 |
} |
1468 |
|
1469 |
p->tbytes = (p->qtd.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH; |
1470 |
if (p->tbytes > BUFF_SIZE) {
|
1471 |
fprintf(stderr, "Request for more bytes than allowed\n");
|
1472 |
return USB_RET_PROCERR;
|
1473 |
} |
1474 |
|
1475 |
p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH; |
1476 |
switch (p->pid) {
|
1477 |
case 0: |
1478 |
p->pid = USB_TOKEN_OUT; |
1479 |
break;
|
1480 |
case 1: |
1481 |
p->pid = USB_TOKEN_IN; |
1482 |
break;
|
1483 |
case 2: |
1484 |
p->pid = USB_TOKEN_SETUP; |
1485 |
break;
|
1486 |
default:
|
1487 |
fprintf(stderr, "bad token\n");
|
1488 |
break;
|
1489 |
} |
1490 |
|
1491 |
if (ehci_init_transfer(p) != 0) { |
1492 |
return USB_RET_PROCERR;
|
1493 |
} |
1494 |
|
1495 |
endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP); |
1496 |
ep = usb_ep_get(p->queue->dev, p->pid, endp); |
1497 |
|
1498 |
usb_packet_setup(&p->packet, p->pid, ep); |
1499 |
usb_packet_map(&p->packet, &p->sgl); |
1500 |
|
1501 |
trace_usb_ehci_packet_action(p->queue, p, action); |
1502 |
ret = usb_handle_packet(p->queue->dev, &p->packet); |
1503 |
DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
|
1504 |
"(total %d) endp %x ret %d\n",
|
1505 |
q->qhaddr, q->qh.next, q->qtdaddr, q->pid, |
1506 |
q->packet.iov.size, q->tbytes, endp, ret); |
1507 |
|
1508 |
if (ret > BUFF_SIZE) {
|
1509 |
fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
|
1510 |
return USB_RET_PROCERR;
|
1511 |
} |
1512 |
|
1513 |
return ret;
|
1514 |
} |
1515 |
|
1516 |
/* 4.7.2
|
1517 |
*/
|
1518 |
|
1519 |
static int ehci_process_itd(EHCIState *ehci, |
1520 |
EHCIitd *itd) |
1521 |
{ |
1522 |
USBDevice *dev; |
1523 |
USBEndpoint *ep; |
1524 |
int ret;
|
1525 |
uint32_t i, len, pid, dir, devaddr, endp; |
1526 |
uint32_t pg, off, ptr1, ptr2, max, mult; |
1527 |
|
1528 |
dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
|
1529 |
devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
|
1530 |
endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
|
1531 |
max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
|
1532 |
mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
|
1533 |
|
1534 |
for(i = 0; i < 8; i++) { |
1535 |
if (itd->transact[i] & ITD_XACT_ACTIVE) {
|
1536 |
pg = get_field(itd->transact[i], ITD_XACT_PGSEL); |
1537 |
off = itd->transact[i] & ITD_XACT_OFFSET_MASK; |
1538 |
ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); |
1539 |
ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
|
1540 |
len = get_field(itd->transact[i], ITD_XACT_LENGTH); |
1541 |
|
1542 |
if (len > max * mult) {
|
1543 |
len = max * mult; |
1544 |
} |
1545 |
|
1546 |
if (len > BUFF_SIZE) {
|
1547 |
return USB_RET_PROCERR;
|
1548 |
} |
1549 |
|
1550 |
pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2);
|
1551 |
if (off + len > 4096) { |
1552 |
/* transfer crosses page border */
|
1553 |
uint32_t len2 = off + len - 4096;
|
1554 |
uint32_t len1 = len - len2; |
1555 |
qemu_sglist_add(&ehci->isgl, ptr1 + off, len1); |
1556 |
qemu_sglist_add(&ehci->isgl, ptr2, len2); |
1557 |
} else {
|
1558 |
qemu_sglist_add(&ehci->isgl, ptr1 + off, len); |
1559 |
} |
1560 |
|
1561 |
pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT; |
1562 |
|
1563 |
dev = ehci_find_device(ehci, devaddr); |
1564 |
ep = usb_ep_get(dev, pid, endp); |
1565 |
if (ep->type == USB_ENDPOINT_XFER_ISOC) {
|
1566 |
usb_packet_setup(&ehci->ipacket, pid, ep); |
1567 |
usb_packet_map(&ehci->ipacket, &ehci->isgl); |
1568 |
ret = usb_handle_packet(dev, &ehci->ipacket); |
1569 |
assert(ret != USB_RET_ASYNC); |
1570 |
usb_packet_unmap(&ehci->ipacket, &ehci->isgl); |
1571 |
} else {
|
1572 |
DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
|
1573 |
ret = USB_RET_NAK; |
1574 |
} |
1575 |
qemu_sglist_destroy(&ehci->isgl); |
1576 |
|
1577 |
if (ret < 0) { |
1578 |
switch (ret) {
|
1579 |
default:
|
1580 |
fprintf(stderr, "Unexpected iso usb result: %d\n", ret);
|
1581 |
/* Fall through */
|
1582 |
case USB_RET_IOERROR:
|
1583 |
case USB_RET_NODEV:
|
1584 |
/* 3.3.2: XACTERR is only allowed on IN transactions */
|
1585 |
if (dir) {
|
1586 |
itd->transact[i] |= ITD_XACT_XACTERR; |
1587 |
ehci_record_interrupt(ehci, USBSTS_ERRINT); |
1588 |
} |
1589 |
break;
|
1590 |
case USB_RET_BABBLE:
|
1591 |
itd->transact[i] |= ITD_XACT_BABBLE; |
1592 |
ehci_record_interrupt(ehci, USBSTS_ERRINT); |
1593 |
break;
|
1594 |
case USB_RET_NAK:
|
1595 |
/* no data for us, so do a zero-length transfer */
|
1596 |
ret = 0;
|
1597 |
break;
|
1598 |
} |
1599 |
} |
1600 |
if (ret >= 0) { |
1601 |
if (!dir) {
|
1602 |
/* OUT */
|
1603 |
set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH); |
1604 |
} else {
|
1605 |
/* IN */
|
1606 |
set_field(&itd->transact[i], ret, ITD_XACT_LENGTH); |
1607 |
} |
1608 |
} |
1609 |
if (itd->transact[i] & ITD_XACT_IOC) {
|
1610 |
ehci_record_interrupt(ehci, USBSTS_INT); |
1611 |
} |
1612 |
itd->transact[i] &= ~ITD_XACT_ACTIVE; |
1613 |
} |
1614 |
} |
1615 |
return 0; |
1616 |
} |
1617 |
|
1618 |
|
1619 |
/* This state is the entry point for asynchronous schedule
|
1620 |
* processing. Entry here consitutes a EHCI start event state (4.8.5)
|
1621 |
*/
|
1622 |
static int ehci_state_waitlisthead(EHCIState *ehci, int async) |
1623 |
{ |
1624 |
EHCIqh qh; |
1625 |
int i = 0; |
1626 |
int again = 0; |
1627 |
uint32_t entry = ehci->asynclistaddr; |
1628 |
|
1629 |
/* set reclamation flag at start event (4.8.6) */
|
1630 |
if (async) {
|
1631 |
ehci_set_usbsts(ehci, USBSTS_REC); |
1632 |
} |
1633 |
|
1634 |
ehci_queues_rip_unused(ehci, async, 0);
|
1635 |
|
1636 |
/* Find the head of the list (4.9.1.1) */
|
1637 |
for(i = 0; i < MAX_QH; i++) { |
1638 |
get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh, |
1639 |
sizeof(EHCIqh) >> 2); |
1640 |
ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
|
1641 |
|
1642 |
if (qh.epchar & QH_EPCHAR_H) {
|
1643 |
if (async) {
|
1644 |
entry |= (NLPTR_TYPE_QH << 1);
|
1645 |
} |
1646 |
|
1647 |
ehci_set_fetch_addr(ehci, async, entry); |
1648 |
ehci_set_state(ehci, async, EST_FETCHENTRY); |
1649 |
again = 1;
|
1650 |
goto out;
|
1651 |
} |
1652 |
|
1653 |
entry = qh.next; |
1654 |
if (entry == ehci->asynclistaddr) {
|
1655 |
break;
|
1656 |
} |
1657 |
} |
1658 |
|
1659 |
/* no head found for list. */
|
1660 |
|
1661 |
ehci_set_state(ehci, async, EST_ACTIVE); |
1662 |
|
1663 |
out:
|
1664 |
return again;
|
1665 |
} |
1666 |
|
1667 |
|
1668 |
/* This state is the entry point for periodic schedule processing as
|
1669 |
* well as being a continuation state for async processing.
|
1670 |
*/
|
1671 |
static int ehci_state_fetchentry(EHCIState *ehci, int async) |
1672 |
{ |
1673 |
int again = 0; |
1674 |
uint32_t entry = ehci_get_fetch_addr(ehci, async); |
1675 |
|
1676 |
if (NLPTR_TBIT(entry)) {
|
1677 |
ehci_set_state(ehci, async, EST_ACTIVE); |
1678 |
goto out;
|
1679 |
} |
1680 |
|
1681 |
/* section 4.8, only QH in async schedule */
|
1682 |
if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
|
1683 |
fprintf(stderr, "non queue head request in async schedule\n");
|
1684 |
return -1; |
1685 |
} |
1686 |
|
1687 |
switch (NLPTR_TYPE_GET(entry)) {
|
1688 |
case NLPTR_TYPE_QH:
|
1689 |
ehci_set_state(ehci, async, EST_FETCHQH); |
1690 |
again = 1;
|
1691 |
break;
|
1692 |
|
1693 |
case NLPTR_TYPE_ITD:
|
1694 |
ehci_set_state(ehci, async, EST_FETCHITD); |
1695 |
again = 1;
|
1696 |
break;
|
1697 |
|
1698 |
case NLPTR_TYPE_STITD:
|
1699 |
ehci_set_state(ehci, async, EST_FETCHSITD); |
1700 |
again = 1;
|
1701 |
break;
|
1702 |
|
1703 |
default:
|
1704 |
/* TODO: handle FSTN type */
|
1705 |
fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
|
1706 |
"which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
|
1707 |
return -1; |
1708 |
} |
1709 |
|
1710 |
out:
|
1711 |
return again;
|
1712 |
} |
1713 |
|
1714 |
static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) |
1715 |
{ |
1716 |
EHCIPacket *p; |
1717 |
uint32_t entry, devaddr; |
1718 |
EHCIQueue *q; |
1719 |
|
1720 |
entry = ehci_get_fetch_addr(ehci, async); |
1721 |
q = ehci_find_queue_by_qh(ehci, entry, async); |
1722 |
if (NULL == q) { |
1723 |
q = ehci_alloc_queue(ehci, entry, async); |
1724 |
} |
1725 |
p = QTAILQ_FIRST(&q->packets); |
1726 |
|
1727 |
q->seen++; |
1728 |
if (q->seen > 1) { |
1729 |
/* we are going in circles -- stop processing */
|
1730 |
ehci_set_state(ehci, async, EST_ACTIVE); |
1731 |
q = NULL;
|
1732 |
goto out;
|
1733 |
} |
1734 |
|
1735 |
get_dwords(ehci, NLPTR_GET(q->qhaddr), |
1736 |
(uint32_t *) &q->qh, sizeof(EHCIqh) >> 2); |
1737 |
ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh); |
1738 |
|
1739 |
devaddr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR); |
1740 |
if (q->dev != NULL && q->dev->addr != devaddr) { |
1741 |
if (!QTAILQ_EMPTY(&q->packets)) {
|
1742 |
/* should not happen (guest bug) */
|
1743 |
while ((p = QTAILQ_FIRST(&q->packets)) != NULL) { |
1744 |
ehci_free_packet(p); |
1745 |
} |
1746 |
} |
1747 |
q->dev = NULL;
|
1748 |
} |
1749 |
if (q->dev == NULL) { |
1750 |
q->dev = ehci_find_device(q->ehci, devaddr); |
1751 |
} |
1752 |
|
1753 |
if (p && p->async == EHCI_ASYNC_INFLIGHT) {
|
1754 |
/* I/O still in progress -- skip queue */
|
1755 |
ehci_set_state(ehci, async, EST_HORIZONTALQH); |
1756 |
goto out;
|
1757 |
} |
1758 |
if (p && p->async == EHCI_ASYNC_FINISHED) {
|
1759 |
/* I/O finished -- continue processing queue */
|
1760 |
trace_usb_ehci_packet_action(p->queue, p, "complete");
|
1761 |
ehci_set_state(ehci, async, EST_EXECUTING); |
1762 |
goto out;
|
1763 |
} |
1764 |
|
1765 |
if (async && (q->qh.epchar & QH_EPCHAR_H)) {
|
1766 |
|
1767 |
/* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
|
1768 |
if (ehci->usbsts & USBSTS_REC) {
|
1769 |
ehci_clear_usbsts(ehci, USBSTS_REC); |
1770 |
} else {
|
1771 |
DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
|
1772 |
" - done processing\n", q->qhaddr);
|
1773 |
ehci_set_state(ehci, async, EST_ACTIVE); |
1774 |
q = NULL;
|
1775 |
goto out;
|
1776 |
} |
1777 |
} |
1778 |
|
1779 |
#if EHCI_DEBUG
|
1780 |
if (q->qhaddr != q->qh.next) {
|
1781 |
DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
|
1782 |
q->qhaddr, |
1783 |
q->qh.epchar & QH_EPCHAR_H, |
1784 |
q->qh.token & QTD_TOKEN_HALT, |
1785 |
q->qh.token & QTD_TOKEN_ACTIVE, |
1786 |
q->qh.next); |
1787 |
} |
1788 |
#endif
|
1789 |
|
1790 |
if (q->qh.token & QTD_TOKEN_HALT) {
|
1791 |
ehci_set_state(ehci, async, EST_HORIZONTALQH); |
1792 |
|
1793 |
} else if ((q->qh.token & QTD_TOKEN_ACTIVE) && |
1794 |
(NLPTR_TBIT(q->qh.current_qtd) == 0)) {
|
1795 |
q->qtdaddr = q->qh.current_qtd; |
1796 |
ehci_set_state(ehci, async, EST_FETCHQTD); |
1797 |
|
1798 |
} else {
|
1799 |
/* EHCI spec version 1.0 Section 4.10.2 */
|
1800 |
ehci_set_state(ehci, async, EST_ADVANCEQUEUE); |
1801 |
} |
1802 |
|
1803 |
out:
|
1804 |
return q;
|
1805 |
} |
1806 |
|
1807 |
static int ehci_state_fetchitd(EHCIState *ehci, int async) |
1808 |
{ |
1809 |
uint32_t entry; |
1810 |
EHCIitd itd; |
1811 |
|
1812 |
assert(!async); |
1813 |
entry = ehci_get_fetch_addr(ehci, async); |
1814 |
|
1815 |
get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
1816 |
sizeof(EHCIitd) >> 2); |
1817 |
ehci_trace_itd(ehci, entry, &itd); |
1818 |
|
1819 |
if (ehci_process_itd(ehci, &itd) != 0) { |
1820 |
return -1; |
1821 |
} |
1822 |
|
1823 |
put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
1824 |
sizeof(EHCIitd) >> 2); |
1825 |
ehci_set_fetch_addr(ehci, async, itd.next); |
1826 |
ehci_set_state(ehci, async, EST_FETCHENTRY); |
1827 |
|
1828 |
return 1; |
1829 |
} |
1830 |
|
1831 |
static int ehci_state_fetchsitd(EHCIState *ehci, int async) |
1832 |
{ |
1833 |
uint32_t entry; |
1834 |
EHCIsitd sitd; |
1835 |
|
1836 |
assert(!async); |
1837 |
entry = ehci_get_fetch_addr(ehci, async); |
1838 |
|
1839 |
get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd, |
1840 |
sizeof(EHCIsitd) >> 2); |
1841 |
ehci_trace_sitd(ehci, entry, &sitd); |
1842 |
|
1843 |
if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
|
1844 |
/* siTD is not active, nothing to do */;
|
1845 |
} else {
|
1846 |
/* TODO: split transfers are not implemented */
|
1847 |
fprintf(stderr, "WARNING: Skipping active siTD\n");
|
1848 |
} |
1849 |
|
1850 |
ehci_set_fetch_addr(ehci, async, sitd.next); |
1851 |
ehci_set_state(ehci, async, EST_FETCHENTRY); |
1852 |
return 1; |
1853 |
} |
1854 |
|
1855 |
/* Section 4.10.2 - paragraph 3 */
|
1856 |
static int ehci_state_advqueue(EHCIQueue *q) |
1857 |
{ |
1858 |
#if 0
|
1859 |
/* TO-DO: 4.10.2 - paragraph 2
|
1860 |
* if I-bit is set to 1 and QH is not active
|
1861 |
* go to horizontal QH
|
1862 |
*/
|
1863 |
if (I-bit set) {
|
1864 |
ehci_set_state(ehci, async, EST_HORIZONTALQH);
|
1865 |
goto out;
|
1866 |
}
|
1867 |
#endif
|
1868 |
|
1869 |
/*
|
1870 |
* want data and alt-next qTD is valid
|
1871 |
*/
|
1872 |
if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && |
1873 |
(NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
|
1874 |
q->qtdaddr = q->qh.altnext_qtd; |
1875 |
ehci_set_state(q->ehci, q->async, EST_FETCHQTD); |
1876 |
|
1877 |
/*
|
1878 |
* next qTD is valid
|
1879 |
*/
|
1880 |
} else if (NLPTR_TBIT(q->qh.next_qtd) == 0) { |
1881 |
q->qtdaddr = q->qh.next_qtd; |
1882 |
ehci_set_state(q->ehci, q->async, EST_FETCHQTD); |
1883 |
|
1884 |
/*
|
1885 |
* no valid qTD, try next QH
|
1886 |
*/
|
1887 |
} else {
|
1888 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
1889 |
} |
1890 |
|
1891 |
return 1; |
1892 |
} |
1893 |
|
1894 |
/* Section 4.10.2 - paragraph 4 */
|
1895 |
static int ehci_state_fetchqtd(EHCIQueue *q) |
1896 |
{ |
1897 |
EHCIqtd qtd; |
1898 |
EHCIPacket *p; |
1899 |
int again = 0; |
1900 |
|
1901 |
get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd, |
1902 |
sizeof(EHCIqtd) >> 2); |
1903 |
ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd); |
1904 |
|
1905 |
p = QTAILQ_FIRST(&q->packets); |
1906 |
while (p != NULL && p->qtdaddr != q->qtdaddr) { |
1907 |
/* should not happen (guest bug) */
|
1908 |
ehci_free_packet(p); |
1909 |
p = QTAILQ_FIRST(&q->packets); |
1910 |
} |
1911 |
if (p != NULL) { |
1912 |
ehci_qh_do_overlay(q); |
1913 |
ehci_flush_qh(q); |
1914 |
if (p->async == EHCI_ASYNC_INFLIGHT) {
|
1915 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
1916 |
} else {
|
1917 |
ehci_set_state(q->ehci, q->async, EST_EXECUTING); |
1918 |
} |
1919 |
again = 1;
|
1920 |
} else if (qtd.token & QTD_TOKEN_ACTIVE) { |
1921 |
p = ehci_alloc_packet(q); |
1922 |
p->qtdaddr = q->qtdaddr; |
1923 |
p->qtd = qtd; |
1924 |
ehci_set_state(q->ehci, q->async, EST_EXECUTE); |
1925 |
again = 1;
|
1926 |
} else {
|
1927 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
1928 |
again = 1;
|
1929 |
} |
1930 |
|
1931 |
return again;
|
1932 |
} |
1933 |
|
1934 |
static int ehci_state_horizqh(EHCIQueue *q) |
1935 |
{ |
1936 |
int again = 0; |
1937 |
|
1938 |
if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {
|
1939 |
ehci_set_fetch_addr(q->ehci, q->async, q->qh.next); |
1940 |
ehci_set_state(q->ehci, q->async, EST_FETCHENTRY); |
1941 |
again = 1;
|
1942 |
} else {
|
1943 |
ehci_set_state(q->ehci, q->async, EST_ACTIVE); |
1944 |
} |
1945 |
|
1946 |
return again;
|
1947 |
} |
1948 |
|
1949 |
static void ehci_fill_queue(EHCIPacket *p) |
1950 |
{ |
1951 |
EHCIQueue *q = p->queue; |
1952 |
EHCIqtd qtd = p->qtd; |
1953 |
uint32_t qtdaddr; |
1954 |
|
1955 |
for (;;) {
|
1956 |
if (NLPTR_TBIT(qtd.altnext) == 0) { |
1957 |
break;
|
1958 |
} |
1959 |
if (NLPTR_TBIT(qtd.next) != 0) { |
1960 |
break;
|
1961 |
} |
1962 |
qtdaddr = qtd.next; |
1963 |
get_dwords(q->ehci, NLPTR_GET(qtdaddr), |
1964 |
(uint32_t *) &qtd, sizeof(EHCIqtd) >> 2); |
1965 |
ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd); |
1966 |
if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
|
1967 |
break;
|
1968 |
} |
1969 |
p = ehci_alloc_packet(q); |
1970 |
p->qtdaddr = qtdaddr; |
1971 |
p->qtd = qtd; |
1972 |
p->usb_status = ehci_execute(p, "queue");
|
1973 |
assert(p->usb_status = USB_RET_ASYNC); |
1974 |
p->async = EHCI_ASYNC_INFLIGHT; |
1975 |
} |
1976 |
} |
1977 |
|
1978 |
static int ehci_state_execute(EHCIQueue *q) |
1979 |
{ |
1980 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
1981 |
int again = 0; |
1982 |
|
1983 |
assert(p != NULL);
|
1984 |
assert(p->qtdaddr == q->qtdaddr); |
1985 |
|
1986 |
if (ehci_qh_do_overlay(q) != 0) { |
1987 |
return -1; |
1988 |
} |
1989 |
|
1990 |
// TODO verify enough time remains in the uframe as in 4.4.1.1
|
1991 |
// TODO write back ptr to async list when done or out of time
|
1992 |
// TODO Windows does not seem to ever set the MULT field
|
1993 |
|
1994 |
if (!q->async) {
|
1995 |
int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
|
1996 |
if (!transactCtr) {
|
1997 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
1998 |
again = 1;
|
1999 |
goto out;
|
2000 |
} |
2001 |
} |
2002 |
|
2003 |
if (q->async) {
|
2004 |
ehci_set_usbsts(q->ehci, USBSTS_REC); |
2005 |
} |
2006 |
|
2007 |
p->usb_status = ehci_execute(p, "process");
|
2008 |
if (p->usb_status == USB_RET_PROCERR) {
|
2009 |
again = -1;
|
2010 |
goto out;
|
2011 |
} |
2012 |
if (p->usb_status == USB_RET_ASYNC) {
|
2013 |
ehci_flush_qh(q); |
2014 |
trace_usb_ehci_packet_action(p->queue, p, "async");
|
2015 |
p->async = EHCI_ASYNC_INFLIGHT; |
2016 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
2017 |
again = 1;
|
2018 |
ehci_fill_queue(p); |
2019 |
goto out;
|
2020 |
} |
2021 |
|
2022 |
ehci_set_state(q->ehci, q->async, EST_EXECUTING); |
2023 |
again = 1;
|
2024 |
|
2025 |
out:
|
2026 |
return again;
|
2027 |
} |
2028 |
|
2029 |
static int ehci_state_executing(EHCIQueue *q) |
2030 |
{ |
2031 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
2032 |
int again = 0; |
2033 |
|
2034 |
assert(p != NULL);
|
2035 |
assert(p->qtdaddr == q->qtdaddr); |
2036 |
|
2037 |
ehci_execute_complete(q); |
2038 |
if (p->usb_status == USB_RET_ASYNC) {
|
2039 |
goto out;
|
2040 |
} |
2041 |
if (p->usb_status == USB_RET_PROCERR) {
|
2042 |
again = -1;
|
2043 |
goto out;
|
2044 |
} |
2045 |
|
2046 |
// 4.10.3
|
2047 |
if (!q->async) {
|
2048 |
int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
|
2049 |
transactCtr--; |
2050 |
set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT); |
2051 |
// 4.10.3, bottom of page 82, should exit this state when transaction
|
2052 |
// counter decrements to 0
|
2053 |
} |
2054 |
|
2055 |
/* 4.10.5 */
|
2056 |
if (p->usb_status == USB_RET_NAK) {
|
2057 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
2058 |
} else {
|
2059 |
ehci_set_state(q->ehci, q->async, EST_WRITEBACK); |
2060 |
} |
2061 |
|
2062 |
again = 1;
|
2063 |
|
2064 |
out:
|
2065 |
ehci_flush_qh(q); |
2066 |
return again;
|
2067 |
} |
2068 |
|
2069 |
|
2070 |
static int ehci_state_writeback(EHCIQueue *q) |
2071 |
{ |
2072 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
2073 |
uint32_t *qtd, addr; |
2074 |
int again = 0; |
2075 |
|
2076 |
/* Write back the QTD from the QH area */
|
2077 |
assert(p != NULL);
|
2078 |
assert(p->qtdaddr == q->qtdaddr); |
2079 |
|
2080 |
ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd); |
2081 |
qtd = (uint32_t *) &q->qh.next_qtd; |
2082 |
addr = NLPTR_GET(p->qtdaddr); |
2083 |
put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2); |
2084 |
ehci_free_packet(p); |
2085 |
|
2086 |
/*
|
2087 |
* EHCI specs say go horizontal here.
|
2088 |
*
|
2089 |
* We can also advance the queue here for performance reasons. We
|
2090 |
* need to take care to only take that shortcut in case we've
|
2091 |
* processed the qtd just written back without errors, i.e. halt
|
2092 |
* bit is clear.
|
2093 |
*/
|
2094 |
if (q->qh.token & QTD_TOKEN_HALT) {
|
2095 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
2096 |
again = 1;
|
2097 |
} else {
|
2098 |
ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE); |
2099 |
again = 1;
|
2100 |
} |
2101 |
return again;
|
2102 |
} |
2103 |
|
2104 |
/*
|
2105 |
* This is the state machine that is common to both async and periodic
|
2106 |
*/
|
2107 |
|
2108 |
static void ehci_advance_state(EHCIState *ehci, int async) |
2109 |
{ |
2110 |
EHCIQueue *q = NULL;
|
2111 |
int again;
|
2112 |
|
2113 |
do {
|
2114 |
switch(ehci_get_state(ehci, async)) {
|
2115 |
case EST_WAITLISTHEAD:
|
2116 |
again = ehci_state_waitlisthead(ehci, async); |
2117 |
break;
|
2118 |
|
2119 |
case EST_FETCHENTRY:
|
2120 |
again = ehci_state_fetchentry(ehci, async); |
2121 |
break;
|
2122 |
|
2123 |
case EST_FETCHQH:
|
2124 |
q = ehci_state_fetchqh(ehci, async); |
2125 |
if (q != NULL) { |
2126 |
assert(q->async == async); |
2127 |
again = 1;
|
2128 |
} else {
|
2129 |
again = 0;
|
2130 |
} |
2131 |
break;
|
2132 |
|
2133 |
case EST_FETCHITD:
|
2134 |
again = ehci_state_fetchitd(ehci, async); |
2135 |
break;
|
2136 |
|
2137 |
case EST_FETCHSITD:
|
2138 |
again = ehci_state_fetchsitd(ehci, async); |
2139 |
break;
|
2140 |
|
2141 |
case EST_ADVANCEQUEUE:
|
2142 |
again = ehci_state_advqueue(q); |
2143 |
break;
|
2144 |
|
2145 |
case EST_FETCHQTD:
|
2146 |
again = ehci_state_fetchqtd(q); |
2147 |
break;
|
2148 |
|
2149 |
case EST_HORIZONTALQH:
|
2150 |
again = ehci_state_horizqh(q); |
2151 |
break;
|
2152 |
|
2153 |
case EST_EXECUTE:
|
2154 |
again = ehci_state_execute(q); |
2155 |
if (async) {
|
2156 |
ehci->async_stepdown = 0;
|
2157 |
} |
2158 |
break;
|
2159 |
|
2160 |
case EST_EXECUTING:
|
2161 |
assert(q != NULL);
|
2162 |
if (async) {
|
2163 |
ehci->async_stepdown = 0;
|
2164 |
} |
2165 |
again = ehci_state_executing(q); |
2166 |
break;
|
2167 |
|
2168 |
case EST_WRITEBACK:
|
2169 |
assert(q != NULL);
|
2170 |
again = ehci_state_writeback(q); |
2171 |
break;
|
2172 |
|
2173 |
default:
|
2174 |
fprintf(stderr, "Bad state!\n");
|
2175 |
again = -1;
|
2176 |
assert(0);
|
2177 |
break;
|
2178 |
} |
2179 |
|
2180 |
if (again < 0) { |
2181 |
fprintf(stderr, "processing error - resetting ehci HC\n");
|
2182 |
ehci_reset(ehci); |
2183 |
again = 0;
|
2184 |
} |
2185 |
} |
2186 |
while (again);
|
2187 |
|
2188 |
ehci_commit_interrupt(ehci); |
2189 |
} |
2190 |
|
2191 |
static void ehci_advance_async_state(EHCIState *ehci) |
2192 |
{ |
2193 |
const int async = 1; |
2194 |
|
2195 |
switch(ehci_get_state(ehci, async)) {
|
2196 |
case EST_INACTIVE:
|
2197 |
if (!ehci_async_enabled(ehci)) {
|
2198 |
break;
|
2199 |
} |
2200 |
ehci_set_state(ehci, async, EST_ACTIVE); |
2201 |
// No break, fall through to ACTIVE
|
2202 |
|
2203 |
case EST_ACTIVE:
|
2204 |
if (!ehci_async_enabled(ehci)) {
|
2205 |
ehci_queues_rip_all(ehci, async); |
2206 |
ehci_set_state(ehci, async, EST_INACTIVE); |
2207 |
break;
|
2208 |
} |
2209 |
|
2210 |
/* make sure guest has acknowledged the doorbell interrupt */
|
2211 |
/* TO-DO: is this really needed? */
|
2212 |
if (ehci->usbsts & USBSTS_IAA) {
|
2213 |
DPRINTF("IAA status bit still set.\n");
|
2214 |
break;
|
2215 |
} |
2216 |
|
2217 |
/* check that address register has been set */
|
2218 |
if (ehci->asynclistaddr == 0) { |
2219 |
break;
|
2220 |
} |
2221 |
|
2222 |
ehci_set_state(ehci, async, EST_WAITLISTHEAD); |
2223 |
ehci_advance_state(ehci, async); |
2224 |
|
2225 |
/* If the doorbell is set, the guest wants to make a change to the
|
2226 |
* schedule. The host controller needs to release cached data.
|
2227 |
* (section 4.8.2)
|
2228 |
*/
|
2229 |
if (ehci->usbcmd & USBCMD_IAAD) {
|
2230 |
/* Remove all unseen qhs from the async qhs queue */
|
2231 |
ehci_queues_rip_unused(ehci, async, 1);
|
2232 |
DPRINTF("ASYNC: doorbell request acknowledged\n");
|
2233 |
ehci->usbcmd &= ~USBCMD_IAAD; |
2234 |
ehci_set_interrupt(ehci, USBSTS_IAA); |
2235 |
} |
2236 |
break;
|
2237 |
|
2238 |
default:
|
2239 |
/* this should only be due to a developer mistake */
|
2240 |
fprintf(stderr, "ehci: Bad asynchronous state %d. "
|
2241 |
"Resetting to active\n", ehci->astate);
|
2242 |
assert(0);
|
2243 |
} |
2244 |
} |
2245 |
|
2246 |
static void ehci_advance_periodic_state(EHCIState *ehci) |
2247 |
{ |
2248 |
uint32_t entry; |
2249 |
uint32_t list; |
2250 |
const int async = 0; |
2251 |
|
2252 |
// 4.6
|
2253 |
|
2254 |
switch(ehci_get_state(ehci, async)) {
|
2255 |
case EST_INACTIVE:
|
2256 |
if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) { |
2257 |
ehci_set_state(ehci, async, EST_ACTIVE); |
2258 |
// No break, fall through to ACTIVE
|
2259 |
} else
|
2260 |
break;
|
2261 |
|
2262 |
case EST_ACTIVE:
|
2263 |
if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) { |
2264 |
ehci_queues_rip_all(ehci, async); |
2265 |
ehci_set_state(ehci, async, EST_INACTIVE); |
2266 |
break;
|
2267 |
} |
2268 |
|
2269 |
list = ehci->periodiclistbase & 0xfffff000;
|
2270 |
/* check that register has been set */
|
2271 |
if (list == 0) { |
2272 |
break;
|
2273 |
} |
2274 |
list |= ((ehci->frindex & 0x1ff8) >> 1); |
2275 |
|
2276 |
pci_dma_read(&ehci->dev, list, &entry, sizeof entry);
|
2277 |
entry = le32_to_cpu(entry); |
2278 |
|
2279 |
DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
|
2280 |
ehci->frindex / 8, list, entry);
|
2281 |
ehci_set_fetch_addr(ehci, async,entry); |
2282 |
ehci_set_state(ehci, async, EST_FETCHENTRY); |
2283 |
ehci_advance_state(ehci, async); |
2284 |
ehci_queues_rip_unused(ehci, async, 0);
|
2285 |
break;
|
2286 |
|
2287 |
default:
|
2288 |
/* this should only be due to a developer mistake */
|
2289 |
fprintf(stderr, "ehci: Bad periodic state %d. "
|
2290 |
"Resetting to active\n", ehci->pstate);
|
2291 |
assert(0);
|
2292 |
} |
2293 |
} |
2294 |
|
2295 |
static void ehci_update_frindex(EHCIState *ehci, int frames) |
2296 |
{ |
2297 |
int i;
|
2298 |
|
2299 |
if (!ehci_enabled(ehci)) {
|
2300 |
return;
|
2301 |
} |
2302 |
|
2303 |
for (i = 0; i < frames; i++) { |
2304 |
ehci->frindex += 8;
|
2305 |
|
2306 |
if (ehci->frindex == 0x00002000) { |
2307 |
ehci_set_interrupt(ehci, USBSTS_FLR); |
2308 |
} |
2309 |
|
2310 |
if (ehci->frindex == 0x00004000) { |
2311 |
ehci_set_interrupt(ehci, USBSTS_FLR); |
2312 |
ehci->frindex = 0;
|
2313 |
} |
2314 |
} |
2315 |
} |
2316 |
|
2317 |
static void ehci_frame_timer(void *opaque) |
2318 |
{ |
2319 |
EHCIState *ehci = opaque; |
2320 |
int schedules = 0; |
2321 |
int64_t expire_time, t_now; |
2322 |
uint64_t ns_elapsed; |
2323 |
int frames, skipped_frames;
|
2324 |
int i;
|
2325 |
|
2326 |
t_now = qemu_get_clock_ns(vm_clock); |
2327 |
ns_elapsed = t_now - ehci->last_run_ns; |
2328 |
frames = ns_elapsed / FRAME_TIMER_NS; |
2329 |
|
2330 |
if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) {
|
2331 |
schedules++; |
2332 |
expire_time = t_now + (get_ticks_per_sec() / FRAME_TIMER_FREQ); |
2333 |
|
2334 |
if (frames > ehci->maxframes) {
|
2335 |
skipped_frames = frames - ehci->maxframes; |
2336 |
ehci_update_frindex(ehci, skipped_frames); |
2337 |
ehci->last_run_ns += FRAME_TIMER_NS * skipped_frames; |
2338 |
frames -= skipped_frames; |
2339 |
DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
|
2340 |
} |
2341 |
|
2342 |
for (i = 0; i < frames; i++) { |
2343 |
ehci_update_frindex(ehci, 1);
|
2344 |
ehci_advance_periodic_state(ehci); |
2345 |
ehci->last_run_ns += FRAME_TIMER_NS; |
2346 |
} |
2347 |
} else {
|
2348 |
if (ehci->async_stepdown < ehci->maxframes / 2) { |
2349 |
ehci->async_stepdown++; |
2350 |
} |
2351 |
expire_time = t_now + (get_ticks_per_sec() |
2352 |
* ehci->async_stepdown / FRAME_TIMER_FREQ); |
2353 |
ehci_update_frindex(ehci, frames); |
2354 |
ehci->last_run_ns += FRAME_TIMER_NS * frames; |
2355 |
} |
2356 |
|
2357 |
/* Async is not inside loop since it executes everything it can once
|
2358 |
* called
|
2359 |
*/
|
2360 |
if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) {
|
2361 |
schedules++; |
2362 |
qemu_bh_schedule(ehci->async_bh); |
2363 |
} |
2364 |
|
2365 |
if (schedules) {
|
2366 |
qemu_mod_timer(ehci->frame_timer, expire_time); |
2367 |
} |
2368 |
} |
2369 |
|
2370 |
static void ehci_async_bh(void *opaque) |
2371 |
{ |
2372 |
EHCIState *ehci = opaque; |
2373 |
ehci_advance_async_state(ehci); |
2374 |
} |
2375 |
|
2376 |
static const MemoryRegionOps ehci_mem_ops = { |
2377 |
.old_mmio = { |
2378 |
.read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl }, |
2379 |
.write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel }, |
2380 |
}, |
2381 |
.endianness = DEVICE_LITTLE_ENDIAN, |
2382 |
}; |
2383 |
|
2384 |
static int usb_ehci_initfn(PCIDevice *dev); |
2385 |
|
2386 |
static USBPortOps ehci_port_ops = {
|
2387 |
.attach = ehci_attach, |
2388 |
.detach = ehci_detach, |
2389 |
.child_detach = ehci_child_detach, |
2390 |
.wakeup = ehci_wakeup, |
2391 |
.complete = ehci_async_complete_packet, |
2392 |
}; |
2393 |
|
2394 |
static USBBusOps ehci_bus_ops = {
|
2395 |
.register_companion = ehci_register_companion, |
2396 |
}; |
2397 |
|
2398 |
static int usb_ehci_post_load(void *opaque, int version_id) |
2399 |
{ |
2400 |
EHCIState *s = opaque; |
2401 |
int i;
|
2402 |
|
2403 |
for (i = 0; i < NB_PORTS; i++) { |
2404 |
USBPort *companion = s->companion_ports[i]; |
2405 |
if (companion == NULL) { |
2406 |
continue;
|
2407 |
} |
2408 |
if (s->portsc[i] & PORTSC_POWNER) {
|
2409 |
companion->dev = s->ports[i].dev; |
2410 |
} else {
|
2411 |
companion->dev = NULL;
|
2412 |
} |
2413 |
} |
2414 |
|
2415 |
return 0; |
2416 |
} |
2417 |
|
2418 |
static const VMStateDescription vmstate_ehci = { |
2419 |
.name = "ehci",
|
2420 |
.version_id = 1,
|
2421 |
.post_load = usb_ehci_post_load, |
2422 |
.fields = (VMStateField[]) { |
2423 |
VMSTATE_PCI_DEVICE(dev, EHCIState), |
2424 |
/* mmio registers */
|
2425 |
VMSTATE_UINT32(usbcmd, EHCIState), |
2426 |
VMSTATE_UINT32(usbsts, EHCIState), |
2427 |
VMSTATE_UINT32(usbintr, EHCIState), |
2428 |
VMSTATE_UINT32(frindex, EHCIState), |
2429 |
VMSTATE_UINT32(ctrldssegment, EHCIState), |
2430 |
VMSTATE_UINT32(periodiclistbase, EHCIState), |
2431 |
VMSTATE_UINT32(asynclistaddr, EHCIState), |
2432 |
VMSTATE_UINT32(configflag, EHCIState), |
2433 |
VMSTATE_UINT32(portsc[0], EHCIState),
|
2434 |
VMSTATE_UINT32(portsc[1], EHCIState),
|
2435 |
VMSTATE_UINT32(portsc[2], EHCIState),
|
2436 |
VMSTATE_UINT32(portsc[3], EHCIState),
|
2437 |
VMSTATE_UINT32(portsc[4], EHCIState),
|
2438 |
VMSTATE_UINT32(portsc[5], EHCIState),
|
2439 |
/* frame timer */
|
2440 |
VMSTATE_TIMER(frame_timer, EHCIState), |
2441 |
VMSTATE_UINT64(last_run_ns, EHCIState), |
2442 |
VMSTATE_UINT32(async_stepdown, EHCIState), |
2443 |
/* schedule state */
|
2444 |
VMSTATE_UINT32(astate, EHCIState), |
2445 |
VMSTATE_UINT32(pstate, EHCIState), |
2446 |
VMSTATE_UINT32(a_fetch_addr, EHCIState), |
2447 |
VMSTATE_UINT32(p_fetch_addr, EHCIState), |
2448 |
VMSTATE_END_OF_LIST() |
2449 |
} |
2450 |
}; |
2451 |
|
2452 |
static Property ehci_properties[] = {
|
2453 |
DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), |
2454 |
DEFINE_PROP_END_OF_LIST(), |
2455 |
}; |
2456 |
|
2457 |
static void ehci_class_init(ObjectClass *klass, void *data) |
2458 |
{ |
2459 |
DeviceClass *dc = DEVICE_CLASS(klass); |
2460 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2461 |
|
2462 |
k->init = usb_ehci_initfn; |
2463 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
2464 |
k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */
|
2465 |
k->revision = 0x10;
|
2466 |
k->class_id = PCI_CLASS_SERIAL_USB; |
2467 |
dc->vmsd = &vmstate_ehci; |
2468 |
dc->props = ehci_properties; |
2469 |
} |
2470 |
|
2471 |
static TypeInfo ehci_info = {
|
2472 |
.name = "usb-ehci",
|
2473 |
.parent = TYPE_PCI_DEVICE, |
2474 |
.instance_size = sizeof(EHCIState),
|
2475 |
.class_init = ehci_class_init, |
2476 |
}; |
2477 |
|
2478 |
static void ich9_ehci_class_init(ObjectClass *klass, void *data) |
2479 |
{ |
2480 |
DeviceClass *dc = DEVICE_CLASS(klass); |
2481 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2482 |
|
2483 |
k->init = usb_ehci_initfn; |
2484 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
2485 |
k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1; |
2486 |
k->revision = 0x03;
|
2487 |
k->class_id = PCI_CLASS_SERIAL_USB; |
2488 |
dc->vmsd = &vmstate_ehci; |
2489 |
dc->props = ehci_properties; |
2490 |
} |
2491 |
|
2492 |
static TypeInfo ich9_ehci_info = {
|
2493 |
.name = "ich9-usb-ehci1",
|
2494 |
.parent = TYPE_PCI_DEVICE, |
2495 |
.instance_size = sizeof(EHCIState),
|
2496 |
.class_init = ich9_ehci_class_init, |
2497 |
}; |
2498 |
|
2499 |
static int usb_ehci_initfn(PCIDevice *dev) |
2500 |
{ |
2501 |
EHCIState *s = DO_UPCAST(EHCIState, dev, dev); |
2502 |
uint8_t *pci_conf = s->dev.config; |
2503 |
int i;
|
2504 |
|
2505 |
pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
|
2506 |
|
2507 |
/* capabilities pointer */
|
2508 |
pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
|
2509 |
//pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
|
2510 |
|
2511 |
pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ |
2512 |
pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
|
2513 |
pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
|
2514 |
|
2515 |
// pci_conf[0x50] = 0x01; // power management caps
|
2516 |
|
2517 |
pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4)
|
2518 |
pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5) |
2519 |
pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6) |
2520 |
|
2521 |
pci_conf[0x64] = 0x00; |
2522 |
pci_conf[0x65] = 0x00; |
2523 |
pci_conf[0x66] = 0x00; |
2524 |
pci_conf[0x67] = 0x00; |
2525 |
pci_conf[0x68] = 0x01; |
2526 |
pci_conf[0x69] = 0x00; |
2527 |
pci_conf[0x6a] = 0x00; |
2528 |
pci_conf[0x6b] = 0x00; // USBLEGSUP |
2529 |
pci_conf[0x6c] = 0x00; |
2530 |
pci_conf[0x6d] = 0x00; |
2531 |
pci_conf[0x6e] = 0x00; |
2532 |
pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS |
2533 |
|
2534 |
// 2.2 host controller interface version
|
2535 |
s->mmio[0x00] = (uint8_t) OPREGBASE;
|
2536 |
s->mmio[0x01] = 0x00; |
2537 |
s->mmio[0x02] = 0x00; |
2538 |
s->mmio[0x03] = 0x01; // HC version |
2539 |
s->mmio[0x04] = NB_PORTS; // Number of downstream ports |
2540 |
s->mmio[0x05] = 0x00; // No companion ports at present |
2541 |
s->mmio[0x06] = 0x00; |
2542 |
s->mmio[0x07] = 0x00; |
2543 |
s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable |
2544 |
s->mmio[0x09] = 0x68; // EECP |
2545 |
s->mmio[0x0a] = 0x00; |
2546 |
s->mmio[0x0b] = 0x00; |
2547 |
|
2548 |
s->irq = s->dev.irq[3];
|
2549 |
|
2550 |
usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); |
2551 |
for(i = 0; i < NB_PORTS; i++) { |
2552 |
usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, |
2553 |
USB_SPEED_MASK_HIGH); |
2554 |
s->ports[i].dev = 0;
|
2555 |
} |
2556 |
|
2557 |
s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); |
2558 |
s->async_bh = qemu_bh_new(ehci_async_bh, s); |
2559 |
QTAILQ_INIT(&s->aqueues); |
2560 |
QTAILQ_INIT(&s->pqueues); |
2561 |
|
2562 |
qemu_register_reset(ehci_reset, s); |
2563 |
|
2564 |
memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE);
|
2565 |
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
|
2566 |
|
2567 |
return 0; |
2568 |
} |
2569 |
|
2570 |
static void ehci_register_types(void) |
2571 |
{ |
2572 |
type_register_static(&ehci_info); |
2573 |
type_register_static(&ich9_ehci_info); |
2574 |
} |
2575 |
|
2576 |
type_init(ehci_register_types) |
2577 |
|
2578 |
/*
|
2579 |
* vim: expandtab ts=4
|
2580 |
*/
|