Revision 4f7403d5 target-s390x/translate.c
| b/target-s390x/translate.c | ||
|---|---|---|
| 1012 | 1012 |
} |
| 1013 | 1013 |
} |
| 1014 | 1014 |
|
| 1015 |
static void gen_op_clc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2) |
|
| 1016 |
{
|
|
| 1017 |
TCGv_i64 tmp; |
|
| 1018 |
TCGv_i64 tmp2; |
|
| 1019 |
TCGv_i32 vl; |
|
| 1020 |
|
|
| 1021 |
/* check for simple 32bit or 64bit match */ |
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| 1022 |
switch (l) {
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|
| 1023 |
case 0: |
|
| 1024 |
tmp = tcg_temp_new_i64(); |
|
| 1025 |
tmp2 = tcg_temp_new_i64(); |
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| 1026 |
|
|
| 1027 |
tcg_gen_qemu_ld8u(tmp, s1, get_mem_index(s)); |
|
| 1028 |
tcg_gen_qemu_ld8u(tmp2, s2, get_mem_index(s)); |
|
| 1029 |
cmp_u64(s, tmp, tmp2); |
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| 1030 |
|
|
| 1031 |
tcg_temp_free_i64(tmp); |
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| 1032 |
tcg_temp_free_i64(tmp2); |
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| 1033 |
return; |
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| 1034 |
case 1: |
|
| 1035 |
tmp = tcg_temp_new_i64(); |
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| 1036 |
tmp2 = tcg_temp_new_i64(); |
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| 1037 |
|
|
| 1038 |
tcg_gen_qemu_ld16u(tmp, s1, get_mem_index(s)); |
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| 1039 |
tcg_gen_qemu_ld16u(tmp2, s2, get_mem_index(s)); |
|
| 1040 |
cmp_u64(s, tmp, tmp2); |
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| 1041 |
|
|
| 1042 |
tcg_temp_free_i64(tmp); |
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| 1043 |
tcg_temp_free_i64(tmp2); |
|
| 1044 |
return; |
|
| 1045 |
case 3: |
|
| 1046 |
tmp = tcg_temp_new_i64(); |
|
| 1047 |
tmp2 = tcg_temp_new_i64(); |
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| 1048 |
|
|
| 1049 |
tcg_gen_qemu_ld32u(tmp, s1, get_mem_index(s)); |
|
| 1050 |
tcg_gen_qemu_ld32u(tmp2, s2, get_mem_index(s)); |
|
| 1051 |
cmp_u64(s, tmp, tmp2); |
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| 1052 |
|
|
| 1053 |
tcg_temp_free_i64(tmp); |
|
| 1054 |
tcg_temp_free_i64(tmp2); |
|
| 1055 |
return; |
|
| 1056 |
case 7: |
|
| 1057 |
tmp = tcg_temp_new_i64(); |
|
| 1058 |
tmp2 = tcg_temp_new_i64(); |
|
| 1059 |
|
|
| 1060 |
tcg_gen_qemu_ld64(tmp, s1, get_mem_index(s)); |
|
| 1061 |
tcg_gen_qemu_ld64(tmp2, s2, get_mem_index(s)); |
|
| 1062 |
cmp_u64(s, tmp, tmp2); |
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| 1063 |
|
|
| 1064 |
tcg_temp_free_i64(tmp); |
|
| 1065 |
tcg_temp_free_i64(tmp2); |
|
| 1066 |
return; |
|
| 1067 |
} |
|
| 1068 |
|
|
| 1069 |
potential_page_fault(s); |
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| 1070 |
vl = tcg_const_i32(l); |
|
| 1071 |
gen_helper_clc(cc_op, cpu_env, vl, s1, s2); |
|
| 1072 |
tcg_temp_free_i32(vl); |
|
| 1073 |
set_cc_static(s); |
|
| 1074 |
} |
|
| 1075 |
|
|
| 1076 | 1015 |
static void disas_e3(CPUS390XState *env, DisasContext* s, int op, int r1, |
| 1077 | 1016 |
int x2, int b2, int d2) |
| 1078 | 1017 |
{
|
| ... | ... | |
| 2200 | 2139 |
tcg_temp_free_i32(tmp32_1); |
| 2201 | 2140 |
tcg_temp_free_i32(tmp32_2); |
| 2202 | 2141 |
break; |
| 2203 |
case 0xd5: /* CLC D1(L,B1),D2(B2) [SS] */ |
|
| 2204 |
insn = ld_code6(env, s->pc); |
|
| 2205 |
b1 = (insn >> 28) & 0xf; |
|
| 2206 |
b2 = (insn >> 12) & 0xf; |
|
| 2207 |
d1 = (insn >> 16) & 0xfff; |
|
| 2208 |
d2 = insn & 0xfff; |
|
| 2209 |
tmp = get_address(s, 0, b1, d1); |
|
| 2210 |
tmp2 = get_address(s, 0, b2, d2); |
|
| 2211 |
gen_op_clc(s, (insn >> 32) & 0xff, tmp, tmp2); |
|
| 2212 |
tcg_temp_free_i64(tmp); |
|
| 2213 |
tcg_temp_free_i64(tmp2); |
|
| 2214 |
break; |
|
| 2215 | 2142 |
#ifndef CONFIG_USER_ONLY |
| 2216 | 2143 |
case 0xda: /* MVCP D1(R1,B1),D2(B2),R3 [SS] */ |
| 2217 | 2144 |
case 0xdb: /* MVCS D1(R1,B1),D2(B2),R3 [SS] */ |
| ... | ... | |
| 2797 | 2724 |
return help_branch(s, &c, is_imm, imm, o->in2); |
| 2798 | 2725 |
} |
| 2799 | 2726 |
|
| 2727 |
static ExitStatus op_clc(DisasContext *s, DisasOps *o) |
|
| 2728 |
{
|
|
| 2729 |
int l = get_field(s->fields, l1); |
|
| 2730 |
TCGv_i32 vl; |
|
| 2731 |
|
|
| 2732 |
switch (l + 1) {
|
|
| 2733 |
case 1: |
|
| 2734 |
tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s)); |
|
| 2735 |
tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s)); |
|
| 2736 |
break; |
|
| 2737 |
case 2: |
|
| 2738 |
tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s)); |
|
| 2739 |
tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s)); |
|
| 2740 |
break; |
|
| 2741 |
case 4: |
|
| 2742 |
tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s)); |
|
| 2743 |
tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s)); |
|
| 2744 |
break; |
|
| 2745 |
case 8: |
|
| 2746 |
tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s)); |
|
| 2747 |
tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s)); |
|
| 2748 |
break; |
|
| 2749 |
default: |
|
| 2750 |
potential_page_fault(s); |
|
| 2751 |
vl = tcg_const_i32(l); |
|
| 2752 |
gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2); |
|
| 2753 |
tcg_temp_free_i32(vl); |
|
| 2754 |
set_cc_static(s); |
|
| 2755 |
return NO_EXIT; |
|
| 2756 |
} |
|
| 2757 |
gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst); |
|
| 2758 |
return NO_EXIT; |
|
| 2759 |
} |
|
| 2760 |
|
|
| 2800 | 2761 |
static ExitStatus op_clcle(DisasContext *s, DisasOps *o) |
| 2801 | 2762 |
{
|
| 2802 | 2763 |
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); |
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