Revision 4fa5d772
| b/vl.c | ||
|---|---|---|
| 2328 | 2328 |
int i; |
| 2329 | 2329 |
uint32_t tmp; |
| 2330 | 2330 |
|
| 2331 |
for(i = 1; i < 8; i++) |
|
| 2332 |
qemu_put_be32s(f, &env->gregs[i]); |
|
| 2333 |
tmp = env->regwptr - env->regbase; |
|
| 2334 |
qemu_put_be32s(f, &tmp); |
|
| 2335 |
for(i = 1; i < NWINDOWS * 16 + 8; i++) |
|
| 2336 |
qemu_put_be32s(f, &env->regbase[i]); |
|
| 2331 |
for(i = 0; i < 8; i++) |
|
| 2332 |
qemu_put_betls(f, &env->gregs[i]); |
|
| 2333 |
for(i = 0; i < NWINDOWS * 16; i++) |
|
| 2334 |
qemu_put_betls(f, &env->regbase[i]); |
|
| 2337 | 2335 |
|
| 2338 | 2336 |
/* FPU */ |
| 2339 |
for(i = 0; i < 32; i++) {
|
|
| 2340 |
uint64_t mant; |
|
| 2341 |
uint16_t exp; |
|
| 2342 |
cpu_get_fp64(&mant, &exp, env->fpr[i]); |
|
| 2343 |
qemu_put_be64(f, mant); |
|
| 2344 |
qemu_put_be16(f, exp); |
|
| 2345 |
} |
|
| 2346 |
qemu_put_be32s(f, &env->pc); |
|
| 2347 |
qemu_put_be32s(f, &env->npc); |
|
| 2348 |
qemu_put_be32s(f, &env->y); |
|
| 2337 |
for(i = 0; i < TARGET_FPREGS; i++) {
|
|
| 2338 |
union {
|
|
| 2339 |
TARGET_FPREG_T f; |
|
| 2340 |
target_ulong i; |
|
| 2341 |
} u; |
|
| 2342 |
u.f = env->fpr[i]; |
|
| 2343 |
qemu_put_betl(f, u.i); |
|
| 2344 |
} |
|
| 2345 |
|
|
| 2346 |
qemu_put_betls(f, &env->pc); |
|
| 2347 |
qemu_put_betls(f, &env->npc); |
|
| 2348 |
qemu_put_betls(f, &env->y); |
|
| 2349 | 2349 |
tmp = GET_PSR(env); |
| 2350 |
qemu_put_be32s(f, &tmp);
|
|
| 2350 |
qemu_put_be32(f, tmp);
|
|
| 2351 | 2351 |
qemu_put_be32s(f, &env->fsr); |
| 2352 |
qemu_put_be32s(f, &env->cwp); |
|
| 2353 | 2352 |
qemu_put_be32s(f, &env->wim); |
| 2354 | 2353 |
qemu_put_be32s(f, &env->tbr); |
| 2355 | 2354 |
/* MMU */ |
| ... | ... | |
| 2363 | 2362 |
int i; |
| 2364 | 2363 |
uint32_t tmp; |
| 2365 | 2364 |
|
| 2366 |
for(i = 1; i < 8; i++) |
|
| 2367 |
qemu_get_be32s(f, &env->gregs[i]); |
|
| 2368 |
qemu_get_be32s(f, &tmp); |
|
| 2369 |
env->regwptr = env->regbase + tmp; |
|
| 2370 |
for(i = 1; i < NWINDOWS * 16 + 8; i++) |
|
| 2371 |
qemu_get_be32s(f, &env->regbase[i]); |
|
| 2365 |
for(i = 0; i < 8; i++) |
|
| 2366 |
qemu_get_betls(f, &env->gregs[i]); |
|
| 2367 |
for(i = 0; i < NWINDOWS * 16; i++) |
|
| 2368 |
qemu_get_betls(f, &env->regbase[i]); |
|
| 2372 | 2369 |
|
| 2373 | 2370 |
/* FPU */ |
| 2374 |
for(i = 0; i < 32; i++) {
|
|
| 2375 |
uint64_t mant; |
|
| 2376 |
uint16_t exp; |
|
| 2377 |
|
|
| 2378 |
qemu_get_be64s(f, &mant); |
|
| 2379 |
qemu_get_be16s(f, &exp); |
|
| 2380 |
env->fpr[i] = cpu_put_fp64(mant, exp); |
|
| 2381 |
} |
|
| 2382 |
qemu_get_be32s(f, &env->pc); |
|
| 2383 |
qemu_get_be32s(f, &env->npc); |
|
| 2384 |
qemu_get_be32s(f, &env->y); |
|
| 2385 |
qemu_get_be32s(f, &tmp); |
|
| 2371 |
for(i = 0; i < TARGET_FPREGS; i++) {
|
|
| 2372 |
union {
|
|
| 2373 |
TARGET_FPREG_T f; |
|
| 2374 |
target_ulong i; |
|
| 2375 |
} u; |
|
| 2376 |
u.i = qemu_get_betl(f); |
|
| 2377 |
env->fpr[i] = u.f; |
|
| 2378 |
} |
|
| 2379 |
|
|
| 2380 |
qemu_get_betls(f, &env->pc); |
|
| 2381 |
qemu_get_betls(f, &env->npc); |
|
| 2382 |
qemu_get_betls(f, &env->y); |
|
| 2383 |
tmp = qemu_get_be32(f); |
|
| 2384 |
env->cwp = 0; /* needed to ensure that the wrapping registers are |
|
| 2385 |
correctly updated */ |
|
| 2386 | 2386 |
PUT_PSR(env, tmp); |
| 2387 | 2387 |
qemu_get_be32s(f, &env->fsr); |
| 2388 |
qemu_get_be32s(f, &env->cwp); |
|
| 2389 | 2388 |
qemu_get_be32s(f, &env->wim); |
| 2390 | 2389 |
qemu_get_be32s(f, &env->tbr); |
| 2391 | 2390 |
/* MMU */ |
| 2392 | 2391 |
for(i = 0; i < 16; i++) |
| 2393 | 2392 |
qemu_get_be32s(f, &env->mmuregs[i]); |
| 2393 |
|
|
| 2394 | 2394 |
tlb_flush(env, 1); |
| 2395 | 2395 |
return 0; |
| 2396 | 2396 |
} |
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