root / hw / usb / hcd-ehci.c @ 5010d4dc
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/*
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* QEMU USB EHCI Emulation
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*
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* Copyright(c) 2008 Emutex Ltd. (address@hidden)
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* Copyright(c) 2011-2012 Red Hat, Inc.
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*
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* Red Hat Authors:
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* Gerd Hoffmann <kraxel@redhat.com>
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* Hans de Goede <hdegoede@redhat.com>
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*
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* EHCI project was started by Mark Burkley, with contributions by
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* Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
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* Jan Kiszka and Vincent Palatin contributed bugfixes.
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*
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or(at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/hw.h" |
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#include "qemu-timer.h" |
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#include "hw/usb.h" |
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#include "hw/pci.h" |
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#include "monitor.h" |
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#include "trace.h" |
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#include "dma.h" |
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#include "sysemu.h" |
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#define EHCI_DEBUG 0 |
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|
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#if EHCI_DEBUG
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#define DPRINTF printf
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#else
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#define DPRINTF(...)
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#endif
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/* internal processing - reset HC to try and recover */
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#define USB_RET_PROCERR (-99) |
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|
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#define MMIO_SIZE 0x1000 |
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#define CAPA_SIZE 0x10 |
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|
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/* Capability Registers Base Address - section 2.2 */
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#define CAPLENGTH 0x0000 /* 1-byte, 0x0001 reserved */ |
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#define HCIVERSION 0x0002 /* 2-bytes, i/f version # */ |
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#define HCSPARAMS 0x0004 /* 4-bytes, structural params */ |
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#define HCCPARAMS 0x0008 /* 4-bytes, capability params */ |
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#define EECP HCCPARAMS + 1 |
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#define HCSPPORTROUTE1 0x000c |
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#define HCSPPORTROUTE2 0x0010 |
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|
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#define USBCMD 0x0000 |
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#define USBCMD_RUNSTOP (1 << 0) // run / Stop |
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#define USBCMD_HCRESET (1 << 1) // HC Reset |
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#define USBCMD_FLS (3 << 2) // Frame List Size |
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#define USBCMD_FLS_SH 2 // Frame List Size Shift |
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#define USBCMD_PSE (1 << 4) // Periodic Schedule Enable |
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#define USBCMD_ASE (1 << 5) // Asynch Schedule Enable |
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#define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell |
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#define USBCMD_LHCR (1 << 7) // Light Host Controller Reset |
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#define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count |
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#define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable |
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#define USBCMD_ITC (0x7f << 16) // Int Threshold Control |
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#define USBCMD_ITC_SH 16 // Int Threshold Control Shift |
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|
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#define USBSTS 0x0004 |
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#define USBSTS_RO_MASK 0x0000003f |
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#define USBSTS_INT (1 << 0) // USB Interrupt |
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#define USBSTS_ERRINT (1 << 1) // Error Interrupt |
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#define USBSTS_PCD (1 << 2) // Port Change Detect |
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#define USBSTS_FLR (1 << 3) // Frame List Rollover |
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#define USBSTS_HSE (1 << 4) // Host System Error |
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#define USBSTS_IAA (1 << 5) // Interrupt on Async Advance |
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#define USBSTS_HALT (1 << 12) // HC Halted |
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#define USBSTS_REC (1 << 13) // Reclamation |
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#define USBSTS_PSS (1 << 14) // Periodic Schedule Status |
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#define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status |
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/*
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* Interrupt enable bits correspond to the interrupt active bits in USBSTS
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* so no need to redefine here.
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*/
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#define USBINTR 0x0008 |
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#define USBINTR_MASK 0x0000003f |
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#define FRINDEX 0x000c |
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#define CTRLDSSEGMENT 0x0010 |
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#define PERIODICLISTBASE 0x0014 |
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#define ASYNCLISTADDR 0x0018 |
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#define ASYNCLISTADDR_MASK 0xffffffe0 |
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|
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#define CONFIGFLAG 0x0040 |
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#define PORTSC 0x0044 |
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#define PORTSC_BEGIN PORTSC
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#define PORTSC_END (PORTSC + 4 * NB_PORTS) |
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/*
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* Bits that are reserved or are read-only are masked out of values
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* written to us by software
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*/
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#define PORTSC_RO_MASK 0x007001c0 |
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#define PORTSC_RWC_MASK 0x0000002a |
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#define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable |
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#define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable |
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#define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable |
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#define PORTSC_PTC (15 << 16) // Port Test Control |
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#define PORTSC_PTC_SH 16 // Port Test Control shift |
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#define PORTSC_PIC (3 << 14) // Port Indicator Control |
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#define PORTSC_PIC_SH 14 // Port Indicator Control Shift |
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#define PORTSC_POWNER (1 << 13) // Port Owner |
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#define PORTSC_PPOWER (1 << 12) // Port Power |
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#define PORTSC_LINESTAT (3 << 10) // Port Line Status |
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#define PORTSC_LINESTAT_SH 10 // Port Line Status Shift |
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#define PORTSC_PRESET (1 << 8) // Port Reset |
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#define PORTSC_SUSPEND (1 << 7) // Port Suspend |
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#define PORTSC_FPRES (1 << 6) // Force Port Resume |
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#define PORTSC_OCC (1 << 5) // Over Current Change |
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#define PORTSC_OCA (1 << 4) // Over Current Active |
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#define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change |
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#define PORTSC_PED (1 << 2) // Port Enable/Disable |
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#define PORTSC_CSC (1 << 1) // Connect Status Change |
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#define PORTSC_CONNECT (1 << 0) // Current Connect Status |
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#define FRAME_TIMER_FREQ 1000 |
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#define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) |
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#define NB_MAXINTRATE 8 // Max rate at which controller issues ints |
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#define NB_PORTS 6 // Number of downstream ports |
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#define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction |
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#define MAX_QH 100 // Max allowable queue heads in a chain |
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#define MIN_FR_PER_TICK 3 // Min frames to process when catching up |
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/* Internal periodic / asynchronous schedule state machine states
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*/
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typedef enum { |
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EST_INACTIVE = 1000,
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EST_ACTIVE, |
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EST_EXECUTING, |
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EST_SLEEPING, |
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/* The following states are internal to the state machine function
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*/
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EST_WAITLISTHEAD, |
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EST_FETCHENTRY, |
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EST_FETCHQH, |
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EST_FETCHITD, |
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EST_FETCHSITD, |
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EST_ADVANCEQUEUE, |
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EST_FETCHQTD, |
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EST_EXECUTE, |
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EST_WRITEBACK, |
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EST_HORIZONTALQH |
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} EHCI_STATES; |
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/* macros for accessing fields within next link pointer entry */
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#define NLPTR_GET(x) ((x) & 0xffffffe0) |
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#define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) |
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#define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid |
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/* link pointer types */
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#define NLPTR_TYPE_ITD 0 // isoc xfer descriptor |
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#define NLPTR_TYPE_QH 1 // queue head |
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#define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor |
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#define NLPTR_TYPE_FSTN 3 // frame span traversal node |
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/* EHCI spec version 1.0 Section 3.3
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*/
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typedef struct EHCIitd { |
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uint32_t next; |
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uint32_t transact[8];
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#define ITD_XACT_ACTIVE (1 << 31) |
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#define ITD_XACT_DBERROR (1 << 30) |
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#define ITD_XACT_BABBLE (1 << 29) |
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#define ITD_XACT_XACTERR (1 << 28) |
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#define ITD_XACT_LENGTH_MASK 0x0fff0000 |
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#define ITD_XACT_LENGTH_SH 16 |
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#define ITD_XACT_IOC (1 << 15) |
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#define ITD_XACT_PGSEL_MASK 0x00007000 |
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#define ITD_XACT_PGSEL_SH 12 |
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#define ITD_XACT_OFFSET_MASK 0x00000fff |
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uint32_t bufptr[7];
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#define ITD_BUFPTR_MASK 0xfffff000 |
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#define ITD_BUFPTR_SH 12 |
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#define ITD_BUFPTR_EP_MASK 0x00000f00 |
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#define ITD_BUFPTR_EP_SH 8 |
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#define ITD_BUFPTR_DEVADDR_MASK 0x0000007f |
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#define ITD_BUFPTR_DEVADDR_SH 0 |
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#define ITD_BUFPTR_DIRECTION (1 << 11) |
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#define ITD_BUFPTR_MAXPKT_MASK 0x000007ff |
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#define ITD_BUFPTR_MAXPKT_SH 0 |
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#define ITD_BUFPTR_MULT_MASK 0x00000003 |
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#define ITD_BUFPTR_MULT_SH 0 |
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} EHCIitd; |
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/* EHCI spec version 1.0 Section 3.4
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*/
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typedef struct EHCIsitd { |
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uint32_t next; // Standard next link pointer
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uint32_t epchar; |
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#define SITD_EPCHAR_IO (1 << 31) |
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#define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 |
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#define SITD_EPCHAR_PORTNUM_SH 24 |
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#define SITD_EPCHAR_HUBADD_MASK 0x007f0000 |
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#define SITD_EPCHAR_HUBADDR_SH 16 |
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#define SITD_EPCHAR_EPNUM_MASK 0x00000f00 |
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#define SITD_EPCHAR_EPNUM_SH 8 |
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#define SITD_EPCHAR_DEVADDR_MASK 0x0000007f |
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|
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uint32_t uframe; |
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#define SITD_UFRAME_CMASK_MASK 0x0000ff00 |
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#define SITD_UFRAME_CMASK_SH 8 |
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#define SITD_UFRAME_SMASK_MASK 0x000000ff |
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|
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uint32_t results; |
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#define SITD_RESULTS_IOC (1 << 31) |
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#define SITD_RESULTS_PGSEL (1 << 30) |
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#define SITD_RESULTS_TBYTES_MASK 0x03ff0000 |
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#define SITD_RESULTS_TYBYTES_SH 16 |
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#define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 |
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#define SITD_RESULTS_CPROGMASK_SH 8 |
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#define SITD_RESULTS_ACTIVE (1 << 7) |
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#define SITD_RESULTS_ERR (1 << 6) |
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#define SITD_RESULTS_DBERR (1 << 5) |
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#define SITD_RESULTS_BABBLE (1 << 4) |
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#define SITD_RESULTS_XACTERR (1 << 3) |
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#define SITD_RESULTS_MISSEDUF (1 << 2) |
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#define SITD_RESULTS_SPLITXSTATE (1 << 1) |
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uint32_t bufptr[2];
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#define SITD_BUFPTR_MASK 0xfffff000 |
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#define SITD_BUFPTR_CURROFF_MASK 0x00000fff |
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#define SITD_BUFPTR_TPOS_MASK 0x00000018 |
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#define SITD_BUFPTR_TPOS_SH 3 |
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#define SITD_BUFPTR_TCNT_MASK 0x00000007 |
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uint32_t backptr; // Standard next link pointer
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} EHCIsitd; |
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/* EHCI spec version 1.0 Section 3.5
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*/
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typedef struct EHCIqtd { |
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uint32_t next; // Standard next link pointer
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uint32_t altnext; // Standard next link pointer
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uint32_t token; |
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#define QTD_TOKEN_DTOGGLE (1 << 31) |
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#define QTD_TOKEN_TBYTES_MASK 0x7fff0000 |
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#define QTD_TOKEN_TBYTES_SH 16 |
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#define QTD_TOKEN_IOC (1 << 15) |
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#define QTD_TOKEN_CPAGE_MASK 0x00007000 |
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#define QTD_TOKEN_CPAGE_SH 12 |
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#define QTD_TOKEN_CERR_MASK 0x00000c00 |
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#define QTD_TOKEN_CERR_SH 10 |
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#define QTD_TOKEN_PID_MASK 0x00000300 |
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#define QTD_TOKEN_PID_SH 8 |
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#define QTD_TOKEN_ACTIVE (1 << 7) |
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#define QTD_TOKEN_HALT (1 << 6) |
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#define QTD_TOKEN_DBERR (1 << 5) |
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#define QTD_TOKEN_BABBLE (1 << 4) |
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#define QTD_TOKEN_XACTERR (1 << 3) |
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#define QTD_TOKEN_MISSEDUF (1 << 2) |
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#define QTD_TOKEN_SPLITXSTATE (1 << 1) |
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#define QTD_TOKEN_PING (1 << 0) |
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|
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uint32_t bufptr[5]; // Standard buffer pointer |
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#define QTD_BUFPTR_MASK 0xfffff000 |
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#define QTD_BUFPTR_SH 12 |
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} EHCIqtd; |
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/* EHCI spec version 1.0 Section 3.6
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*/
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typedef struct EHCIqh { |
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uint32_t next; // Standard next link pointer
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/* endpoint characteristics */
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uint32_t epchar; |
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#define QH_EPCHAR_RL_MASK 0xf0000000 |
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#define QH_EPCHAR_RL_SH 28 |
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#define QH_EPCHAR_C (1 << 27) |
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#define QH_EPCHAR_MPLEN_MASK 0x07FF0000 |
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#define QH_EPCHAR_MPLEN_SH 16 |
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#define QH_EPCHAR_H (1 << 15) |
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#define QH_EPCHAR_DTC (1 << 14) |
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#define QH_EPCHAR_EPS_MASK 0x00003000 |
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#define QH_EPCHAR_EPS_SH 12 |
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#define EHCI_QH_EPS_FULL 0 |
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#define EHCI_QH_EPS_LOW 1 |
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#define EHCI_QH_EPS_HIGH 2 |
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#define EHCI_QH_EPS_RESERVED 3 |
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|
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#define QH_EPCHAR_EP_MASK 0x00000f00 |
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#define QH_EPCHAR_EP_SH 8 |
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#define QH_EPCHAR_I (1 << 7) |
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#define QH_EPCHAR_DEVADDR_MASK 0x0000007f |
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#define QH_EPCHAR_DEVADDR_SH 0 |
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|
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/* endpoint capabilities */
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uint32_t epcap; |
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#define QH_EPCAP_MULT_MASK 0xc0000000 |
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#define QH_EPCAP_MULT_SH 30 |
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#define QH_EPCAP_PORTNUM_MASK 0x3f800000 |
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#define QH_EPCAP_PORTNUM_SH 23 |
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#define QH_EPCAP_HUBADDR_MASK 0x007f0000 |
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#define QH_EPCAP_HUBADDR_SH 16 |
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#define QH_EPCAP_CMASK_MASK 0x0000ff00 |
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#define QH_EPCAP_CMASK_SH 8 |
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#define QH_EPCAP_SMASK_MASK 0x000000ff |
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#define QH_EPCAP_SMASK_SH 0 |
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|
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uint32_t current_qtd; // Standard next link pointer
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uint32_t next_qtd; // Standard next link pointer
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uint32_t altnext_qtd; |
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#define QH_ALTNEXT_NAKCNT_MASK 0x0000001e |
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#define QH_ALTNEXT_NAKCNT_SH 1 |
326 |
|
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uint32_t token; // Same as QTD token
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uint32_t bufptr[5]; // Standard buffer pointer |
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#define BUFPTR_CPROGMASK_MASK 0x000000ff |
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#define BUFPTR_FRAMETAG_MASK 0x0000001f |
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#define BUFPTR_SBYTES_MASK 0x00000fe0 |
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#define BUFPTR_SBYTES_SH 5 |
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} EHCIqh; |
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|
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/* EHCI spec version 1.0 Section 3.7
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*/
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typedef struct EHCIfstn { |
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uint32_t next; // Standard next link pointer
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uint32_t backptr; // Standard next link pointer
|
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} EHCIfstn; |
341 |
|
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typedef struct EHCIPacket EHCIPacket; |
343 |
typedef struct EHCIQueue EHCIQueue; |
344 |
typedef struct EHCIState EHCIState; |
345 |
|
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enum async_state {
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EHCI_ASYNC_NONE = 0,
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EHCI_ASYNC_INITIALIZED, |
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EHCI_ASYNC_INFLIGHT, |
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EHCI_ASYNC_FINISHED, |
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}; |
352 |
|
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struct EHCIPacket {
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EHCIQueue *queue; |
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QTAILQ_ENTRY(EHCIPacket) next; |
356 |
|
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EHCIqtd qtd; /* copy of current QTD (being worked on) */
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uint32_t qtdaddr; /* address QTD read from */
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|
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USBPacket packet; |
361 |
QEMUSGList sgl; |
362 |
int pid;
|
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enum async_state async;
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int usb_status;
|
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}; |
366 |
|
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struct EHCIQueue {
|
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EHCIState *ehci; |
369 |
QTAILQ_ENTRY(EHCIQueue) next; |
370 |
uint32_t seen; |
371 |
uint64_t ts; |
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int async;
|
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int transact_ctr;
|
374 |
|
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/* cached data from guest - needs to be flushed
|
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* when guest removes an entry (doorbell, handshake sequence)
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*/
|
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EHCIqh qh; /* copy of current QH (being worked on) */
|
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uint32_t qhaddr; /* address QH read from */
|
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uint32_t qtdaddr; /* address QTD read from */
|
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USBDevice *dev; |
382 |
QTAILQ_HEAD(pkts_head, EHCIPacket) packets; |
383 |
}; |
384 |
|
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typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;
|
386 |
|
387 |
struct EHCIState {
|
388 |
USBBus bus; |
389 |
qemu_irq irq; |
390 |
MemoryRegion mem; |
391 |
DMAContext *dma; |
392 |
MemoryRegion mem_caps; |
393 |
MemoryRegion mem_opreg; |
394 |
MemoryRegion mem_ports; |
395 |
int companion_count;
|
396 |
uint16_t capsbase; |
397 |
uint16_t opregbase; |
398 |
|
399 |
/* properties */
|
400 |
uint32_t maxframes; |
401 |
|
402 |
/*
|
403 |
* EHCI spec version 1.0 Section 2.3
|
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* Host Controller Operational Registers
|
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*/
|
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uint8_t caps[CAPA_SIZE]; |
407 |
union {
|
408 |
uint32_t opreg[PORTSC_BEGIN/sizeof(uint32_t)];
|
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struct {
|
410 |
uint32_t usbcmd; |
411 |
uint32_t usbsts; |
412 |
uint32_t usbintr; |
413 |
uint32_t frindex; |
414 |
uint32_t ctrldssegment; |
415 |
uint32_t periodiclistbase; |
416 |
uint32_t asynclistaddr; |
417 |
uint32_t notused[9];
|
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uint32_t configflag; |
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}; |
420 |
}; |
421 |
uint32_t portsc[NB_PORTS]; |
422 |
|
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/*
|
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* Internal states, shadow registers, etc
|
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*/
|
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QEMUTimer *frame_timer; |
427 |
QEMUBH *async_bh; |
428 |
uint32_t astate; /* Current state in asynchronous schedule */
|
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uint32_t pstate; /* Current state in periodic schedule */
|
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USBPort ports[NB_PORTS]; |
431 |
USBPort *companion_ports[NB_PORTS]; |
432 |
uint32_t usbsts_pending; |
433 |
uint32_t usbsts_frindex; |
434 |
EHCIQueueHead aqueues; |
435 |
EHCIQueueHead pqueues; |
436 |
|
437 |
/* which address to look at next */
|
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uint32_t a_fetch_addr; |
439 |
uint32_t p_fetch_addr; |
440 |
|
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USBPacket ipacket; |
442 |
QEMUSGList isgl; |
443 |
|
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uint64_t last_run_ns; |
445 |
uint32_t async_stepdown; |
446 |
bool int_req_by_async;
|
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}; |
448 |
|
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typedef struct EHCIPCIState { |
450 |
PCIDevice pcidev; |
451 |
EHCIState ehci; |
452 |
} EHCIPCIState; |
453 |
|
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#define SET_LAST_RUN_CLOCK(s) \
|
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(s)->last_run_ns = qemu_get_clock_ns(vm_clock); |
456 |
|
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/* nifty macros from Arnon's EHCI version */
|
458 |
#define get_field(data, field) \
|
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(((data) & field##_MASK) >> field##_SH) |
460 |
|
461 |
#define set_field(data, newval, field) do { \ |
462 |
uint32_t val = *data; \ |
463 |
val &= ~ field##_MASK; \ |
464 |
val |= ((newval) << field##_SH) & field##_MASK; \ |
465 |
*data = val; \ |
466 |
} while(0) |
467 |
|
468 |
static const char *ehci_state_names[] = { |
469 |
[EST_INACTIVE] = "INACTIVE",
|
470 |
[EST_ACTIVE] = "ACTIVE",
|
471 |
[EST_EXECUTING] = "EXECUTING",
|
472 |
[EST_SLEEPING] = "SLEEPING",
|
473 |
[EST_WAITLISTHEAD] = "WAITLISTHEAD",
|
474 |
[EST_FETCHENTRY] = "FETCH ENTRY",
|
475 |
[EST_FETCHQH] = "FETCH QH",
|
476 |
[EST_FETCHITD] = "FETCH ITD",
|
477 |
[EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
|
478 |
[EST_FETCHQTD] = "FETCH QTD",
|
479 |
[EST_EXECUTE] = "EXECUTE",
|
480 |
[EST_WRITEBACK] = "WRITEBACK",
|
481 |
[EST_HORIZONTALQH] = "HORIZONTALQH",
|
482 |
}; |
483 |
|
484 |
static const char *ehci_mmio_names[] = { |
485 |
[USBCMD] = "USBCMD",
|
486 |
[USBSTS] = "USBSTS",
|
487 |
[USBINTR] = "USBINTR",
|
488 |
[FRINDEX] = "FRINDEX",
|
489 |
[PERIODICLISTBASE] = "P-LIST BASE",
|
490 |
[ASYNCLISTADDR] = "A-LIST ADDR",
|
491 |
[CONFIGFLAG] = "CONFIGFLAG",
|
492 |
}; |
493 |
|
494 |
static int ehci_state_executing(EHCIQueue *q); |
495 |
static int ehci_state_writeback(EHCIQueue *q); |
496 |
static int ehci_fill_queue(EHCIPacket *p); |
497 |
|
498 |
static const char *nr2str(const char **n, size_t len, uint32_t nr) |
499 |
{ |
500 |
if (nr < len && n[nr] != NULL) { |
501 |
return n[nr];
|
502 |
} else {
|
503 |
return "unknown"; |
504 |
} |
505 |
} |
506 |
|
507 |
static const char *state2str(uint32_t state) |
508 |
{ |
509 |
return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
|
510 |
} |
511 |
|
512 |
static const char *addr2str(hwaddr addr) |
513 |
{ |
514 |
return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
|
515 |
} |
516 |
|
517 |
static void ehci_trace_usbsts(uint32_t mask, int state) |
518 |
{ |
519 |
/* interrupts */
|
520 |
if (mask & USBSTS_INT) {
|
521 |
trace_usb_ehci_usbsts("INT", state);
|
522 |
} |
523 |
if (mask & USBSTS_ERRINT) {
|
524 |
trace_usb_ehci_usbsts("ERRINT", state);
|
525 |
} |
526 |
if (mask & USBSTS_PCD) {
|
527 |
trace_usb_ehci_usbsts("PCD", state);
|
528 |
} |
529 |
if (mask & USBSTS_FLR) {
|
530 |
trace_usb_ehci_usbsts("FLR", state);
|
531 |
} |
532 |
if (mask & USBSTS_HSE) {
|
533 |
trace_usb_ehci_usbsts("HSE", state);
|
534 |
} |
535 |
if (mask & USBSTS_IAA) {
|
536 |
trace_usb_ehci_usbsts("IAA", state);
|
537 |
} |
538 |
|
539 |
/* status */
|
540 |
if (mask & USBSTS_HALT) {
|
541 |
trace_usb_ehci_usbsts("HALT", state);
|
542 |
} |
543 |
if (mask & USBSTS_REC) {
|
544 |
trace_usb_ehci_usbsts("REC", state);
|
545 |
} |
546 |
if (mask & USBSTS_PSS) {
|
547 |
trace_usb_ehci_usbsts("PSS", state);
|
548 |
} |
549 |
if (mask & USBSTS_ASS) {
|
550 |
trace_usb_ehci_usbsts("ASS", state);
|
551 |
} |
552 |
} |
553 |
|
554 |
static inline void ehci_set_usbsts(EHCIState *s, int mask) |
555 |
{ |
556 |
if ((s->usbsts & mask) == mask) {
|
557 |
return;
|
558 |
} |
559 |
ehci_trace_usbsts(mask, 1);
|
560 |
s->usbsts |= mask; |
561 |
} |
562 |
|
563 |
static inline void ehci_clear_usbsts(EHCIState *s, int mask) |
564 |
{ |
565 |
if ((s->usbsts & mask) == 0) { |
566 |
return;
|
567 |
} |
568 |
ehci_trace_usbsts(mask, 0);
|
569 |
s->usbsts &= ~mask; |
570 |
} |
571 |
|
572 |
/* update irq line */
|
573 |
static inline void ehci_update_irq(EHCIState *s) |
574 |
{ |
575 |
int level = 0; |
576 |
|
577 |
if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
|
578 |
level = 1;
|
579 |
} |
580 |
|
581 |
trace_usb_ehci_irq(level, s->frindex, s->usbsts, s->usbintr); |
582 |
qemu_set_irq(s->irq, level); |
583 |
} |
584 |
|
585 |
/* flag interrupt condition */
|
586 |
static inline void ehci_raise_irq(EHCIState *s, int intr) |
587 |
{ |
588 |
if (intr & (USBSTS_PCD | USBSTS_FLR | USBSTS_HSE)) {
|
589 |
s->usbsts |= intr; |
590 |
ehci_update_irq(s); |
591 |
} else {
|
592 |
s->usbsts_pending |= intr; |
593 |
} |
594 |
} |
595 |
|
596 |
/*
|
597 |
* Commit pending interrupts (added via ehci_raise_irq),
|
598 |
* at the rate allowed by "Interrupt Threshold Control".
|
599 |
*/
|
600 |
static inline void ehci_commit_irq(EHCIState *s) |
601 |
{ |
602 |
uint32_t itc; |
603 |
|
604 |
if (!s->usbsts_pending) {
|
605 |
return;
|
606 |
} |
607 |
if (s->usbsts_frindex > s->frindex) {
|
608 |
return;
|
609 |
} |
610 |
|
611 |
itc = (s->usbcmd >> 16) & 0xff; |
612 |
s->usbsts |= s->usbsts_pending; |
613 |
s->usbsts_pending = 0;
|
614 |
s->usbsts_frindex = s->frindex + itc; |
615 |
ehci_update_irq(s); |
616 |
} |
617 |
|
618 |
static void ehci_update_halt(EHCIState *s) |
619 |
{ |
620 |
if (s->usbcmd & USBCMD_RUNSTOP) {
|
621 |
ehci_clear_usbsts(s, USBSTS_HALT); |
622 |
} else {
|
623 |
if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) {
|
624 |
ehci_set_usbsts(s, USBSTS_HALT); |
625 |
} |
626 |
} |
627 |
} |
628 |
|
629 |
static void ehci_set_state(EHCIState *s, int async, int state) |
630 |
{ |
631 |
if (async) {
|
632 |
trace_usb_ehci_state("async", state2str(state));
|
633 |
s->astate = state; |
634 |
if (s->astate == EST_INACTIVE) {
|
635 |
ehci_clear_usbsts(s, USBSTS_ASS); |
636 |
ehci_update_halt(s); |
637 |
} else {
|
638 |
ehci_set_usbsts(s, USBSTS_ASS); |
639 |
} |
640 |
} else {
|
641 |
trace_usb_ehci_state("periodic", state2str(state));
|
642 |
s->pstate = state; |
643 |
if (s->pstate == EST_INACTIVE) {
|
644 |
ehci_clear_usbsts(s, USBSTS_PSS); |
645 |
ehci_update_halt(s); |
646 |
} else {
|
647 |
ehci_set_usbsts(s, USBSTS_PSS); |
648 |
} |
649 |
} |
650 |
} |
651 |
|
652 |
static int ehci_get_state(EHCIState *s, int async) |
653 |
{ |
654 |
return async ? s->astate : s->pstate;
|
655 |
} |
656 |
|
657 |
static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) |
658 |
{ |
659 |
if (async) {
|
660 |
s->a_fetch_addr = addr; |
661 |
} else {
|
662 |
s->p_fetch_addr = addr; |
663 |
} |
664 |
} |
665 |
|
666 |
static int ehci_get_fetch_addr(EHCIState *s, int async) |
667 |
{ |
668 |
return async ? s->a_fetch_addr : s->p_fetch_addr;
|
669 |
} |
670 |
|
671 |
static void ehci_trace_qh(EHCIQueue *q, hwaddr addr, EHCIqh *qh) |
672 |
{ |
673 |
/* need three here due to argument count limits */
|
674 |
trace_usb_ehci_qh_ptrs(q, addr, qh->next, |
675 |
qh->current_qtd, qh->next_qtd, qh->altnext_qtd); |
676 |
trace_usb_ehci_qh_fields(addr, |
677 |
get_field(qh->epchar, QH_EPCHAR_RL), |
678 |
get_field(qh->epchar, QH_EPCHAR_MPLEN), |
679 |
get_field(qh->epchar, QH_EPCHAR_EPS), |
680 |
get_field(qh->epchar, QH_EPCHAR_EP), |
681 |
get_field(qh->epchar, QH_EPCHAR_DEVADDR)); |
682 |
trace_usb_ehci_qh_bits(addr, |
683 |
(bool)(qh->epchar & QH_EPCHAR_C),
|
684 |
(bool)(qh->epchar & QH_EPCHAR_H),
|
685 |
(bool)(qh->epchar & QH_EPCHAR_DTC),
|
686 |
(bool)(qh->epchar & QH_EPCHAR_I));
|
687 |
} |
688 |
|
689 |
static void ehci_trace_qtd(EHCIQueue *q, hwaddr addr, EHCIqtd *qtd) |
690 |
{ |
691 |
/* need three here due to argument count limits */
|
692 |
trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); |
693 |
trace_usb_ehci_qtd_fields(addr, |
694 |
get_field(qtd->token, QTD_TOKEN_TBYTES), |
695 |
get_field(qtd->token, QTD_TOKEN_CPAGE), |
696 |
get_field(qtd->token, QTD_TOKEN_CERR), |
697 |
get_field(qtd->token, QTD_TOKEN_PID)); |
698 |
trace_usb_ehci_qtd_bits(addr, |
699 |
(bool)(qtd->token & QTD_TOKEN_IOC),
|
700 |
(bool)(qtd->token & QTD_TOKEN_ACTIVE),
|
701 |
(bool)(qtd->token & QTD_TOKEN_HALT),
|
702 |
(bool)(qtd->token & QTD_TOKEN_BABBLE),
|
703 |
(bool)(qtd->token & QTD_TOKEN_XACTERR));
|
704 |
} |
705 |
|
706 |
static void ehci_trace_itd(EHCIState *s, hwaddr addr, EHCIitd *itd) |
707 |
{ |
708 |
trace_usb_ehci_itd(addr, itd->next, |
709 |
get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
|
710 |
get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
|
711 |
get_field(itd->bufptr[0], ITD_BUFPTR_EP),
|
712 |
get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
|
713 |
} |
714 |
|
715 |
static void ehci_trace_sitd(EHCIState *s, hwaddr addr, |
716 |
EHCIsitd *sitd) |
717 |
{ |
718 |
trace_usb_ehci_sitd(addr, sitd->next, |
719 |
(bool)(sitd->results & SITD_RESULTS_ACTIVE));
|
720 |
} |
721 |
|
722 |
static void ehci_trace_guest_bug(EHCIState *s, const char *message) |
723 |
{ |
724 |
trace_usb_ehci_guest_bug(message); |
725 |
fprintf(stderr, "ehci warning: %s\n", message);
|
726 |
} |
727 |
|
728 |
static inline bool ehci_enabled(EHCIState *s) |
729 |
{ |
730 |
return s->usbcmd & USBCMD_RUNSTOP;
|
731 |
} |
732 |
|
733 |
static inline bool ehci_async_enabled(EHCIState *s) |
734 |
{ |
735 |
return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE);
|
736 |
} |
737 |
|
738 |
static inline bool ehci_periodic_enabled(EHCIState *s) |
739 |
{ |
740 |
return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE);
|
741 |
} |
742 |
|
743 |
/* packet management */
|
744 |
|
745 |
static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
|
746 |
{ |
747 |
EHCIPacket *p; |
748 |
|
749 |
p = g_new0(EHCIPacket, 1);
|
750 |
p->queue = q; |
751 |
usb_packet_init(&p->packet); |
752 |
QTAILQ_INSERT_TAIL(&q->packets, p, next); |
753 |
trace_usb_ehci_packet_action(p->queue, p, "alloc");
|
754 |
return p;
|
755 |
} |
756 |
|
757 |
static void ehci_free_packet(EHCIPacket *p) |
758 |
{ |
759 |
if (p->async == EHCI_ASYNC_FINISHED) {
|
760 |
int state = ehci_get_state(p->queue->ehci, p->queue->async);
|
761 |
/* This is a normal, but rare condition (cancel racing completion) */
|
762 |
fprintf(stderr, "EHCI: Warning packet completed but not processed\n");
|
763 |
ehci_state_executing(p->queue); |
764 |
ehci_state_writeback(p->queue); |
765 |
ehci_set_state(p->queue->ehci, p->queue->async, state); |
766 |
/* state_writeback recurses into us with async == EHCI_ASYNC_NONE!! */
|
767 |
return;
|
768 |
} |
769 |
trace_usb_ehci_packet_action(p->queue, p, "free");
|
770 |
if (p->async == EHCI_ASYNC_INITIALIZED) {
|
771 |
usb_packet_unmap(&p->packet, &p->sgl); |
772 |
qemu_sglist_destroy(&p->sgl); |
773 |
} |
774 |
if (p->async == EHCI_ASYNC_INFLIGHT) {
|
775 |
usb_cancel_packet(&p->packet); |
776 |
usb_packet_unmap(&p->packet, &p->sgl); |
777 |
qemu_sglist_destroy(&p->sgl); |
778 |
} |
779 |
QTAILQ_REMOVE(&p->queue->packets, p, next); |
780 |
usb_packet_cleanup(&p->packet); |
781 |
g_free(p); |
782 |
} |
783 |
|
784 |
/* queue management */
|
785 |
|
786 |
static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async) |
787 |
{ |
788 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
789 |
EHCIQueue *q; |
790 |
|
791 |
q = g_malloc0(sizeof(*q));
|
792 |
q->ehci = ehci; |
793 |
q->qhaddr = addr; |
794 |
q->async = async; |
795 |
QTAILQ_INIT(&q->packets); |
796 |
QTAILQ_INSERT_HEAD(head, q, next); |
797 |
trace_usb_ehci_queue_action(q, "alloc");
|
798 |
return q;
|
799 |
} |
800 |
|
801 |
static int ehci_cancel_queue(EHCIQueue *q) |
802 |
{ |
803 |
EHCIPacket *p; |
804 |
int packets = 0; |
805 |
|
806 |
p = QTAILQ_FIRST(&q->packets); |
807 |
if (p == NULL) { |
808 |
return 0; |
809 |
} |
810 |
|
811 |
trace_usb_ehci_queue_action(q, "cancel");
|
812 |
do {
|
813 |
ehci_free_packet(p); |
814 |
packets++; |
815 |
} while ((p = QTAILQ_FIRST(&q->packets)) != NULL); |
816 |
return packets;
|
817 |
} |
818 |
|
819 |
static int ehci_reset_queue(EHCIQueue *q) |
820 |
{ |
821 |
int packets;
|
822 |
|
823 |
trace_usb_ehci_queue_action(q, "reset");
|
824 |
packets = ehci_cancel_queue(q); |
825 |
q->dev = NULL;
|
826 |
q->qtdaddr = 0;
|
827 |
return packets;
|
828 |
} |
829 |
|
830 |
static void ehci_free_queue(EHCIQueue *q, const char *warn) |
831 |
{ |
832 |
EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues; |
833 |
int cancelled;
|
834 |
|
835 |
trace_usb_ehci_queue_action(q, "free");
|
836 |
cancelled = ehci_cancel_queue(q); |
837 |
if (warn && cancelled > 0) { |
838 |
ehci_trace_guest_bug(q->ehci, warn); |
839 |
} |
840 |
QTAILQ_REMOVE(head, q, next); |
841 |
g_free(q); |
842 |
} |
843 |
|
844 |
static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
|
845 |
int async)
|
846 |
{ |
847 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
848 |
EHCIQueue *q; |
849 |
|
850 |
QTAILQ_FOREACH(q, head, next) { |
851 |
if (addr == q->qhaddr) {
|
852 |
return q;
|
853 |
} |
854 |
} |
855 |
return NULL; |
856 |
} |
857 |
|
858 |
static void ehci_queues_rip_unused(EHCIState *ehci, int async) |
859 |
{ |
860 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
861 |
const char *warn = async ? "guest unlinked busy QH" : NULL; |
862 |
uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4;
|
863 |
EHCIQueue *q, *tmp; |
864 |
|
865 |
QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
866 |
if (q->seen) {
|
867 |
q->seen = 0;
|
868 |
q->ts = ehci->last_run_ns; |
869 |
continue;
|
870 |
} |
871 |
if (ehci->last_run_ns < q->ts + maxage) {
|
872 |
continue;
|
873 |
} |
874 |
ehci_free_queue(q, warn); |
875 |
} |
876 |
} |
877 |
|
878 |
static void ehci_queues_rip_unseen(EHCIState *ehci, int async) |
879 |
{ |
880 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
881 |
EHCIQueue *q, *tmp; |
882 |
|
883 |
QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
884 |
if (!q->seen) {
|
885 |
ehci_free_queue(q, NULL);
|
886 |
} |
887 |
} |
888 |
} |
889 |
|
890 |
static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async) |
891 |
{ |
892 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
893 |
EHCIQueue *q, *tmp; |
894 |
|
895 |
QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
896 |
if (q->dev != dev) {
|
897 |
continue;
|
898 |
} |
899 |
ehci_free_queue(q, NULL);
|
900 |
} |
901 |
} |
902 |
|
903 |
static void ehci_queues_rip_all(EHCIState *ehci, int async) |
904 |
{ |
905 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
906 |
const char *warn = async ? "guest stopped busy async schedule" : NULL; |
907 |
EHCIQueue *q, *tmp; |
908 |
|
909 |
QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
910 |
ehci_free_queue(q, warn); |
911 |
} |
912 |
} |
913 |
|
914 |
/* Attach or detach a device on root hub */
|
915 |
|
916 |
static void ehci_attach(USBPort *port) |
917 |
{ |
918 |
EHCIState *s = port->opaque; |
919 |
uint32_t *portsc = &s->portsc[port->index]; |
920 |
const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; |
921 |
|
922 |
trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc); |
923 |
|
924 |
if (*portsc & PORTSC_POWNER) {
|
925 |
USBPort *companion = s->companion_ports[port->index]; |
926 |
companion->dev = port->dev; |
927 |
companion->ops->attach(companion); |
928 |
return;
|
929 |
} |
930 |
|
931 |
*portsc |= PORTSC_CONNECT; |
932 |
*portsc |= PORTSC_CSC; |
933 |
|
934 |
ehci_raise_irq(s, USBSTS_PCD); |
935 |
ehci_commit_irq(s); |
936 |
} |
937 |
|
938 |
static void ehci_detach(USBPort *port) |
939 |
{ |
940 |
EHCIState *s = port->opaque; |
941 |
uint32_t *portsc = &s->portsc[port->index]; |
942 |
const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; |
943 |
|
944 |
trace_usb_ehci_port_detach(port->index, owner); |
945 |
|
946 |
if (*portsc & PORTSC_POWNER) {
|
947 |
USBPort *companion = s->companion_ports[port->index]; |
948 |
companion->ops->detach(companion); |
949 |
companion->dev = NULL;
|
950 |
/*
|
951 |
* EHCI spec 4.2.2: "When a disconnect occurs... On the event,
|
952 |
* the port ownership is returned immediately to the EHCI controller."
|
953 |
*/
|
954 |
*portsc &= ~PORTSC_POWNER; |
955 |
return;
|
956 |
} |
957 |
|
958 |
ehci_queues_rip_device(s, port->dev, 0);
|
959 |
ehci_queues_rip_device(s, port->dev, 1);
|
960 |
|
961 |
*portsc &= ~(PORTSC_CONNECT|PORTSC_PED); |
962 |
*portsc |= PORTSC_CSC; |
963 |
|
964 |
ehci_raise_irq(s, USBSTS_PCD); |
965 |
ehci_commit_irq(s); |
966 |
} |
967 |
|
968 |
static void ehci_child_detach(USBPort *port, USBDevice *child) |
969 |
{ |
970 |
EHCIState *s = port->opaque; |
971 |
uint32_t portsc = s->portsc[port->index]; |
972 |
|
973 |
if (portsc & PORTSC_POWNER) {
|
974 |
USBPort *companion = s->companion_ports[port->index]; |
975 |
companion->ops->child_detach(companion, child); |
976 |
return;
|
977 |
} |
978 |
|
979 |
ehci_queues_rip_device(s, child, 0);
|
980 |
ehci_queues_rip_device(s, child, 1);
|
981 |
} |
982 |
|
983 |
static void ehci_wakeup(USBPort *port) |
984 |
{ |
985 |
EHCIState *s = port->opaque; |
986 |
uint32_t portsc = s->portsc[port->index]; |
987 |
|
988 |
if (portsc & PORTSC_POWNER) {
|
989 |
USBPort *companion = s->companion_ports[port->index]; |
990 |
if (companion->ops->wakeup) {
|
991 |
companion->ops->wakeup(companion); |
992 |
} |
993 |
return;
|
994 |
} |
995 |
|
996 |
qemu_bh_schedule(s->async_bh); |
997 |
} |
998 |
|
999 |
static int ehci_register_companion(USBBus *bus, USBPort *ports[], |
1000 |
uint32_t portcount, uint32_t firstport) |
1001 |
{ |
1002 |
EHCIState *s = container_of(bus, EHCIState, bus); |
1003 |
uint32_t i; |
1004 |
|
1005 |
if (firstport + portcount > NB_PORTS) {
|
1006 |
qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
|
1007 |
"firstport on masterbus");
|
1008 |
error_printf_unless_qmp( |
1009 |
"firstport value of %u makes companion take ports %u - %u, which "
|
1010 |
"is outside of the valid range of 0 - %u\n", firstport, firstport,
|
1011 |
firstport + portcount - 1, NB_PORTS - 1); |
1012 |
return -1; |
1013 |
} |
1014 |
|
1015 |
for (i = 0; i < portcount; i++) { |
1016 |
if (s->companion_ports[firstport + i]) {
|
1017 |
qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
|
1018 |
"an USB masterbus");
|
1019 |
error_printf_unless_qmp( |
1020 |
"port %u on masterbus %s already has a companion assigned\n",
|
1021 |
firstport + i, bus->qbus.name); |
1022 |
return -1; |
1023 |
} |
1024 |
} |
1025 |
|
1026 |
for (i = 0; i < portcount; i++) { |
1027 |
s->companion_ports[firstport + i] = ports[i]; |
1028 |
s->ports[firstport + i].speedmask |= |
1029 |
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL; |
1030 |
/* Ensure devs attached before the initial reset go to the companion */
|
1031 |
s->portsc[firstport + i] = PORTSC_POWNER; |
1032 |
} |
1033 |
|
1034 |
s->companion_count++; |
1035 |
s->caps[0x05] = (s->companion_count << 4) | portcount; |
1036 |
|
1037 |
return 0; |
1038 |
} |
1039 |
|
1040 |
static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
|
1041 |
{ |
1042 |
USBDevice *dev; |
1043 |
USBPort *port; |
1044 |
int i;
|
1045 |
|
1046 |
for (i = 0; i < NB_PORTS; i++) { |
1047 |
port = &ehci->ports[i]; |
1048 |
if (!(ehci->portsc[i] & PORTSC_PED)) {
|
1049 |
DPRINTF("Port %d not enabled\n", i);
|
1050 |
continue;
|
1051 |
} |
1052 |
dev = usb_find_device(port, addr); |
1053 |
if (dev != NULL) { |
1054 |
return dev;
|
1055 |
} |
1056 |
} |
1057 |
return NULL; |
1058 |
} |
1059 |
|
1060 |
/* 4.1 host controller initialization */
|
1061 |
static void ehci_reset(void *opaque) |
1062 |
{ |
1063 |
EHCIState *s = opaque; |
1064 |
int i;
|
1065 |
USBDevice *devs[NB_PORTS]; |
1066 |
|
1067 |
trace_usb_ehci_reset(); |
1068 |
|
1069 |
/*
|
1070 |
* Do the detach before touching portsc, so that it correctly gets send to
|
1071 |
* us or to our companion based on PORTSC_POWNER before the reset.
|
1072 |
*/
|
1073 |
for(i = 0; i < NB_PORTS; i++) { |
1074 |
devs[i] = s->ports[i].dev; |
1075 |
if (devs[i] && devs[i]->attached) {
|
1076 |
usb_detach(&s->ports[i]); |
1077 |
} |
1078 |
} |
1079 |
|
1080 |
memset(&s->opreg, 0x00, sizeof(s->opreg)); |
1081 |
memset(&s->portsc, 0x00, sizeof(s->portsc)); |
1082 |
|
1083 |
s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; |
1084 |
s->usbsts = USBSTS_HALT; |
1085 |
s->usbsts_pending = 0;
|
1086 |
s->usbsts_frindex = 0;
|
1087 |
|
1088 |
s->astate = EST_INACTIVE; |
1089 |
s->pstate = EST_INACTIVE; |
1090 |
|
1091 |
for(i = 0; i < NB_PORTS; i++) { |
1092 |
if (s->companion_ports[i]) {
|
1093 |
s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; |
1094 |
} else {
|
1095 |
s->portsc[i] = PORTSC_PPOWER; |
1096 |
} |
1097 |
if (devs[i] && devs[i]->attached) {
|
1098 |
usb_attach(&s->ports[i]); |
1099 |
usb_device_reset(devs[i]); |
1100 |
} |
1101 |
} |
1102 |
ehci_queues_rip_all(s, 0);
|
1103 |
ehci_queues_rip_all(s, 1);
|
1104 |
qemu_del_timer(s->frame_timer); |
1105 |
qemu_bh_cancel(s->async_bh); |
1106 |
} |
1107 |
|
1108 |
static uint64_t ehci_caps_read(void *ptr, hwaddr addr, |
1109 |
unsigned size)
|
1110 |
{ |
1111 |
EHCIState *s = ptr; |
1112 |
return s->caps[addr];
|
1113 |
} |
1114 |
|
1115 |
static uint64_t ehci_opreg_read(void *ptr, hwaddr addr, |
1116 |
unsigned size)
|
1117 |
{ |
1118 |
EHCIState *s = ptr; |
1119 |
uint32_t val; |
1120 |
|
1121 |
val = s->opreg[addr >> 2];
|
1122 |
trace_usb_ehci_opreg_read(addr + s->opregbase, addr2str(addr), val); |
1123 |
return val;
|
1124 |
} |
1125 |
|
1126 |
static uint64_t ehci_port_read(void *ptr, hwaddr addr, |
1127 |
unsigned size)
|
1128 |
{ |
1129 |
EHCIState *s = ptr; |
1130 |
uint32_t val; |
1131 |
|
1132 |
val = s->portsc[addr >> 2];
|
1133 |
trace_usb_ehci_portsc_read(addr + PORTSC_BEGIN, addr >> 2, val);
|
1134 |
return val;
|
1135 |
} |
1136 |
|
1137 |
static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner) |
1138 |
{ |
1139 |
USBDevice *dev = s->ports[port].dev; |
1140 |
uint32_t *portsc = &s->portsc[port]; |
1141 |
uint32_t orig; |
1142 |
|
1143 |
if (s->companion_ports[port] == NULL) |
1144 |
return;
|
1145 |
|
1146 |
owner = owner & PORTSC_POWNER; |
1147 |
orig = *portsc & PORTSC_POWNER; |
1148 |
|
1149 |
if (!(owner ^ orig)) {
|
1150 |
return;
|
1151 |
} |
1152 |
|
1153 |
if (dev && dev->attached) {
|
1154 |
usb_detach(&s->ports[port]); |
1155 |
} |
1156 |
|
1157 |
*portsc &= ~PORTSC_POWNER; |
1158 |
*portsc |= owner; |
1159 |
|
1160 |
if (dev && dev->attached) {
|
1161 |
usb_attach(&s->ports[port]); |
1162 |
} |
1163 |
} |
1164 |
|
1165 |
static void ehci_port_write(void *ptr, hwaddr addr, |
1166 |
uint64_t val, unsigned size)
|
1167 |
{ |
1168 |
EHCIState *s = ptr; |
1169 |
int port = addr >> 2; |
1170 |
uint32_t *portsc = &s->portsc[port]; |
1171 |
uint32_t old = *portsc; |
1172 |
USBDevice *dev = s->ports[port].dev; |
1173 |
|
1174 |
trace_usb_ehci_portsc_write(addr + PORTSC_BEGIN, addr >> 2, val);
|
1175 |
|
1176 |
/* Clear rwc bits */
|
1177 |
*portsc &= ~(val & PORTSC_RWC_MASK); |
1178 |
/* The guest may clear, but not set the PED bit */
|
1179 |
*portsc &= val | ~PORTSC_PED; |
1180 |
/* POWNER is masked out by RO_MASK as it is RO when we've no companion */
|
1181 |
handle_port_owner_write(s, port, val); |
1182 |
/* And finally apply RO_MASK */
|
1183 |
val &= PORTSC_RO_MASK; |
1184 |
|
1185 |
if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
|
1186 |
trace_usb_ehci_port_reset(port, 1);
|
1187 |
} |
1188 |
|
1189 |
if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
|
1190 |
trace_usb_ehci_port_reset(port, 0);
|
1191 |
if (dev && dev->attached) {
|
1192 |
usb_port_reset(&s->ports[port]); |
1193 |
*portsc &= ~PORTSC_CSC; |
1194 |
} |
1195 |
|
1196 |
/*
|
1197 |
* Table 2.16 Set the enable bit(and enable bit change) to indicate
|
1198 |
* to SW that this port has a high speed device attached
|
1199 |
*/
|
1200 |
if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
|
1201 |
val |= PORTSC_PED; |
1202 |
} |
1203 |
} |
1204 |
|
1205 |
*portsc &= ~PORTSC_RO_MASK; |
1206 |
*portsc |= val; |
1207 |
trace_usb_ehci_portsc_change(addr + PORTSC_BEGIN, addr >> 2, *portsc, old);
|
1208 |
} |
1209 |
|
1210 |
static void ehci_opreg_write(void *ptr, hwaddr addr, |
1211 |
uint64_t val, unsigned size)
|
1212 |
{ |
1213 |
EHCIState *s = ptr; |
1214 |
uint32_t *mmio = s->opreg + (addr >> 2);
|
1215 |
uint32_t old = *mmio; |
1216 |
int i;
|
1217 |
|
1218 |
trace_usb_ehci_opreg_write(addr + s->opregbase, addr2str(addr), val); |
1219 |
|
1220 |
switch (addr) {
|
1221 |
case USBCMD:
|
1222 |
if (val & USBCMD_HCRESET) {
|
1223 |
ehci_reset(s); |
1224 |
val = s->usbcmd; |
1225 |
break;
|
1226 |
} |
1227 |
|
1228 |
/* not supporting dynamic frame list size at the moment */
|
1229 |
if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
|
1230 |
fprintf(stderr, "attempt to set frame list size -- value %d\n",
|
1231 |
(int)val & USBCMD_FLS);
|
1232 |
val &= ~USBCMD_FLS; |
1233 |
} |
1234 |
|
1235 |
if (val & USBCMD_IAAD) {
|
1236 |
/*
|
1237 |
* Process IAAD immediately, otherwise the Linux IAAD watchdog may
|
1238 |
* trigger and re-use a qh without us seeing the unlink.
|
1239 |
*/
|
1240 |
s->async_stepdown = 0;
|
1241 |
qemu_bh_schedule(s->async_bh); |
1242 |
trace_usb_ehci_doorbell_ring(); |
1243 |
} |
1244 |
|
1245 |
if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=
|
1246 |
((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) { |
1247 |
if (s->pstate == EST_INACTIVE) {
|
1248 |
SET_LAST_RUN_CLOCK(s); |
1249 |
} |
1250 |
s->usbcmd = val; /* Set usbcmd for ehci_update_halt() */
|
1251 |
ehci_update_halt(s); |
1252 |
s->async_stepdown = 0;
|
1253 |
qemu_bh_schedule(s->async_bh); |
1254 |
} |
1255 |
break;
|
1256 |
|
1257 |
case USBSTS:
|
1258 |
val &= USBSTS_RO_MASK; // bits 6 through 31 are RO
|
1259 |
ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC
|
1260 |
val = s->usbsts; |
1261 |
ehci_update_irq(s); |
1262 |
break;
|
1263 |
|
1264 |
case USBINTR:
|
1265 |
val &= USBINTR_MASK; |
1266 |
break;
|
1267 |
|
1268 |
case FRINDEX:
|
1269 |
val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */ |
1270 |
break;
|
1271 |
|
1272 |
case CONFIGFLAG:
|
1273 |
val &= 0x1;
|
1274 |
if (val) {
|
1275 |
for(i = 0; i < NB_PORTS; i++) |
1276 |
handle_port_owner_write(s, i, 0);
|
1277 |
} |
1278 |
break;
|
1279 |
|
1280 |
case PERIODICLISTBASE:
|
1281 |
if (ehci_periodic_enabled(s)) {
|
1282 |
fprintf(stderr, |
1283 |
"ehci: PERIODIC list base register set while periodic schedule\n"
|
1284 |
" is enabled and HC is enabled\n");
|
1285 |
} |
1286 |
break;
|
1287 |
|
1288 |
case ASYNCLISTADDR:
|
1289 |
if (ehci_async_enabled(s)) {
|
1290 |
fprintf(stderr, |
1291 |
"ehci: ASYNC list address register set while async schedule\n"
|
1292 |
" is enabled and HC is enabled\n");
|
1293 |
} |
1294 |
break;
|
1295 |
} |
1296 |
|
1297 |
*mmio = val; |
1298 |
trace_usb_ehci_opreg_change(addr + s->opregbase, addr2str(addr), |
1299 |
*mmio, old); |
1300 |
} |
1301 |
|
1302 |
|
1303 |
// TODO : Put in common header file, duplication from usb-ohci.c
|
1304 |
|
1305 |
/* Get an array of dwords from main memory */
|
1306 |
static inline int get_dwords(EHCIState *ehci, uint32_t addr, |
1307 |
uint32_t *buf, int num)
|
1308 |
{ |
1309 |
int i;
|
1310 |
|
1311 |
for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
1312 |
dma_memory_read(ehci->dma, addr, buf, sizeof(*buf));
|
1313 |
*buf = le32_to_cpu(*buf); |
1314 |
} |
1315 |
|
1316 |
return 1; |
1317 |
} |
1318 |
|
1319 |
/* Put an array of dwords in to main memory */
|
1320 |
static inline int put_dwords(EHCIState *ehci, uint32_t addr, |
1321 |
uint32_t *buf, int num)
|
1322 |
{ |
1323 |
int i;
|
1324 |
|
1325 |
for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
1326 |
uint32_t tmp = cpu_to_le32(*buf); |
1327 |
dma_memory_write(ehci->dma, addr, &tmp, sizeof(tmp));
|
1328 |
} |
1329 |
|
1330 |
return 1; |
1331 |
} |
1332 |
|
1333 |
/*
|
1334 |
* Write the qh back to guest physical memory. This step isn't
|
1335 |
* in the EHCI spec but we need to do it since we don't share
|
1336 |
* physical memory with our guest VM.
|
1337 |
*
|
1338 |
* The first three dwords are read-only for the EHCI, so skip them
|
1339 |
* when writing back the qh.
|
1340 |
*/
|
1341 |
static void ehci_flush_qh(EHCIQueue *q) |
1342 |
{ |
1343 |
uint32_t *qh = (uint32_t *) &q->qh; |
1344 |
uint32_t dwords = sizeof(EHCIqh) >> 2; |
1345 |
uint32_t addr = NLPTR_GET(q->qhaddr); |
1346 |
|
1347 |
put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); |
1348 |
} |
1349 |
|
1350 |
// 4.10.2
|
1351 |
|
1352 |
static int ehci_qh_do_overlay(EHCIQueue *q) |
1353 |
{ |
1354 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
1355 |
int i;
|
1356 |
int dtoggle;
|
1357 |
int ping;
|
1358 |
int eps;
|
1359 |
int reload;
|
1360 |
|
1361 |
assert(p != NULL);
|
1362 |
assert(p->qtdaddr == q->qtdaddr); |
1363 |
|
1364 |
// remember values in fields to preserve in qh after overlay
|
1365 |
|
1366 |
dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; |
1367 |
ping = q->qh.token & QTD_TOKEN_PING; |
1368 |
|
1369 |
q->qh.current_qtd = p->qtdaddr; |
1370 |
q->qh.next_qtd = p->qtd.next; |
1371 |
q->qh.altnext_qtd = p->qtd.altnext; |
1372 |
q->qh.token = p->qtd.token; |
1373 |
|
1374 |
|
1375 |
eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); |
1376 |
if (eps == EHCI_QH_EPS_HIGH) {
|
1377 |
q->qh.token &= ~QTD_TOKEN_PING; |
1378 |
q->qh.token |= ping; |
1379 |
} |
1380 |
|
1381 |
reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1382 |
set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); |
1383 |
|
1384 |
for (i = 0; i < 5; i++) { |
1385 |
q->qh.bufptr[i] = p->qtd.bufptr[i]; |
1386 |
} |
1387 |
|
1388 |
if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
|
1389 |
// preserve QH DT bit
|
1390 |
q->qh.token &= ~QTD_TOKEN_DTOGGLE; |
1391 |
q->qh.token |= dtoggle; |
1392 |
} |
1393 |
|
1394 |
q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
|
1395 |
q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
|
1396 |
|
1397 |
ehci_flush_qh(q); |
1398 |
|
1399 |
return 0; |
1400 |
} |
1401 |
|
1402 |
static int ehci_init_transfer(EHCIPacket *p) |
1403 |
{ |
1404 |
uint32_t cpage, offset, bytes, plen; |
1405 |
dma_addr_t page; |
1406 |
|
1407 |
cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE); |
1408 |
bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES); |
1409 |
offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
|
1410 |
qemu_sglist_init(&p->sgl, 5, p->queue->ehci->dma);
|
1411 |
|
1412 |
while (bytes > 0) { |
1413 |
if (cpage > 4) { |
1414 |
fprintf(stderr, "cpage out of range (%d)\n", cpage);
|
1415 |
return USB_RET_PROCERR;
|
1416 |
} |
1417 |
|
1418 |
page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK; |
1419 |
page += offset; |
1420 |
plen = bytes; |
1421 |
if (plen > 4096 - offset) { |
1422 |
plen = 4096 - offset;
|
1423 |
offset = 0;
|
1424 |
cpage++; |
1425 |
} |
1426 |
|
1427 |
qemu_sglist_add(&p->sgl, page, plen); |
1428 |
bytes -= plen; |
1429 |
} |
1430 |
return 0; |
1431 |
} |
1432 |
|
1433 |
static void ehci_finish_transfer(EHCIQueue *q, int status) |
1434 |
{ |
1435 |
uint32_t cpage, offset; |
1436 |
|
1437 |
if (status > 0) { |
1438 |
/* update cpage & offset */
|
1439 |
cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); |
1440 |
offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
|
1441 |
|
1442 |
offset += status; |
1443 |
cpage += offset >> QTD_BUFPTR_SH; |
1444 |
offset &= ~QTD_BUFPTR_MASK; |
1445 |
|
1446 |
set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); |
1447 |
q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
|
1448 |
q->qh.bufptr[0] |= offset;
|
1449 |
} |
1450 |
} |
1451 |
|
1452 |
static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) |
1453 |
{ |
1454 |
EHCIPacket *p; |
1455 |
EHCIState *s = port->opaque; |
1456 |
uint32_t portsc = s->portsc[port->index]; |
1457 |
|
1458 |
if (portsc & PORTSC_POWNER) {
|
1459 |
USBPort *companion = s->companion_ports[port->index]; |
1460 |
companion->ops->complete(companion, packet); |
1461 |
return;
|
1462 |
} |
1463 |
|
1464 |
p = container_of(packet, EHCIPacket, packet); |
1465 |
assert(p->async == EHCI_ASYNC_INFLIGHT); |
1466 |
|
1467 |
if (packet->result == USB_RET_REMOVE_FROM_QUEUE) {
|
1468 |
trace_usb_ehci_packet_action(p->queue, p, "remove");
|
1469 |
ehci_free_packet(p); |
1470 |
return;
|
1471 |
} |
1472 |
|
1473 |
trace_usb_ehci_packet_action(p->queue, p, "wakeup");
|
1474 |
p->async = EHCI_ASYNC_FINISHED; |
1475 |
p->usb_status = packet->result; |
1476 |
|
1477 |
if (p->queue->async) {
|
1478 |
qemu_bh_schedule(p->queue->ehci->async_bh); |
1479 |
} |
1480 |
} |
1481 |
|
1482 |
static void ehci_execute_complete(EHCIQueue *q) |
1483 |
{ |
1484 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
1485 |
|
1486 |
assert(p != NULL);
|
1487 |
assert(p->qtdaddr == q->qtdaddr); |
1488 |
assert(p->async == EHCI_ASYNC_INITIALIZED || |
1489 |
p->async == EHCI_ASYNC_FINISHED); |
1490 |
|
1491 |
DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
|
1492 |
q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status); |
1493 |
|
1494 |
if (p->usb_status < 0) { |
1495 |
switch (p->usb_status) {
|
1496 |
case USB_RET_IOERROR:
|
1497 |
case USB_RET_NODEV:
|
1498 |
q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); |
1499 |
set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
|
1500 |
ehci_raise_irq(q->ehci, USBSTS_ERRINT); |
1501 |
break;
|
1502 |
case USB_RET_STALL:
|
1503 |
q->qh.token |= QTD_TOKEN_HALT; |
1504 |
ehci_raise_irq(q->ehci, USBSTS_ERRINT); |
1505 |
break;
|
1506 |
case USB_RET_NAK:
|
1507 |
set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
|
1508 |
return; /* We're not done yet with this transaction */ |
1509 |
case USB_RET_BABBLE:
|
1510 |
q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); |
1511 |
ehci_raise_irq(q->ehci, USBSTS_ERRINT); |
1512 |
break;
|
1513 |
default:
|
1514 |
/* should not be triggerable */
|
1515 |
fprintf(stderr, "USB invalid response %d\n", p->usb_status);
|
1516 |
assert(0);
|
1517 |
break;
|
1518 |
} |
1519 |
} else {
|
1520 |
// TODO check 4.12 for splits
|
1521 |
uint32_t tbytes = get_field(q->qh.token, QTD_TOKEN_TBYTES); |
1522 |
|
1523 |
if (tbytes && p->pid == USB_TOKEN_IN) {
|
1524 |
tbytes -= p->usb_status; |
1525 |
if (tbytes) {
|
1526 |
/* 4.15.1.2 must raise int on a short input packet */
|
1527 |
ehci_raise_irq(q->ehci, USBSTS_INT); |
1528 |
} |
1529 |
} else {
|
1530 |
tbytes = 0;
|
1531 |
} |
1532 |
|
1533 |
DPRINTF("updating tbytes to %d\n", tbytes);
|
1534 |
set_field(&q->qh.token, tbytes, QTD_TOKEN_TBYTES); |
1535 |
} |
1536 |
ehci_finish_transfer(q, p->usb_status); |
1537 |
usb_packet_unmap(&p->packet, &p->sgl); |
1538 |
qemu_sglist_destroy(&p->sgl); |
1539 |
p->async = EHCI_ASYNC_NONE; |
1540 |
|
1541 |
q->qh.token ^= QTD_TOKEN_DTOGGLE; |
1542 |
q->qh.token &= ~QTD_TOKEN_ACTIVE; |
1543 |
|
1544 |
if (q->qh.token & QTD_TOKEN_IOC) {
|
1545 |
ehci_raise_irq(q->ehci, USBSTS_INT); |
1546 |
if (q->async) {
|
1547 |
q->ehci->int_req_by_async = true;
|
1548 |
} |
1549 |
} |
1550 |
} |
1551 |
|
1552 |
// 4.10.3
|
1553 |
|
1554 |
static int ehci_execute(EHCIPacket *p, const char *action) |
1555 |
{ |
1556 |
USBEndpoint *ep; |
1557 |
int ret;
|
1558 |
int endp;
|
1559 |
bool spd;
|
1560 |
|
1561 |
assert(p->async == EHCI_ASYNC_NONE || |
1562 |
p->async == EHCI_ASYNC_INITIALIZED); |
1563 |
|
1564 |
if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) {
|
1565 |
fprintf(stderr, "Attempting to execute inactive qtd\n");
|
1566 |
return USB_RET_PROCERR;
|
1567 |
} |
1568 |
|
1569 |
if (get_field(p->qtd.token, QTD_TOKEN_TBYTES) > BUFF_SIZE) {
|
1570 |
ehci_trace_guest_bug(p->queue->ehci, |
1571 |
"guest requested more bytes than allowed");
|
1572 |
return USB_RET_PROCERR;
|
1573 |
} |
1574 |
|
1575 |
p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH; |
1576 |
switch (p->pid) {
|
1577 |
case 0: |
1578 |
p->pid = USB_TOKEN_OUT; |
1579 |
break;
|
1580 |
case 1: |
1581 |
p->pid = USB_TOKEN_IN; |
1582 |
break;
|
1583 |
case 2: |
1584 |
p->pid = USB_TOKEN_SETUP; |
1585 |
break;
|
1586 |
default:
|
1587 |
fprintf(stderr, "bad token\n");
|
1588 |
break;
|
1589 |
} |
1590 |
|
1591 |
endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP); |
1592 |
ep = usb_ep_get(p->queue->dev, p->pid, endp); |
1593 |
|
1594 |
if (p->async == EHCI_ASYNC_NONE) {
|
1595 |
if (ehci_init_transfer(p) != 0) { |
1596 |
return USB_RET_PROCERR;
|
1597 |
} |
1598 |
|
1599 |
spd = (p->pid == USB_TOKEN_IN && NLPTR_TBIT(p->qtd.altnext) == 0);
|
1600 |
usb_packet_setup(&p->packet, p->pid, ep, p->qtdaddr, spd, |
1601 |
(p->qtd.token & QTD_TOKEN_IOC) != 0);
|
1602 |
usb_packet_map(&p->packet, &p->sgl); |
1603 |
p->async = EHCI_ASYNC_INITIALIZED; |
1604 |
} |
1605 |
|
1606 |
trace_usb_ehci_packet_action(p->queue, p, action); |
1607 |
ret = usb_handle_packet(p->queue->dev, &p->packet); |
1608 |
DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd endp %x ret %d\n",
|
1609 |
q->qhaddr, q->qh.next, q->qtdaddr, q->pid, |
1610 |
q->packet.iov.size, endp, ret); |
1611 |
|
1612 |
if (ret > BUFF_SIZE) {
|
1613 |
fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
|
1614 |
return USB_RET_PROCERR;
|
1615 |
} |
1616 |
|
1617 |
return ret;
|
1618 |
} |
1619 |
|
1620 |
/* 4.7.2
|
1621 |
*/
|
1622 |
|
1623 |
static int ehci_process_itd(EHCIState *ehci, |
1624 |
EHCIitd *itd, |
1625 |
uint32_t addr) |
1626 |
{ |
1627 |
USBDevice *dev; |
1628 |
USBEndpoint *ep; |
1629 |
int ret;
|
1630 |
uint32_t i, len, pid, dir, devaddr, endp; |
1631 |
uint32_t pg, off, ptr1, ptr2, max, mult; |
1632 |
|
1633 |
dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
|
1634 |
devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
|
1635 |
endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
|
1636 |
max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
|
1637 |
mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
|
1638 |
|
1639 |
for(i = 0; i < 8; i++) { |
1640 |
if (itd->transact[i] & ITD_XACT_ACTIVE) {
|
1641 |
pg = get_field(itd->transact[i], ITD_XACT_PGSEL); |
1642 |
off = itd->transact[i] & ITD_XACT_OFFSET_MASK; |
1643 |
ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); |
1644 |
ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
|
1645 |
len = get_field(itd->transact[i], ITD_XACT_LENGTH); |
1646 |
|
1647 |
if (len > max * mult) {
|
1648 |
len = max * mult; |
1649 |
} |
1650 |
|
1651 |
if (len > BUFF_SIZE) {
|
1652 |
return USB_RET_PROCERR;
|
1653 |
} |
1654 |
|
1655 |
qemu_sglist_init(&ehci->isgl, 2, ehci->dma);
|
1656 |
if (off + len > 4096) { |
1657 |
/* transfer crosses page border */
|
1658 |
uint32_t len2 = off + len - 4096;
|
1659 |
uint32_t len1 = len - len2; |
1660 |
qemu_sglist_add(&ehci->isgl, ptr1 + off, len1); |
1661 |
qemu_sglist_add(&ehci->isgl, ptr2, len2); |
1662 |
} else {
|
1663 |
qemu_sglist_add(&ehci->isgl, ptr1 + off, len); |
1664 |
} |
1665 |
|
1666 |
pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT; |
1667 |
|
1668 |
dev = ehci_find_device(ehci, devaddr); |
1669 |
ep = usb_ep_get(dev, pid, endp); |
1670 |
if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) {
|
1671 |
usb_packet_setup(&ehci->ipacket, pid, ep, addr, false,
|
1672 |
(itd->transact[i] & ITD_XACT_IOC) != 0);
|
1673 |
usb_packet_map(&ehci->ipacket, &ehci->isgl); |
1674 |
ret = usb_handle_packet(dev, &ehci->ipacket); |
1675 |
usb_packet_unmap(&ehci->ipacket, &ehci->isgl); |
1676 |
} else {
|
1677 |
DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
|
1678 |
ret = USB_RET_NAK; |
1679 |
} |
1680 |
qemu_sglist_destroy(&ehci->isgl); |
1681 |
|
1682 |
if (ret < 0) { |
1683 |
switch (ret) {
|
1684 |
default:
|
1685 |
fprintf(stderr, "Unexpected iso usb result: %d\n", ret);
|
1686 |
/* Fall through */
|
1687 |
case USB_RET_IOERROR:
|
1688 |
case USB_RET_NODEV:
|
1689 |
/* 3.3.2: XACTERR is only allowed on IN transactions */
|
1690 |
if (dir) {
|
1691 |
itd->transact[i] |= ITD_XACT_XACTERR; |
1692 |
ehci_raise_irq(ehci, USBSTS_ERRINT); |
1693 |
} |
1694 |
break;
|
1695 |
case USB_RET_BABBLE:
|
1696 |
itd->transact[i] |= ITD_XACT_BABBLE; |
1697 |
ehci_raise_irq(ehci, USBSTS_ERRINT); |
1698 |
break;
|
1699 |
case USB_RET_NAK:
|
1700 |
/* no data for us, so do a zero-length transfer */
|
1701 |
ret = 0;
|
1702 |
break;
|
1703 |
} |
1704 |
} |
1705 |
if (ret >= 0) { |
1706 |
if (!dir) {
|
1707 |
/* OUT */
|
1708 |
set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH); |
1709 |
} else {
|
1710 |
/* IN */
|
1711 |
set_field(&itd->transact[i], ret, ITD_XACT_LENGTH); |
1712 |
} |
1713 |
} |
1714 |
if (itd->transact[i] & ITD_XACT_IOC) {
|
1715 |
ehci_raise_irq(ehci, USBSTS_INT); |
1716 |
} |
1717 |
itd->transact[i] &= ~ITD_XACT_ACTIVE; |
1718 |
} |
1719 |
} |
1720 |
return 0; |
1721 |
} |
1722 |
|
1723 |
|
1724 |
/* This state is the entry point for asynchronous schedule
|
1725 |
* processing. Entry here consitutes a EHCI start event state (4.8.5)
|
1726 |
*/
|
1727 |
static int ehci_state_waitlisthead(EHCIState *ehci, int async) |
1728 |
{ |
1729 |
EHCIqh qh; |
1730 |
int i = 0; |
1731 |
int again = 0; |
1732 |
uint32_t entry = ehci->asynclistaddr; |
1733 |
|
1734 |
/* set reclamation flag at start event (4.8.6) */
|
1735 |
if (async) {
|
1736 |
ehci_set_usbsts(ehci, USBSTS_REC); |
1737 |
} |
1738 |
|
1739 |
ehci_queues_rip_unused(ehci, async); |
1740 |
|
1741 |
/* Find the head of the list (4.9.1.1) */
|
1742 |
for(i = 0; i < MAX_QH; i++) { |
1743 |
get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh, |
1744 |
sizeof(EHCIqh) >> 2); |
1745 |
ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
|
1746 |
|
1747 |
if (qh.epchar & QH_EPCHAR_H) {
|
1748 |
if (async) {
|
1749 |
entry |= (NLPTR_TYPE_QH << 1);
|
1750 |
} |
1751 |
|
1752 |
ehci_set_fetch_addr(ehci, async, entry); |
1753 |
ehci_set_state(ehci, async, EST_FETCHENTRY); |
1754 |
again = 1;
|
1755 |
goto out;
|
1756 |
} |
1757 |
|
1758 |
entry = qh.next; |
1759 |
if (entry == ehci->asynclistaddr) {
|
1760 |
break;
|
1761 |
} |
1762 |
} |
1763 |
|
1764 |
/* no head found for list. */
|
1765 |
|
1766 |
ehci_set_state(ehci, async, EST_ACTIVE); |
1767 |
|
1768 |
out:
|
1769 |
return again;
|
1770 |
} |
1771 |
|
1772 |
|
1773 |
/* This state is the entry point for periodic schedule processing as
|
1774 |
* well as being a continuation state for async processing.
|
1775 |
*/
|
1776 |
static int ehci_state_fetchentry(EHCIState *ehci, int async) |
1777 |
{ |
1778 |
int again = 0; |
1779 |
uint32_t entry = ehci_get_fetch_addr(ehci, async); |
1780 |
|
1781 |
if (NLPTR_TBIT(entry)) {
|
1782 |
ehci_set_state(ehci, async, EST_ACTIVE); |
1783 |
goto out;
|
1784 |
} |
1785 |
|
1786 |
/* section 4.8, only QH in async schedule */
|
1787 |
if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
|
1788 |
fprintf(stderr, "non queue head request in async schedule\n");
|
1789 |
return -1; |
1790 |
} |
1791 |
|
1792 |
switch (NLPTR_TYPE_GET(entry)) {
|
1793 |
case NLPTR_TYPE_QH:
|
1794 |
ehci_set_state(ehci, async, EST_FETCHQH); |
1795 |
again = 1;
|
1796 |
break;
|
1797 |
|
1798 |
case NLPTR_TYPE_ITD:
|
1799 |
ehci_set_state(ehci, async, EST_FETCHITD); |
1800 |
again = 1;
|
1801 |
break;
|
1802 |
|
1803 |
case NLPTR_TYPE_STITD:
|
1804 |
ehci_set_state(ehci, async, EST_FETCHSITD); |
1805 |
again = 1;
|
1806 |
break;
|
1807 |
|
1808 |
default:
|
1809 |
/* TODO: handle FSTN type */
|
1810 |
fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
|
1811 |
"which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
|
1812 |
return -1; |
1813 |
} |
1814 |
|
1815 |
out:
|
1816 |
return again;
|
1817 |
} |
1818 |
|
1819 |
static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) |
1820 |
{ |
1821 |
EHCIPacket *p; |
1822 |
uint32_t entry, devaddr, endp; |
1823 |
EHCIQueue *q; |
1824 |
EHCIqh qh; |
1825 |
|
1826 |
entry = ehci_get_fetch_addr(ehci, async); |
1827 |
q = ehci_find_queue_by_qh(ehci, entry, async); |
1828 |
if (NULL == q) { |
1829 |
q = ehci_alloc_queue(ehci, entry, async); |
1830 |
} |
1831 |
p = QTAILQ_FIRST(&q->packets); |
1832 |
|
1833 |
q->seen++; |
1834 |
if (q->seen > 1) { |
1835 |
/* we are going in circles -- stop processing */
|
1836 |
ehci_set_state(ehci, async, EST_ACTIVE); |
1837 |
q = NULL;
|
1838 |
goto out;
|
1839 |
} |
1840 |
|
1841 |
get_dwords(ehci, NLPTR_GET(q->qhaddr), |
1842 |
(uint32_t *) &qh, sizeof(EHCIqh) >> 2); |
1843 |
ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &qh); |
1844 |
|
1845 |
/*
|
1846 |
* The overlay area of the qh should never be changed by the guest,
|
1847 |
* except when idle, in which case the reset is a nop.
|
1848 |
*/
|
1849 |
devaddr = get_field(qh.epchar, QH_EPCHAR_DEVADDR); |
1850 |
endp = get_field(qh.epchar, QH_EPCHAR_EP); |
1851 |
if ((devaddr != get_field(q->qh.epchar, QH_EPCHAR_DEVADDR)) ||
|
1852 |
(endp != get_field(q->qh.epchar, QH_EPCHAR_EP)) || |
1853 |
(memcmp(&qh.current_qtd, &q->qh.current_qtd, |
1854 |
9 * sizeof(uint32_t)) != 0) || |
1855 |
(q->dev != NULL && q->dev->addr != devaddr)) {
|
1856 |
if (ehci_reset_queue(q) > 0) { |
1857 |
ehci_trace_guest_bug(ehci, "guest updated active QH");
|
1858 |
} |
1859 |
p = NULL;
|
1860 |
} |
1861 |
q->qh = qh; |
1862 |
|
1863 |
q->transact_ctr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
1864 |
if (q->transact_ctr == 0) { /* Guest bug in some versions of windows */ |
1865 |
q->transact_ctr = 4;
|
1866 |
} |
1867 |
|
1868 |
if (q->dev == NULL) { |
1869 |
q->dev = ehci_find_device(q->ehci, devaddr); |
1870 |
} |
1871 |
|
1872 |
if (p && p->async == EHCI_ASYNC_FINISHED) {
|
1873 |
/* I/O finished -- continue processing queue */
|
1874 |
trace_usb_ehci_packet_action(p->queue, p, "complete");
|
1875 |
ehci_set_state(ehci, async, EST_EXECUTING); |
1876 |
goto out;
|
1877 |
} |
1878 |
|
1879 |
if (async && (q->qh.epchar & QH_EPCHAR_H)) {
|
1880 |
|
1881 |
/* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
|
1882 |
if (ehci->usbsts & USBSTS_REC) {
|
1883 |
ehci_clear_usbsts(ehci, USBSTS_REC); |
1884 |
} else {
|
1885 |
DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
|
1886 |
" - done processing\n", q->qhaddr);
|
1887 |
ehci_set_state(ehci, async, EST_ACTIVE); |
1888 |
q = NULL;
|
1889 |
goto out;
|
1890 |
} |
1891 |
} |
1892 |
|
1893 |
#if EHCI_DEBUG
|
1894 |
if (q->qhaddr != q->qh.next) {
|
1895 |
DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
|
1896 |
q->qhaddr, |
1897 |
q->qh.epchar & QH_EPCHAR_H, |
1898 |
q->qh.token & QTD_TOKEN_HALT, |
1899 |
q->qh.token & QTD_TOKEN_ACTIVE, |
1900 |
q->qh.next); |
1901 |
} |
1902 |
#endif
|
1903 |
|
1904 |
if (q->qh.token & QTD_TOKEN_HALT) {
|
1905 |
ehci_set_state(ehci, async, EST_HORIZONTALQH); |
1906 |
|
1907 |
} else if ((q->qh.token & QTD_TOKEN_ACTIVE) && |
1908 |
(NLPTR_TBIT(q->qh.current_qtd) == 0)) {
|
1909 |
q->qtdaddr = q->qh.current_qtd; |
1910 |
ehci_set_state(ehci, async, EST_FETCHQTD); |
1911 |
|
1912 |
} else {
|
1913 |
/* EHCI spec version 1.0 Section 4.10.2 */
|
1914 |
ehci_set_state(ehci, async, EST_ADVANCEQUEUE); |
1915 |
} |
1916 |
|
1917 |
out:
|
1918 |
return q;
|
1919 |
} |
1920 |
|
1921 |
static int ehci_state_fetchitd(EHCIState *ehci, int async) |
1922 |
{ |
1923 |
uint32_t entry; |
1924 |
EHCIitd itd; |
1925 |
|
1926 |
assert(!async); |
1927 |
entry = ehci_get_fetch_addr(ehci, async); |
1928 |
|
1929 |
get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
1930 |
sizeof(EHCIitd) >> 2); |
1931 |
ehci_trace_itd(ehci, entry, &itd); |
1932 |
|
1933 |
if (ehci_process_itd(ehci, &itd, entry) != 0) { |
1934 |
return -1; |
1935 |
} |
1936 |
|
1937 |
put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
1938 |
sizeof(EHCIitd) >> 2); |
1939 |
ehci_set_fetch_addr(ehci, async, itd.next); |
1940 |
ehci_set_state(ehci, async, EST_FETCHENTRY); |
1941 |
|
1942 |
return 1; |
1943 |
} |
1944 |
|
1945 |
static int ehci_state_fetchsitd(EHCIState *ehci, int async) |
1946 |
{ |
1947 |
uint32_t entry; |
1948 |
EHCIsitd sitd; |
1949 |
|
1950 |
assert(!async); |
1951 |
entry = ehci_get_fetch_addr(ehci, async); |
1952 |
|
1953 |
get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd, |
1954 |
sizeof(EHCIsitd) >> 2); |
1955 |
ehci_trace_sitd(ehci, entry, &sitd); |
1956 |
|
1957 |
if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
|
1958 |
/* siTD is not active, nothing to do */;
|
1959 |
} else {
|
1960 |
/* TODO: split transfers are not implemented */
|
1961 |
fprintf(stderr, "WARNING: Skipping active siTD\n");
|
1962 |
} |
1963 |
|
1964 |
ehci_set_fetch_addr(ehci, async, sitd.next); |
1965 |
ehci_set_state(ehci, async, EST_FETCHENTRY); |
1966 |
return 1; |
1967 |
} |
1968 |
|
1969 |
/* Section 4.10.2 - paragraph 3 */
|
1970 |
static int ehci_state_advqueue(EHCIQueue *q) |
1971 |
{ |
1972 |
#if 0
|
1973 |
/* TO-DO: 4.10.2 - paragraph 2
|
1974 |
* if I-bit is set to 1 and QH is not active
|
1975 |
* go to horizontal QH
|
1976 |
*/
|
1977 |
if (I-bit set) {
|
1978 |
ehci_set_state(ehci, async, EST_HORIZONTALQH);
|
1979 |
goto out;
|
1980 |
}
|
1981 |
#endif
|
1982 |
|
1983 |
/*
|
1984 |
* want data and alt-next qTD is valid
|
1985 |
*/
|
1986 |
if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && |
1987 |
(NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
|
1988 |
q->qtdaddr = q->qh.altnext_qtd; |
1989 |
ehci_set_state(q->ehci, q->async, EST_FETCHQTD); |
1990 |
|
1991 |
/*
|
1992 |
* next qTD is valid
|
1993 |
*/
|
1994 |
} else if (NLPTR_TBIT(q->qh.next_qtd) == 0) { |
1995 |
q->qtdaddr = q->qh.next_qtd; |
1996 |
ehci_set_state(q->ehci, q->async, EST_FETCHQTD); |
1997 |
|
1998 |
/*
|
1999 |
* no valid qTD, try next QH
|
2000 |
*/
|
2001 |
} else {
|
2002 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
2003 |
} |
2004 |
|
2005 |
return 1; |
2006 |
} |
2007 |
|
2008 |
/* Section 4.10.2 - paragraph 4 */
|
2009 |
static int ehci_state_fetchqtd(EHCIQueue *q) |
2010 |
{ |
2011 |
EHCIqtd qtd; |
2012 |
EHCIPacket *p; |
2013 |
int again = 1; |
2014 |
|
2015 |
get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd, |
2016 |
sizeof(EHCIqtd) >> 2); |
2017 |
ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd); |
2018 |
|
2019 |
p = QTAILQ_FIRST(&q->packets); |
2020 |
if (p != NULL) { |
2021 |
if (p->qtdaddr != q->qtdaddr ||
|
2022 |
(!NLPTR_TBIT(p->qtd.next) && (p->qtd.next != qtd.next)) || |
2023 |
(!NLPTR_TBIT(p->qtd.altnext) && (p->qtd.altnext != qtd.altnext)) || |
2024 |
p->qtd.bufptr[0] != qtd.bufptr[0]) { |
2025 |
ehci_cancel_queue(q); |
2026 |
ehci_trace_guest_bug(q->ehci, "guest updated active QH or qTD");
|
2027 |
p = NULL;
|
2028 |
} else {
|
2029 |
p->qtd = qtd; |
2030 |
ehci_qh_do_overlay(q); |
2031 |
} |
2032 |
} |
2033 |
|
2034 |
if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
|
2035 |
if (p != NULL) { |
2036 |
/* transfer canceled by guest (clear active) */
|
2037 |
ehci_cancel_queue(q); |
2038 |
p = NULL;
|
2039 |
} |
2040 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
2041 |
} else if (p != NULL) { |
2042 |
switch (p->async) {
|
2043 |
case EHCI_ASYNC_NONE:
|
2044 |
case EHCI_ASYNC_INITIALIZED:
|
2045 |
/* Not yet executed (MULT), or previously nacked (int) packet */
|
2046 |
ehci_set_state(q->ehci, q->async, EST_EXECUTE); |
2047 |
break;
|
2048 |
case EHCI_ASYNC_INFLIGHT:
|
2049 |
/* Check if the guest has added new tds to the queue */
|
2050 |
again = (ehci_fill_queue(QTAILQ_LAST(&q->packets, pkts_head)) == |
2051 |
USB_RET_PROCERR) ? -1 : 1; |
2052 |
/* Unfinished async handled packet, go horizontal */
|
2053 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
2054 |
break;
|
2055 |
case EHCI_ASYNC_FINISHED:
|
2056 |
/*
|
2057 |
* We get here when advqueue moves to a packet which is already
|
2058 |
* finished, which can happen with packets queued up by fill_queue
|
2059 |
*/
|
2060 |
ehci_set_state(q->ehci, q->async, EST_EXECUTING); |
2061 |
break;
|
2062 |
} |
2063 |
} else {
|
2064 |
p = ehci_alloc_packet(q); |
2065 |
p->qtdaddr = q->qtdaddr; |
2066 |
p->qtd = qtd; |
2067 |
ehci_set_state(q->ehci, q->async, EST_EXECUTE); |
2068 |
} |
2069 |
|
2070 |
return again;
|
2071 |
} |
2072 |
|
2073 |
static int ehci_state_horizqh(EHCIQueue *q) |
2074 |
{ |
2075 |
int again = 0; |
2076 |
|
2077 |
if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {
|
2078 |
ehci_set_fetch_addr(q->ehci, q->async, q->qh.next); |
2079 |
ehci_set_state(q->ehci, q->async, EST_FETCHENTRY); |
2080 |
again = 1;
|
2081 |
} else {
|
2082 |
ehci_set_state(q->ehci, q->async, EST_ACTIVE); |
2083 |
} |
2084 |
|
2085 |
return again;
|
2086 |
} |
2087 |
|
2088 |
static int ehci_fill_queue(EHCIPacket *p) |
2089 |
{ |
2090 |
USBEndpoint *ep = p->packet.ep; |
2091 |
EHCIQueue *q = p->queue; |
2092 |
EHCIqtd qtd = p->qtd; |
2093 |
uint32_t qtdaddr, start_addr = p->qtdaddr; |
2094 |
|
2095 |
for (;;) {
|
2096 |
if (NLPTR_TBIT(qtd.next) != 0) { |
2097 |
break;
|
2098 |
} |
2099 |
qtdaddr = qtd.next; |
2100 |
/*
|
2101 |
* Detect circular td lists, Windows creates these, counting on the
|
2102 |
* active bit going low after execution to make the queue stop.
|
2103 |
*/
|
2104 |
if (qtdaddr == start_addr) {
|
2105 |
break;
|
2106 |
} |
2107 |
get_dwords(q->ehci, NLPTR_GET(qtdaddr), |
2108 |
(uint32_t *) &qtd, sizeof(EHCIqtd) >> 2); |
2109 |
ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd); |
2110 |
if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
|
2111 |
break;
|
2112 |
} |
2113 |
p = ehci_alloc_packet(q); |
2114 |
p->qtdaddr = qtdaddr; |
2115 |
p->qtd = qtd; |
2116 |
p->usb_status = ehci_execute(p, "queue");
|
2117 |
if (p->usb_status == USB_RET_PROCERR) {
|
2118 |
break;
|
2119 |
} |
2120 |
assert(p->usb_status == USB_RET_ASYNC); |
2121 |
p->async = EHCI_ASYNC_INFLIGHT; |
2122 |
} |
2123 |
if (p->usb_status != USB_RET_PROCERR) {
|
2124 |
usb_device_flush_ep_queue(ep->dev, ep); |
2125 |
} |
2126 |
return p->usb_status;
|
2127 |
} |
2128 |
|
2129 |
static int ehci_state_execute(EHCIQueue *q) |
2130 |
{ |
2131 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
2132 |
int again = 0; |
2133 |
|
2134 |
assert(p != NULL);
|
2135 |
assert(p->qtdaddr == q->qtdaddr); |
2136 |
|
2137 |
if (ehci_qh_do_overlay(q) != 0) { |
2138 |
return -1; |
2139 |
} |
2140 |
|
2141 |
// TODO verify enough time remains in the uframe as in 4.4.1.1
|
2142 |
// TODO write back ptr to async list when done or out of time
|
2143 |
|
2144 |
/* 4.10.3, bottom of page 82, go horizontal on transaction counter == 0 */
|
2145 |
if (!q->async && q->transact_ctr == 0) { |
2146 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
2147 |
again = 1;
|
2148 |
goto out;
|
2149 |
} |
2150 |
|
2151 |
if (q->async) {
|
2152 |
ehci_set_usbsts(q->ehci, USBSTS_REC); |
2153 |
} |
2154 |
|
2155 |
p->usb_status = ehci_execute(p, "process");
|
2156 |
if (p->usb_status == USB_RET_PROCERR) {
|
2157 |
again = -1;
|
2158 |
goto out;
|
2159 |
} |
2160 |
if (p->usb_status == USB_RET_ASYNC) {
|
2161 |
ehci_flush_qh(q); |
2162 |
trace_usb_ehci_packet_action(p->queue, p, "async");
|
2163 |
p->async = EHCI_ASYNC_INFLIGHT; |
2164 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
2165 |
if (q->async) {
|
2166 |
again = (ehci_fill_queue(p) == USB_RET_PROCERR) ? -1 : 1; |
2167 |
} else {
|
2168 |
again = 1;
|
2169 |
} |
2170 |
goto out;
|
2171 |
} |
2172 |
|
2173 |
ehci_set_state(q->ehci, q->async, EST_EXECUTING); |
2174 |
again = 1;
|
2175 |
|
2176 |
out:
|
2177 |
return again;
|
2178 |
} |
2179 |
|
2180 |
static int ehci_state_executing(EHCIQueue *q) |
2181 |
{ |
2182 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
2183 |
|
2184 |
assert(p != NULL);
|
2185 |
assert(p->qtdaddr == q->qtdaddr); |
2186 |
|
2187 |
ehci_execute_complete(q); |
2188 |
|
2189 |
/* 4.10.3 */
|
2190 |
if (!q->async && q->transact_ctr > 0) { |
2191 |
q->transact_ctr--; |
2192 |
} |
2193 |
|
2194 |
/* 4.10.5 */
|
2195 |
if (p->usb_status == USB_RET_NAK) {
|
2196 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
2197 |
} else {
|
2198 |
ehci_set_state(q->ehci, q->async, EST_WRITEBACK); |
2199 |
} |
2200 |
|
2201 |
ehci_flush_qh(q); |
2202 |
return 1; |
2203 |
} |
2204 |
|
2205 |
|
2206 |
static int ehci_state_writeback(EHCIQueue *q) |
2207 |
{ |
2208 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
2209 |
uint32_t *qtd, addr; |
2210 |
int again = 0; |
2211 |
|
2212 |
/* Write back the QTD from the QH area */
|
2213 |
assert(p != NULL);
|
2214 |
assert(p->qtdaddr == q->qtdaddr); |
2215 |
|
2216 |
ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd); |
2217 |
qtd = (uint32_t *) &q->qh.next_qtd; |
2218 |
addr = NLPTR_GET(p->qtdaddr); |
2219 |
put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2); |
2220 |
ehci_free_packet(p); |
2221 |
|
2222 |
/*
|
2223 |
* EHCI specs say go horizontal here.
|
2224 |
*
|
2225 |
* We can also advance the queue here for performance reasons. We
|
2226 |
* need to take care to only take that shortcut in case we've
|
2227 |
* processed the qtd just written back without errors, i.e. halt
|
2228 |
* bit is clear.
|
2229 |
*/
|
2230 |
if (q->qh.token & QTD_TOKEN_HALT) {
|
2231 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
2232 |
again = 1;
|
2233 |
} else {
|
2234 |
ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE); |
2235 |
again = 1;
|
2236 |
} |
2237 |
return again;
|
2238 |
} |
2239 |
|
2240 |
/*
|
2241 |
* This is the state machine that is common to both async and periodic
|
2242 |
*/
|
2243 |
|
2244 |
static void ehci_advance_state(EHCIState *ehci, int async) |
2245 |
{ |
2246 |
EHCIQueue *q = NULL;
|
2247 |
int again;
|
2248 |
|
2249 |
do {
|
2250 |
switch(ehci_get_state(ehci, async)) {
|
2251 |
case EST_WAITLISTHEAD:
|
2252 |
again = ehci_state_waitlisthead(ehci, async); |
2253 |
break;
|
2254 |
|
2255 |
case EST_FETCHENTRY:
|
2256 |
again = ehci_state_fetchentry(ehci, async); |
2257 |
break;
|
2258 |
|
2259 |
case EST_FETCHQH:
|
2260 |
q = ehci_state_fetchqh(ehci, async); |
2261 |
if (q != NULL) { |
2262 |
assert(q->async == async); |
2263 |
again = 1;
|
2264 |
} else {
|
2265 |
again = 0;
|
2266 |
} |
2267 |
break;
|
2268 |
|
2269 |
case EST_FETCHITD:
|
2270 |
again = ehci_state_fetchitd(ehci, async); |
2271 |
break;
|
2272 |
|
2273 |
case EST_FETCHSITD:
|
2274 |
again = ehci_state_fetchsitd(ehci, async); |
2275 |
break;
|
2276 |
|
2277 |
case EST_ADVANCEQUEUE:
|
2278 |
again = ehci_state_advqueue(q); |
2279 |
break;
|
2280 |
|
2281 |
case EST_FETCHQTD:
|
2282 |
again = ehci_state_fetchqtd(q); |
2283 |
break;
|
2284 |
|
2285 |
case EST_HORIZONTALQH:
|
2286 |
again = ehci_state_horizqh(q); |
2287 |
break;
|
2288 |
|
2289 |
case EST_EXECUTE:
|
2290 |
again = ehci_state_execute(q); |
2291 |
if (async) {
|
2292 |
ehci->async_stepdown = 0;
|
2293 |
} |
2294 |
break;
|
2295 |
|
2296 |
case EST_EXECUTING:
|
2297 |
assert(q != NULL);
|
2298 |
if (async) {
|
2299 |
ehci->async_stepdown = 0;
|
2300 |
} |
2301 |
again = ehci_state_executing(q); |
2302 |
break;
|
2303 |
|
2304 |
case EST_WRITEBACK:
|
2305 |
assert(q != NULL);
|
2306 |
again = ehci_state_writeback(q); |
2307 |
break;
|
2308 |
|
2309 |
default:
|
2310 |
fprintf(stderr, "Bad state!\n");
|
2311 |
again = -1;
|
2312 |
assert(0);
|
2313 |
break;
|
2314 |
} |
2315 |
|
2316 |
if (again < 0) { |
2317 |
fprintf(stderr, "processing error - resetting ehci HC\n");
|
2318 |
ehci_reset(ehci); |
2319 |
again = 0;
|
2320 |
} |
2321 |
} |
2322 |
while (again);
|
2323 |
} |
2324 |
|
2325 |
static void ehci_advance_async_state(EHCIState *ehci) |
2326 |
{ |
2327 |
const int async = 1; |
2328 |
|
2329 |
switch(ehci_get_state(ehci, async)) {
|
2330 |
case EST_INACTIVE:
|
2331 |
if (!ehci_async_enabled(ehci)) {
|
2332 |
break;
|
2333 |
} |
2334 |
ehci_set_state(ehci, async, EST_ACTIVE); |
2335 |
// No break, fall through to ACTIVE
|
2336 |
|
2337 |
case EST_ACTIVE:
|
2338 |
if (!ehci_async_enabled(ehci)) {
|
2339 |
ehci_queues_rip_all(ehci, async); |
2340 |
ehci_set_state(ehci, async, EST_INACTIVE); |
2341 |
break;
|
2342 |
} |
2343 |
|
2344 |
/* make sure guest has acknowledged the doorbell interrupt */
|
2345 |
/* TO-DO: is this really needed? */
|
2346 |
if (ehci->usbsts & USBSTS_IAA) {
|
2347 |
DPRINTF("IAA status bit still set.\n");
|
2348 |
break;
|
2349 |
} |
2350 |
|
2351 |
/* check that address register has been set */
|
2352 |
if (ehci->asynclistaddr == 0) { |
2353 |
break;
|
2354 |
} |
2355 |
|
2356 |
ehci_set_state(ehci, async, EST_WAITLISTHEAD); |
2357 |
ehci_advance_state(ehci, async); |
2358 |
|
2359 |
/* If the doorbell is set, the guest wants to make a change to the
|
2360 |
* schedule. The host controller needs to release cached data.
|
2361 |
* (section 4.8.2)
|
2362 |
*/
|
2363 |
if (ehci->usbcmd & USBCMD_IAAD) {
|
2364 |
/* Remove all unseen qhs from the async qhs queue */
|
2365 |
ehci_queues_rip_unseen(ehci, async); |
2366 |
trace_usb_ehci_doorbell_ack(); |
2367 |
ehci->usbcmd &= ~USBCMD_IAAD; |
2368 |
ehci_raise_irq(ehci, USBSTS_IAA); |
2369 |
} |
2370 |
break;
|
2371 |
|
2372 |
default:
|
2373 |
/* this should only be due to a developer mistake */
|
2374 |
fprintf(stderr, "ehci: Bad asynchronous state %d. "
|
2375 |
"Resetting to active\n", ehci->astate);
|
2376 |
assert(0);
|
2377 |
} |
2378 |
} |
2379 |
|
2380 |
static void ehci_advance_periodic_state(EHCIState *ehci) |
2381 |
{ |
2382 |
uint32_t entry; |
2383 |
uint32_t list; |
2384 |
const int async = 0; |
2385 |
|
2386 |
// 4.6
|
2387 |
|
2388 |
switch(ehci_get_state(ehci, async)) {
|
2389 |
case EST_INACTIVE:
|
2390 |
if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) { |
2391 |
ehci_set_state(ehci, async, EST_ACTIVE); |
2392 |
// No break, fall through to ACTIVE
|
2393 |
} else
|
2394 |
break;
|
2395 |
|
2396 |
case EST_ACTIVE:
|
2397 |
if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) { |
2398 |
ehci_queues_rip_all(ehci, async); |
2399 |
ehci_set_state(ehci, async, EST_INACTIVE); |
2400 |
break;
|
2401 |
} |
2402 |
|
2403 |
list = ehci->periodiclistbase & 0xfffff000;
|
2404 |
/* check that register has been set */
|
2405 |
if (list == 0) { |
2406 |
break;
|
2407 |
} |
2408 |
list |= ((ehci->frindex & 0x1ff8) >> 1); |
2409 |
|
2410 |
dma_memory_read(ehci->dma, list, &entry, sizeof entry);
|
2411 |
entry = le32_to_cpu(entry); |
2412 |
|
2413 |
DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
|
2414 |
ehci->frindex / 8, list, entry);
|
2415 |
ehci_set_fetch_addr(ehci, async,entry); |
2416 |
ehci_set_state(ehci, async, EST_FETCHENTRY); |
2417 |
ehci_advance_state(ehci, async); |
2418 |
ehci_queues_rip_unused(ehci, async); |
2419 |
break;
|
2420 |
|
2421 |
default:
|
2422 |
/* this should only be due to a developer mistake */
|
2423 |
fprintf(stderr, "ehci: Bad periodic state %d. "
|
2424 |
"Resetting to active\n", ehci->pstate);
|
2425 |
assert(0);
|
2426 |
} |
2427 |
} |
2428 |
|
2429 |
static void ehci_update_frindex(EHCIState *ehci, int frames) |
2430 |
{ |
2431 |
int i;
|
2432 |
|
2433 |
if (!ehci_enabled(ehci)) {
|
2434 |
return;
|
2435 |
} |
2436 |
|
2437 |
for (i = 0; i < frames; i++) { |
2438 |
ehci->frindex += 8;
|
2439 |
|
2440 |
if (ehci->frindex == 0x00002000) { |
2441 |
ehci_raise_irq(ehci, USBSTS_FLR); |
2442 |
} |
2443 |
|
2444 |
if (ehci->frindex == 0x00004000) { |
2445 |
ehci_raise_irq(ehci, USBSTS_FLR); |
2446 |
ehci->frindex = 0;
|
2447 |
if (ehci->usbsts_frindex >= 0x00004000) { |
2448 |
ehci->usbsts_frindex -= 0x00004000;
|
2449 |
} else {
|
2450 |
ehci->usbsts_frindex = 0;
|
2451 |
} |
2452 |
} |
2453 |
} |
2454 |
} |
2455 |
|
2456 |
static void ehci_frame_timer(void *opaque) |
2457 |
{ |
2458 |
EHCIState *ehci = opaque; |
2459 |
int need_timer = 0; |
2460 |
int64_t expire_time, t_now; |
2461 |
uint64_t ns_elapsed; |
2462 |
int frames, skipped_frames;
|
2463 |
int i;
|
2464 |
|
2465 |
t_now = qemu_get_clock_ns(vm_clock); |
2466 |
ns_elapsed = t_now - ehci->last_run_ns; |
2467 |
frames = ns_elapsed / FRAME_TIMER_NS; |
2468 |
|
2469 |
if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) {
|
2470 |
need_timer++; |
2471 |
ehci->async_stepdown = 0;
|
2472 |
|
2473 |
if (frames > ehci->maxframes) {
|
2474 |
skipped_frames = frames - ehci->maxframes; |
2475 |
ehci_update_frindex(ehci, skipped_frames); |
2476 |
ehci->last_run_ns += FRAME_TIMER_NS * skipped_frames; |
2477 |
frames -= skipped_frames; |
2478 |
DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
|
2479 |
} |
2480 |
|
2481 |
for (i = 0; i < frames; i++) { |
2482 |
/*
|
2483 |
* If we're running behind schedule, we should not catch up
|
2484 |
* too fast, as that will make some guests unhappy:
|
2485 |
* 1) We must process a minimum of MIN_FR_PER_TICK frames,
|
2486 |
* otherwise we will never catch up
|
2487 |
* 2) Process frames until the guest has requested an irq (IOC)
|
2488 |
*/
|
2489 |
if (i >= MIN_FR_PER_TICK) {
|
2490 |
ehci_commit_irq(ehci); |
2491 |
if ((ehci->usbsts & USBINTR_MASK) & ehci->usbintr) {
|
2492 |
break;
|
2493 |
} |
2494 |
} |
2495 |
ehci_update_frindex(ehci, 1);
|
2496 |
ehci_advance_periodic_state(ehci); |
2497 |
ehci->last_run_ns += FRAME_TIMER_NS; |
2498 |
} |
2499 |
} else {
|
2500 |
if (ehci->async_stepdown < ehci->maxframes / 2) { |
2501 |
ehci->async_stepdown++; |
2502 |
} |
2503 |
ehci_update_frindex(ehci, frames); |
2504 |
ehci->last_run_ns += FRAME_TIMER_NS * frames; |
2505 |
} |
2506 |
|
2507 |
/* Async is not inside loop since it executes everything it can once
|
2508 |
* called
|
2509 |
*/
|
2510 |
if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) {
|
2511 |
need_timer++; |
2512 |
ehci_advance_async_state(ehci); |
2513 |
} |
2514 |
|
2515 |
ehci_commit_irq(ehci); |
2516 |
if (ehci->usbsts_pending) {
|
2517 |
need_timer++; |
2518 |
ehci->async_stepdown = 0;
|
2519 |
} |
2520 |
|
2521 |
if (need_timer) {
|
2522 |
/* If we've raised int, we speed up the timer, so that we quickly
|
2523 |
* notice any new packets queued up in response */
|
2524 |
if (ehci->int_req_by_async && (ehci->usbsts & USBSTS_INT)) {
|
2525 |
expire_time = t_now + get_ticks_per_sec() / (FRAME_TIMER_FREQ * 2);
|
2526 |
ehci->int_req_by_async = false;
|
2527 |
} else {
|
2528 |
expire_time = t_now + (get_ticks_per_sec() |
2529 |
* (ehci->async_stepdown+1) / FRAME_TIMER_FREQ);
|
2530 |
} |
2531 |
qemu_mod_timer(ehci->frame_timer, expire_time); |
2532 |
} |
2533 |
} |
2534 |
|
2535 |
static const MemoryRegionOps ehci_mmio_caps_ops = { |
2536 |
.read = ehci_caps_read, |
2537 |
.valid.min_access_size = 1,
|
2538 |
.valid.max_access_size = 4,
|
2539 |
.impl.min_access_size = 1,
|
2540 |
.impl.max_access_size = 1,
|
2541 |
.endianness = DEVICE_LITTLE_ENDIAN, |
2542 |
}; |
2543 |
|
2544 |
static const MemoryRegionOps ehci_mmio_opreg_ops = { |
2545 |
.read = ehci_opreg_read, |
2546 |
.write = ehci_opreg_write, |
2547 |
.valid.min_access_size = 4,
|
2548 |
.valid.max_access_size = 4,
|
2549 |
.endianness = DEVICE_LITTLE_ENDIAN, |
2550 |
}; |
2551 |
|
2552 |
static const MemoryRegionOps ehci_mmio_port_ops = { |
2553 |
.read = ehci_port_read, |
2554 |
.write = ehci_port_write, |
2555 |
.valid.min_access_size = 4,
|
2556 |
.valid.max_access_size = 4,
|
2557 |
.endianness = DEVICE_LITTLE_ENDIAN, |
2558 |
}; |
2559 |
|
2560 |
static int usb_ehci_pci_initfn(PCIDevice *dev); |
2561 |
|
2562 |
static USBPortOps ehci_port_ops = {
|
2563 |
.attach = ehci_attach, |
2564 |
.detach = ehci_detach, |
2565 |
.child_detach = ehci_child_detach, |
2566 |
.wakeup = ehci_wakeup, |
2567 |
.complete = ehci_async_complete_packet, |
2568 |
}; |
2569 |
|
2570 |
static USBBusOps ehci_bus_ops = {
|
2571 |
.register_companion = ehci_register_companion, |
2572 |
}; |
2573 |
|
2574 |
static int usb_ehci_post_load(void *opaque, int version_id) |
2575 |
{ |
2576 |
EHCIState *s = opaque; |
2577 |
int i;
|
2578 |
|
2579 |
for (i = 0; i < NB_PORTS; i++) { |
2580 |
USBPort *companion = s->companion_ports[i]; |
2581 |
if (companion == NULL) { |
2582 |
continue;
|
2583 |
} |
2584 |
if (s->portsc[i] & PORTSC_POWNER) {
|
2585 |
companion->dev = s->ports[i].dev; |
2586 |
} else {
|
2587 |
companion->dev = NULL;
|
2588 |
} |
2589 |
} |
2590 |
|
2591 |
return 0; |
2592 |
} |
2593 |
|
2594 |
static void usb_ehci_vm_state_change(void *opaque, int running, RunState state) |
2595 |
{ |
2596 |
EHCIState *ehci = opaque; |
2597 |
|
2598 |
/*
|
2599 |
* We don't migrate the EHCIQueue-s, instead we rebuild them for the
|
2600 |
* schedule in guest memory. We must do the rebuilt ASAP, so that
|
2601 |
* USB-devices which have async handled packages have a packet in the
|
2602 |
* ep queue to match the completion with.
|
2603 |
*/
|
2604 |
if (state == RUN_STATE_RUNNING) {
|
2605 |
ehci_advance_async_state(ehci); |
2606 |
} |
2607 |
|
2608 |
/*
|
2609 |
* The schedule rebuilt from guest memory could cause the migration dest
|
2610 |
* to miss a QH unlink, and fail to cancel packets, since the unlinked QH
|
2611 |
* will never have existed on the destination. Therefor we must flush the
|
2612 |
* async schedule on savevm to catch any not yet noticed unlinks.
|
2613 |
*/
|
2614 |
if (state == RUN_STATE_SAVE_VM) {
|
2615 |
ehci_advance_async_state(ehci); |
2616 |
ehci_queues_rip_unseen(ehci, 1);
|
2617 |
} |
2618 |
} |
2619 |
|
2620 |
static const VMStateDescription vmstate_ehci = { |
2621 |
.name = "ehci-core",
|
2622 |
.version_id = 2,
|
2623 |
.minimum_version_id = 1,
|
2624 |
.post_load = usb_ehci_post_load, |
2625 |
.fields = (VMStateField[]) { |
2626 |
/* mmio registers */
|
2627 |
VMSTATE_UINT32(usbcmd, EHCIState), |
2628 |
VMSTATE_UINT32(usbsts, EHCIState), |
2629 |
VMSTATE_UINT32_V(usbsts_pending, EHCIState, 2),
|
2630 |
VMSTATE_UINT32_V(usbsts_frindex, EHCIState, 2),
|
2631 |
VMSTATE_UINT32(usbintr, EHCIState), |
2632 |
VMSTATE_UINT32(frindex, EHCIState), |
2633 |
VMSTATE_UINT32(ctrldssegment, EHCIState), |
2634 |
VMSTATE_UINT32(periodiclistbase, EHCIState), |
2635 |
VMSTATE_UINT32(asynclistaddr, EHCIState), |
2636 |
VMSTATE_UINT32(configflag, EHCIState), |
2637 |
VMSTATE_UINT32(portsc[0], EHCIState),
|
2638 |
VMSTATE_UINT32(portsc[1], EHCIState),
|
2639 |
VMSTATE_UINT32(portsc[2], EHCIState),
|
2640 |
VMSTATE_UINT32(portsc[3], EHCIState),
|
2641 |
VMSTATE_UINT32(portsc[4], EHCIState),
|
2642 |
VMSTATE_UINT32(portsc[5], EHCIState),
|
2643 |
/* frame timer */
|
2644 |
VMSTATE_TIMER(frame_timer, EHCIState), |
2645 |
VMSTATE_UINT64(last_run_ns, EHCIState), |
2646 |
VMSTATE_UINT32(async_stepdown, EHCIState), |
2647 |
/* schedule state */
|
2648 |
VMSTATE_UINT32(astate, EHCIState), |
2649 |
VMSTATE_UINT32(pstate, EHCIState), |
2650 |
VMSTATE_UINT32(a_fetch_addr, EHCIState), |
2651 |
VMSTATE_UINT32(p_fetch_addr, EHCIState), |
2652 |
VMSTATE_END_OF_LIST() |
2653 |
} |
2654 |
}; |
2655 |
|
2656 |
static const VMStateDescription vmstate_ehci_pci = { |
2657 |
.name = "ehci",
|
2658 |
.version_id = 2,
|
2659 |
.minimum_version_id = 1,
|
2660 |
.post_load = usb_ehci_post_load, |
2661 |
.fields = (VMStateField[]) { |
2662 |
VMSTATE_PCI_DEVICE(pcidev, EHCIPCIState), |
2663 |
VMSTATE_STRUCT(ehci, EHCIPCIState, 2, vmstate_ehci, EHCIState),
|
2664 |
} |
2665 |
}; |
2666 |
|
2667 |
static Property ehci_pci_properties[] = {
|
2668 |
DEFINE_PROP_UINT32("maxframes", EHCIPCIState, ehci.maxframes, 128), |
2669 |
DEFINE_PROP_END_OF_LIST(), |
2670 |
}; |
2671 |
|
2672 |
static void ehci_class_init(ObjectClass *klass, void *data) |
2673 |
{ |
2674 |
DeviceClass *dc = DEVICE_CLASS(klass); |
2675 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2676 |
|
2677 |
k->init = usb_ehci_pci_initfn; |
2678 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
2679 |
k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */
|
2680 |
k->revision = 0x10;
|
2681 |
k->class_id = PCI_CLASS_SERIAL_USB; |
2682 |
dc->vmsd = &vmstate_ehci; |
2683 |
dc->props = ehci_pci_properties; |
2684 |
} |
2685 |
|
2686 |
static TypeInfo ehci_info = {
|
2687 |
.name = "usb-ehci",
|
2688 |
.parent = TYPE_PCI_DEVICE, |
2689 |
.instance_size = sizeof(EHCIState),
|
2690 |
.class_init = ehci_class_init, |
2691 |
}; |
2692 |
|
2693 |
static void ich9_ehci_class_init(ObjectClass *klass, void *data) |
2694 |
{ |
2695 |
DeviceClass *dc = DEVICE_CLASS(klass); |
2696 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2697 |
|
2698 |
k->init = usb_ehci_pci_initfn; |
2699 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
2700 |
k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1; |
2701 |
k->revision = 0x03;
|
2702 |
k->class_id = PCI_CLASS_SERIAL_USB; |
2703 |
dc->vmsd = &vmstate_ehci; |
2704 |
dc->props = ehci_pci_properties; |
2705 |
} |
2706 |
|
2707 |
static TypeInfo ich9_ehci_info = {
|
2708 |
.name = "ich9-usb-ehci1",
|
2709 |
.parent = TYPE_PCI_DEVICE, |
2710 |
.instance_size = sizeof(EHCIState),
|
2711 |
.class_init = ich9_ehci_class_init, |
2712 |
}; |
2713 |
|
2714 |
static void usb_ehci_initfn(EHCIState *s, DeviceState *dev) |
2715 |
{ |
2716 |
int i;
|
2717 |
|
2718 |
/* 2.2 host controller interface version */
|
2719 |
s->caps[0x00] = (uint8_t)(s->opregbase - s->capsbase);
|
2720 |
s->caps[0x01] = 0x00; |
2721 |
s->caps[0x02] = 0x00; |
2722 |
s->caps[0x03] = 0x01; /* HC version */ |
2723 |
s->caps[0x04] = NB_PORTS; /* Number of downstream ports */ |
2724 |
s->caps[0x05] = 0x00; /* No companion ports at present */ |
2725 |
s->caps[0x06] = 0x00; |
2726 |
s->caps[0x07] = 0x00; |
2727 |
s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */ |
2728 |
s->caps[0x0a] = 0x00; |
2729 |
s->caps[0x0b] = 0x00; |
2730 |
|
2731 |
usb_bus_new(&s->bus, &ehci_bus_ops, dev); |
2732 |
for(i = 0; i < NB_PORTS; i++) { |
2733 |
usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, |
2734 |
USB_SPEED_MASK_HIGH); |
2735 |
s->ports[i].dev = 0;
|
2736 |
} |
2737 |
|
2738 |
s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); |
2739 |
s->async_bh = qemu_bh_new(ehci_frame_timer, s); |
2740 |
QTAILQ_INIT(&s->aqueues); |
2741 |
QTAILQ_INIT(&s->pqueues); |
2742 |
usb_packet_init(&s->ipacket); |
2743 |
|
2744 |
qemu_register_reset(ehci_reset, s); |
2745 |
qemu_add_vm_change_state_handler(usb_ehci_vm_state_change, s); |
2746 |
|
2747 |
memory_region_init(&s->mem, "ehci", MMIO_SIZE);
|
2748 |
memory_region_init_io(&s->mem_caps, &ehci_mmio_caps_ops, s, |
2749 |
"capabilities", CAPA_SIZE);
|
2750 |
memory_region_init_io(&s->mem_opreg, &ehci_mmio_opreg_ops, s, |
2751 |
"operational", PORTSC_BEGIN);
|
2752 |
memory_region_init_io(&s->mem_ports, &ehci_mmio_port_ops, s, |
2753 |
"ports", PORTSC_END - PORTSC_BEGIN);
|
2754 |
|
2755 |
memory_region_add_subregion(&s->mem, s->capsbase, &s->mem_caps); |
2756 |
memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg); |
2757 |
memory_region_add_subregion(&s->mem, s->opregbase + PORTSC_BEGIN, |
2758 |
&s->mem_ports); |
2759 |
} |
2760 |
|
2761 |
static int usb_ehci_pci_initfn(PCIDevice *dev) |
2762 |
{ |
2763 |
EHCIPCIState *i = DO_UPCAST(EHCIPCIState, pcidev, dev); |
2764 |
EHCIState *s = &i->ehci; |
2765 |
uint8_t *pci_conf = dev->config; |
2766 |
|
2767 |
pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
|
2768 |
|
2769 |
/* capabilities pointer */
|
2770 |
pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
|
2771 |
/* pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); */
|
2772 |
|
2773 |
pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ |
2774 |
pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
|
2775 |
pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
|
2776 |
|
2777 |
/* pci_conf[0x50] = 0x01; *//* power management caps */ |
2778 |
|
2779 |
pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); /* release # (2.1.4) */
|
2780 |
pci_set_byte(&pci_conf[0x61], 0x20); /* frame length adjustment (2.1.5) */ |
2781 |
pci_set_word(&pci_conf[0x62], 0x00); /* port wake up capability (2.1.6) */ |
2782 |
|
2783 |
pci_conf[0x64] = 0x00; |
2784 |
pci_conf[0x65] = 0x00; |
2785 |
pci_conf[0x66] = 0x00; |
2786 |
pci_conf[0x67] = 0x00; |
2787 |
pci_conf[0x68] = 0x01; |
2788 |
pci_conf[0x69] = 0x00; |
2789 |
pci_conf[0x6a] = 0x00; |
2790 |
pci_conf[0x6b] = 0x00; /* USBLEGSUP */ |
2791 |
pci_conf[0x6c] = 0x00; |
2792 |
pci_conf[0x6d] = 0x00; |
2793 |
pci_conf[0x6e] = 0x00; |
2794 |
pci_conf[0x6f] = 0xc0; /* USBLEFCTLSTS */ |
2795 |
|
2796 |
s->caps[0x09] = 0x68; /* EECP */ |
2797 |
|
2798 |
s->irq = dev->irq[3];
|
2799 |
s->dma = pci_dma_context(dev); |
2800 |
|
2801 |
s->capsbase = 0x00;
|
2802 |
s->opregbase = 0x20;
|
2803 |
|
2804 |
usb_ehci_initfn(s, DEVICE(dev)); |
2805 |
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
|
2806 |
|
2807 |
return 0; |
2808 |
} |
2809 |
|
2810 |
static void ehci_register_types(void) |
2811 |
{ |
2812 |
type_register_static(&ehci_info); |
2813 |
type_register_static(&ich9_ehci_info); |
2814 |
} |
2815 |
|
2816 |
type_init(ehci_register_types) |
2817 |
|
2818 |
/*
|
2819 |
* vim: expandtab ts=4
|
2820 |
*/
|