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1 | 16b29ae1 | aliguori | /*
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2 | 16b29ae1 | aliguori | * High Precisition Event Timer emulation
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3 | 16b29ae1 | aliguori | *
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4 | 16b29ae1 | aliguori | * Copyright (c) 2007 Alexander Graf
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5 | 16b29ae1 | aliguori | * Copyright (c) 2008 IBM Corporation
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6 | 16b29ae1 | aliguori | *
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7 | 16b29ae1 | aliguori | * Authors: Beth Kon <bkon@us.ibm.com>
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8 | 16b29ae1 | aliguori | *
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9 | 16b29ae1 | aliguori | * This library is free software; you can redistribute it and/or
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10 | 16b29ae1 | aliguori | * modify it under the terms of the GNU Lesser General Public
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11 | 16b29ae1 | aliguori | * License as published by the Free Software Foundation; either
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12 | 16b29ae1 | aliguori | * version 2 of the License, or (at your option) any later version.
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13 | 16b29ae1 | aliguori | *
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14 | 16b29ae1 | aliguori | * This library is distributed in the hope that it will be useful,
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15 | 16b29ae1 | aliguori | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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16 | 16b29ae1 | aliguori | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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17 | 16b29ae1 | aliguori | * Lesser General Public License for more details.
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18 | 16b29ae1 | aliguori | *
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19 | 16b29ae1 | aliguori | * You should have received a copy of the GNU Lesser General Public
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20 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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21 | 16b29ae1 | aliguori | *
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22 | 16b29ae1 | aliguori | * *****************************************************************
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23 | 16b29ae1 | aliguori | *
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24 | 16b29ae1 | aliguori | * This driver attempts to emulate an HPET device in software.
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25 | 16b29ae1 | aliguori | */
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26 | 16b29ae1 | aliguori | |
27 | 16b29ae1 | aliguori | #include "hw.h" |
28 | bf4f74c0 | aurel32 | #include "pc.h" |
29 | 16b29ae1 | aliguori | #include "console.h" |
30 | 16b29ae1 | aliguori | #include "qemu-timer.h" |
31 | 16b29ae1 | aliguori | #include "hpet_emul.h" |
32 | 16b29ae1 | aliguori | |
33 | 16b29ae1 | aliguori | //#define HPET_DEBUG
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34 | 16b29ae1 | aliguori | #ifdef HPET_DEBUG
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35 | 16b29ae1 | aliguori | #define dprintf printf
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36 | 16b29ae1 | aliguori | #else
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37 | 16b29ae1 | aliguori | #define dprintf(...)
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38 | 16b29ae1 | aliguori | #endif
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39 | 16b29ae1 | aliguori | |
40 | 16b29ae1 | aliguori | static HPETState *hpet_statep;
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41 | 16b29ae1 | aliguori | |
42 | 16b29ae1 | aliguori | uint32_t hpet_in_legacy_mode(void)
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43 | 16b29ae1 | aliguori | { |
44 | 16b29ae1 | aliguori | if (hpet_statep)
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45 | 16b29ae1 | aliguori | return hpet_statep->config & HPET_CFG_LEGACY;
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46 | 16b29ae1 | aliguori | else
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47 | 16b29ae1 | aliguori | return 0; |
48 | 16b29ae1 | aliguori | } |
49 | 16b29ae1 | aliguori | |
50 | c50c2d68 | aurel32 | static uint32_t timer_int_route(struct HPETTimer *timer) |
51 | 16b29ae1 | aliguori | { |
52 | 16b29ae1 | aliguori | uint32_t route; |
53 | 16b29ae1 | aliguori | route = (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT; |
54 | 16b29ae1 | aliguori | return route;
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55 | 16b29ae1 | aliguori | } |
56 | 16b29ae1 | aliguori | |
57 | 16b29ae1 | aliguori | static uint32_t hpet_enabled(void) |
58 | 16b29ae1 | aliguori | { |
59 | 16b29ae1 | aliguori | return hpet_statep->config & HPET_CFG_ENABLE;
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60 | 16b29ae1 | aliguori | } |
61 | 16b29ae1 | aliguori | |
62 | 16b29ae1 | aliguori | static uint32_t timer_is_periodic(HPETTimer *t)
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63 | 16b29ae1 | aliguori | { |
64 | 16b29ae1 | aliguori | return t->config & HPET_TN_PERIODIC;
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65 | 16b29ae1 | aliguori | } |
66 | 16b29ae1 | aliguori | |
67 | 16b29ae1 | aliguori | static uint32_t timer_enabled(HPETTimer *t)
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68 | 16b29ae1 | aliguori | { |
69 | 16b29ae1 | aliguori | return t->config & HPET_TN_ENABLE;
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70 | 16b29ae1 | aliguori | } |
71 | 16b29ae1 | aliguori | |
72 | 16b29ae1 | aliguori | static uint32_t hpet_time_after(uint64_t a, uint64_t b)
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73 | 16b29ae1 | aliguori | { |
74 | 16b29ae1 | aliguori | return ((int32_t)(b) - (int32_t)(a) < 0); |
75 | 16b29ae1 | aliguori | } |
76 | 16b29ae1 | aliguori | |
77 | 16b29ae1 | aliguori | static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
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78 | 16b29ae1 | aliguori | { |
79 | 16b29ae1 | aliguori | return ((int64_t)(b) - (int64_t)(a) < 0); |
80 | 16b29ae1 | aliguori | } |
81 | 16b29ae1 | aliguori | |
82 | c50c2d68 | aurel32 | static uint64_t ticks_to_ns(uint64_t value)
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83 | 16b29ae1 | aliguori | { |
84 | 16b29ae1 | aliguori | return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
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85 | 16b29ae1 | aliguori | } |
86 | 16b29ae1 | aliguori | |
87 | c50c2d68 | aurel32 | static uint64_t ns_to_ticks(uint64_t value)
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88 | 16b29ae1 | aliguori | { |
89 | 16b29ae1 | aliguori | return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
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90 | 16b29ae1 | aliguori | } |
91 | 16b29ae1 | aliguori | |
92 | 16b29ae1 | aliguori | static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
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93 | 16b29ae1 | aliguori | { |
94 | 16b29ae1 | aliguori | new &= mask; |
95 | 16b29ae1 | aliguori | new |= old & ~mask; |
96 | 16b29ae1 | aliguori | return new;
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97 | 16b29ae1 | aliguori | } |
98 | 16b29ae1 | aliguori | |
99 | 16b29ae1 | aliguori | static int activating_bit(uint64_t old, uint64_t new, uint64_t mask) |
100 | 16b29ae1 | aliguori | { |
101 | c50c2d68 | aurel32 | return (!(old & mask) && (new & mask));
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102 | 16b29ae1 | aliguori | } |
103 | 16b29ae1 | aliguori | |
104 | 16b29ae1 | aliguori | static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask) |
105 | 16b29ae1 | aliguori | { |
106 | c50c2d68 | aurel32 | return ((old & mask) && !(new & mask));
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107 | 16b29ae1 | aliguori | } |
108 | 16b29ae1 | aliguori | |
109 | c50c2d68 | aurel32 | static uint64_t hpet_get_ticks(void) |
110 | 16b29ae1 | aliguori | { |
111 | 16b29ae1 | aliguori | uint64_t ticks; |
112 | 16b29ae1 | aliguori | ticks = ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset); |
113 | 16b29ae1 | aliguori | return ticks;
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114 | 16b29ae1 | aliguori | } |
115 | 16b29ae1 | aliguori | |
116 | c50c2d68 | aurel32 | /*
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117 | c50c2d68 | aurel32 | * calculate diff between comparator value and current ticks
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118 | 16b29ae1 | aliguori | */
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119 | 16b29ae1 | aliguori | static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current) |
120 | 16b29ae1 | aliguori | { |
121 | c50c2d68 | aurel32 | |
122 | 16b29ae1 | aliguori | if (t->config & HPET_TN_32BIT) {
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123 | 16b29ae1 | aliguori | uint32_t diff, cmp; |
124 | 16b29ae1 | aliguori | cmp = (uint32_t)t->cmp; |
125 | 16b29ae1 | aliguori | diff = cmp - (uint32_t)current; |
126 | 16b29ae1 | aliguori | diff = (int32_t)diff > 0 ? diff : (uint32_t)0; |
127 | 16b29ae1 | aliguori | return (uint64_t)diff;
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128 | 16b29ae1 | aliguori | } else {
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129 | 16b29ae1 | aliguori | uint64_t diff, cmp; |
130 | 16b29ae1 | aliguori | cmp = t->cmp; |
131 | 16b29ae1 | aliguori | diff = cmp - current; |
132 | 16b29ae1 | aliguori | diff = (int64_t)diff > 0 ? diff : (uint64_t)0; |
133 | 16b29ae1 | aliguori | return diff;
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134 | 16b29ae1 | aliguori | } |
135 | 16b29ae1 | aliguori | } |
136 | 16b29ae1 | aliguori | |
137 | 16b29ae1 | aliguori | static void update_irq(struct HPETTimer *timer) |
138 | 16b29ae1 | aliguori | { |
139 | 16b29ae1 | aliguori | qemu_irq irq; |
140 | 16b29ae1 | aliguori | int route;
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141 | 16b29ae1 | aliguori | |
142 | 16b29ae1 | aliguori | if (timer->tn <= 1 && hpet_in_legacy_mode()) { |
143 | 16b29ae1 | aliguori | /* if LegacyReplacementRoute bit is set, HPET specification requires
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144 | 16b29ae1 | aliguori | * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
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145 | c50c2d68 | aurel32 | * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
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146 | 16b29ae1 | aliguori | */
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147 | 16b29ae1 | aliguori | if (timer->tn == 0) { |
148 | 16b29ae1 | aliguori | irq=timer->state->irqs[0];
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149 | 16b29ae1 | aliguori | } else
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150 | 16b29ae1 | aliguori | irq=timer->state->irqs[8];
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151 | 16b29ae1 | aliguori | } else {
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152 | 16b29ae1 | aliguori | route=timer_int_route(timer); |
153 | 16b29ae1 | aliguori | irq=timer->state->irqs[route]; |
154 | 16b29ae1 | aliguori | } |
155 | 16b29ae1 | aliguori | if (timer_enabled(timer) && hpet_enabled()) {
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156 | 16b29ae1 | aliguori | qemu_irq_pulse(irq); |
157 | 16b29ae1 | aliguori | } |
158 | 16b29ae1 | aliguori | } |
159 | 16b29ae1 | aliguori | |
160 | d4bfa4d7 | Juan Quintela | static void hpet_pre_save(void *opaque) |
161 | 16b29ae1 | aliguori | { |
162 | d4bfa4d7 | Juan Quintela | HPETState *s = opaque; |
163 | 16b29ae1 | aliguori | /* save current counter value */
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164 | c50c2d68 | aurel32 | s->hpet_counter = hpet_get_ticks(); |
165 | 16b29ae1 | aliguori | } |
166 | 16b29ae1 | aliguori | |
167 | e59fb374 | Juan Quintela | static int hpet_post_load(void *opaque, int version_id) |
168 | 16b29ae1 | aliguori | { |
169 | 16b29ae1 | aliguori | HPETState *s = opaque; |
170 | c50c2d68 | aurel32 | |
171 | 16b29ae1 | aliguori | /* Recalculate the offset between the main counter and guest time */
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172 | 16b29ae1 | aliguori | s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock); |
173 | 16b29ae1 | aliguori | return 0; |
174 | 16b29ae1 | aliguori | } |
175 | 16b29ae1 | aliguori | |
176 | e6cb4d45 | Juan Quintela | static const VMStateDescription vmstate_hpet_timer = { |
177 | e6cb4d45 | Juan Quintela | .name = "hpet_timer",
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178 | e6cb4d45 | Juan Quintela | .version_id = 1,
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179 | e6cb4d45 | Juan Quintela | .minimum_version_id = 1,
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180 | e6cb4d45 | Juan Quintela | .minimum_version_id_old = 1,
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181 | e6cb4d45 | Juan Quintela | .fields = (VMStateField []) { |
182 | e6cb4d45 | Juan Quintela | VMSTATE_UINT8(tn, HPETTimer), |
183 | e6cb4d45 | Juan Quintela | VMSTATE_UINT64(config, HPETTimer), |
184 | e6cb4d45 | Juan Quintela | VMSTATE_UINT64(cmp, HPETTimer), |
185 | e6cb4d45 | Juan Quintela | VMSTATE_UINT64(fsb, HPETTimer), |
186 | e6cb4d45 | Juan Quintela | VMSTATE_UINT64(period, HPETTimer), |
187 | e6cb4d45 | Juan Quintela | VMSTATE_UINT8(wrap_flag, HPETTimer), |
188 | e6cb4d45 | Juan Quintela | VMSTATE_TIMER(qemu_timer, HPETTimer), |
189 | e6cb4d45 | Juan Quintela | VMSTATE_END_OF_LIST() |
190 | e6cb4d45 | Juan Quintela | } |
191 | e6cb4d45 | Juan Quintela | }; |
192 | e6cb4d45 | Juan Quintela | |
193 | e6cb4d45 | Juan Quintela | static const VMStateDescription vmstate_hpet = { |
194 | e6cb4d45 | Juan Quintela | .name = "hpet",
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195 | e6cb4d45 | Juan Quintela | .version_id = 1,
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196 | e6cb4d45 | Juan Quintela | .minimum_version_id = 1,
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197 | e6cb4d45 | Juan Quintela | .minimum_version_id_old = 1,
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198 | e6cb4d45 | Juan Quintela | .pre_save = hpet_pre_save, |
199 | e6cb4d45 | Juan Quintela | .post_load = hpet_post_load, |
200 | e6cb4d45 | Juan Quintela | .fields = (VMStateField []) { |
201 | e6cb4d45 | Juan Quintela | VMSTATE_UINT64(config, HPETState), |
202 | e6cb4d45 | Juan Quintela | VMSTATE_UINT64(isr, HPETState), |
203 | e6cb4d45 | Juan Quintela | VMSTATE_UINT64(hpet_counter, HPETState), |
204 | e6cb4d45 | Juan Quintela | VMSTATE_STRUCT_ARRAY(timer, HPETState, HPET_NUM_TIMERS, 0,
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205 | e6cb4d45 | Juan Quintela | vmstate_hpet_timer, HPETTimer), |
206 | e6cb4d45 | Juan Quintela | VMSTATE_END_OF_LIST() |
207 | e6cb4d45 | Juan Quintela | } |
208 | e6cb4d45 | Juan Quintela | }; |
209 | e6cb4d45 | Juan Quintela | |
210 | c50c2d68 | aurel32 | /*
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211 | 16b29ae1 | aliguori | * timer expiration callback
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212 | 16b29ae1 | aliguori | */
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213 | 16b29ae1 | aliguori | static void hpet_timer(void *opaque) |
214 | 16b29ae1 | aliguori | { |
215 | 16b29ae1 | aliguori | HPETTimer *t = (HPETTimer*)opaque; |
216 | 16b29ae1 | aliguori | uint64_t diff; |
217 | 16b29ae1 | aliguori | |
218 | 16b29ae1 | aliguori | uint64_t period = t->period; |
219 | 16b29ae1 | aliguori | uint64_t cur_tick = hpet_get_ticks(); |
220 | 16b29ae1 | aliguori | |
221 | 16b29ae1 | aliguori | if (timer_is_periodic(t) && period != 0) { |
222 | 16b29ae1 | aliguori | if (t->config & HPET_TN_32BIT) {
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223 | 16b29ae1 | aliguori | while (hpet_time_after(cur_tick, t->cmp))
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224 | 16b29ae1 | aliguori | t->cmp = (uint32_t)(t->cmp + t->period); |
225 | 16b29ae1 | aliguori | } else
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226 | 16b29ae1 | aliguori | while (hpet_time_after64(cur_tick, t->cmp))
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227 | 16b29ae1 | aliguori | t->cmp += period; |
228 | 16b29ae1 | aliguori | |
229 | 16b29ae1 | aliguori | diff = hpet_calculate_diff(t, cur_tick); |
230 | c50c2d68 | aurel32 | qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) |
231 | 16b29ae1 | aliguori | + (int64_t)ticks_to_ns(diff)); |
232 | 16b29ae1 | aliguori | } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { |
233 | 16b29ae1 | aliguori | if (t->wrap_flag) {
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234 | 16b29ae1 | aliguori | diff = hpet_calculate_diff(t, cur_tick); |
235 | c50c2d68 | aurel32 | qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) |
236 | 16b29ae1 | aliguori | + (int64_t)ticks_to_ns(diff)); |
237 | 16b29ae1 | aliguori | t->wrap_flag = 0;
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238 | 16b29ae1 | aliguori | } |
239 | 16b29ae1 | aliguori | } |
240 | 16b29ae1 | aliguori | update_irq(t); |
241 | 16b29ae1 | aliguori | } |
242 | 16b29ae1 | aliguori | |
243 | 16b29ae1 | aliguori | static void hpet_set_timer(HPETTimer *t) |
244 | 16b29ae1 | aliguori | { |
245 | 16b29ae1 | aliguori | uint64_t diff; |
246 | 16b29ae1 | aliguori | uint32_t wrap_diff; /* how many ticks until we wrap? */
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247 | 16b29ae1 | aliguori | uint64_t cur_tick = hpet_get_ticks(); |
248 | c50c2d68 | aurel32 | |
249 | 16b29ae1 | aliguori | /* whenever new timer is being set up, make sure wrap_flag is 0 */
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250 | 16b29ae1 | aliguori | t->wrap_flag = 0;
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251 | 16b29ae1 | aliguori | diff = hpet_calculate_diff(t, cur_tick); |
252 | 16b29ae1 | aliguori | |
253 | c50c2d68 | aurel32 | /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
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254 | 16b29ae1 | aliguori | * counter wraps in addition to an interrupt with comparator match.
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255 | c50c2d68 | aurel32 | */
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256 | 16b29ae1 | aliguori | if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
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257 | 16b29ae1 | aliguori | wrap_diff = 0xffffffff - (uint32_t)cur_tick;
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258 | 16b29ae1 | aliguori | if (wrap_diff < (uint32_t)diff) {
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259 | 16b29ae1 | aliguori | diff = wrap_diff; |
260 | c50c2d68 | aurel32 | t->wrap_flag = 1;
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261 | 16b29ae1 | aliguori | } |
262 | 16b29ae1 | aliguori | } |
263 | c50c2d68 | aurel32 | qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) |
264 | 16b29ae1 | aliguori | + (int64_t)ticks_to_ns(diff)); |
265 | 16b29ae1 | aliguori | } |
266 | 16b29ae1 | aliguori | |
267 | 16b29ae1 | aliguori | static void hpet_del_timer(HPETTimer *t) |
268 | 16b29ae1 | aliguori | { |
269 | 16b29ae1 | aliguori | qemu_del_timer(t->qemu_timer); |
270 | 16b29ae1 | aliguori | } |
271 | 16b29ae1 | aliguori | |
272 | 16b29ae1 | aliguori | #ifdef HPET_DEBUG
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273 | c227f099 | Anthony Liguori | static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr) |
274 | 16b29ae1 | aliguori | { |
275 | 16b29ae1 | aliguori | printf("qemu: hpet_read b at %" PRIx64 "\n", addr); |
276 | 16b29ae1 | aliguori | return 0; |
277 | 16b29ae1 | aliguori | } |
278 | 16b29ae1 | aliguori | |
279 | c227f099 | Anthony Liguori | static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr) |
280 | 16b29ae1 | aliguori | { |
281 | 16b29ae1 | aliguori | printf("qemu: hpet_read w at %" PRIx64 "\n", addr); |
282 | 16b29ae1 | aliguori | return 0; |
283 | 16b29ae1 | aliguori | } |
284 | 16b29ae1 | aliguori | #endif
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285 | 16b29ae1 | aliguori | |
286 | c227f099 | Anthony Liguori | static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr) |
287 | 16b29ae1 | aliguori | { |
288 | 16b29ae1 | aliguori | HPETState *s = (HPETState *)opaque; |
289 | 16b29ae1 | aliguori | uint64_t cur_tick, index; |
290 | 16b29ae1 | aliguori | |
291 | 16b29ae1 | aliguori | dprintf("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr); |
292 | 16b29ae1 | aliguori | index = addr; |
293 | 16b29ae1 | aliguori | /*address range of all TN regs*/
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294 | 16b29ae1 | aliguori | if (index >= 0x100 && index <= 0x3ff) { |
295 | 16b29ae1 | aliguori | uint8_t timer_id = (addr - 0x100) / 0x20; |
296 | 16b29ae1 | aliguori | if (timer_id > HPET_NUM_TIMERS - 1) { |
297 | 16b29ae1 | aliguori | printf("qemu: timer id out of range\n");
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298 | 16b29ae1 | aliguori | return 0; |
299 | 16b29ae1 | aliguori | } |
300 | 16b29ae1 | aliguori | HPETTimer *timer = &s->timer[timer_id]; |
301 | 16b29ae1 | aliguori | |
302 | 16b29ae1 | aliguori | switch ((addr - 0x100) % 0x20) { |
303 | 16b29ae1 | aliguori | case HPET_TN_CFG:
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304 | 16b29ae1 | aliguori | return timer->config;
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305 | 16b29ae1 | aliguori | case HPET_TN_CFG + 4: // Interrupt capabilities |
306 | 16b29ae1 | aliguori | return timer->config >> 32; |
307 | 16b29ae1 | aliguori | case HPET_TN_CMP: // comparator register |
308 | 16b29ae1 | aliguori | return timer->cmp;
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309 | 16b29ae1 | aliguori | case HPET_TN_CMP + 4: |
310 | 16b29ae1 | aliguori | return timer->cmp >> 32; |
311 | 16b29ae1 | aliguori | case HPET_TN_ROUTE:
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312 | 16b29ae1 | aliguori | return timer->fsb >> 32; |
313 | 16b29ae1 | aliguori | default:
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314 | 16b29ae1 | aliguori | dprintf("qemu: invalid hpet_ram_readl\n");
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315 | 16b29ae1 | aliguori | break;
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316 | 16b29ae1 | aliguori | } |
317 | 16b29ae1 | aliguori | } else {
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318 | 16b29ae1 | aliguori | switch (index) {
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319 | 16b29ae1 | aliguori | case HPET_ID:
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320 | 16b29ae1 | aliguori | return s->capability;
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321 | 16b29ae1 | aliguori | case HPET_PERIOD:
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322 | c50c2d68 | aurel32 | return s->capability >> 32; |
323 | 16b29ae1 | aliguori | case HPET_CFG:
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324 | 16b29ae1 | aliguori | return s->config;
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325 | 16b29ae1 | aliguori | case HPET_CFG + 4: |
326 | 16b29ae1 | aliguori | dprintf("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
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327 | 16b29ae1 | aliguori | return 0; |
328 | c50c2d68 | aurel32 | case HPET_COUNTER:
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329 | 16b29ae1 | aliguori | if (hpet_enabled())
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330 | 16b29ae1 | aliguori | cur_tick = hpet_get_ticks(); |
331 | c50c2d68 | aurel32 | else
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332 | 16b29ae1 | aliguori | cur_tick = s->hpet_counter; |
333 | 16b29ae1 | aliguori | dprintf("qemu: reading counter = %" PRIx64 "\n", cur_tick); |
334 | 16b29ae1 | aliguori | return cur_tick;
|
335 | 16b29ae1 | aliguori | case HPET_COUNTER + 4: |
336 | 16b29ae1 | aliguori | if (hpet_enabled())
|
337 | 16b29ae1 | aliguori | cur_tick = hpet_get_ticks(); |
338 | c50c2d68 | aurel32 | else
|
339 | 16b29ae1 | aliguori | cur_tick = s->hpet_counter; |
340 | 16b29ae1 | aliguori | dprintf("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick); |
341 | 16b29ae1 | aliguori | return cur_tick >> 32; |
342 | 16b29ae1 | aliguori | case HPET_STATUS:
|
343 | 16b29ae1 | aliguori | return s->isr;
|
344 | 16b29ae1 | aliguori | default:
|
345 | 16b29ae1 | aliguori | dprintf("qemu: invalid hpet_ram_readl\n");
|
346 | 16b29ae1 | aliguori | break;
|
347 | 16b29ae1 | aliguori | } |
348 | 16b29ae1 | aliguori | } |
349 | 16b29ae1 | aliguori | return 0; |
350 | 16b29ae1 | aliguori | } |
351 | 16b29ae1 | aliguori | |
352 | 16b29ae1 | aliguori | #ifdef HPET_DEBUG
|
353 | c227f099 | Anthony Liguori | static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr, |
354 | 16b29ae1 | aliguori | uint32_t value) |
355 | 16b29ae1 | aliguori | { |
356 | c50c2d68 | aurel32 | printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n", |
357 | 16b29ae1 | aliguori | addr, value); |
358 | 16b29ae1 | aliguori | } |
359 | 16b29ae1 | aliguori | |
360 | c227f099 | Anthony Liguori | static void hpet_ram_writew(void *opaque, target_phys_addr_t addr, |
361 | 16b29ae1 | aliguori | uint32_t value) |
362 | 16b29ae1 | aliguori | { |
363 | c50c2d68 | aurel32 | printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n", |
364 | 16b29ae1 | aliguori | addr, value); |
365 | 16b29ae1 | aliguori | } |
366 | 16b29ae1 | aliguori | #endif
|
367 | 16b29ae1 | aliguori | |
368 | c227f099 | Anthony Liguori | static void hpet_ram_writel(void *opaque, target_phys_addr_t addr, |
369 | 16b29ae1 | aliguori | uint32_t value) |
370 | 16b29ae1 | aliguori | { |
371 | 16b29ae1 | aliguori | int i;
|
372 | 16b29ae1 | aliguori | HPETState *s = (HPETState *)opaque; |
373 | ce536cfd | Beth Kon | uint64_t old_val, new_val, val, index; |
374 | 16b29ae1 | aliguori | |
375 | 16b29ae1 | aliguori | dprintf("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value); |
376 | 16b29ae1 | aliguori | index = addr; |
377 | 16b29ae1 | aliguori | old_val = hpet_ram_readl(opaque, addr); |
378 | 16b29ae1 | aliguori | new_val = value; |
379 | 16b29ae1 | aliguori | |
380 | 16b29ae1 | aliguori | /*address range of all TN regs*/
|
381 | 16b29ae1 | aliguori | if (index >= 0x100 && index <= 0x3ff) { |
382 | 16b29ae1 | aliguori | uint8_t timer_id = (addr - 0x100) / 0x20; |
383 | 16b29ae1 | aliguori | dprintf("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
|
384 | 16b29ae1 | aliguori | HPETTimer *timer = &s->timer[timer_id]; |
385 | c50c2d68 | aurel32 | |
386 | 16b29ae1 | aliguori | switch ((addr - 0x100) % 0x20) { |
387 | 16b29ae1 | aliguori | case HPET_TN_CFG:
|
388 | 16b29ae1 | aliguori | dprintf("qemu: hpet_ram_writel HPET_TN_CFG\n");
|
389 | ce536cfd | Beth Kon | val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); |
390 | ce536cfd | Beth Kon | timer->config = (timer->config & 0xffffffff00000000ULL) | val;
|
391 | 16b29ae1 | aliguori | if (new_val & HPET_TN_32BIT) {
|
392 | 16b29ae1 | aliguori | timer->cmp = (uint32_t)timer->cmp; |
393 | 16b29ae1 | aliguori | timer->period = (uint32_t)timer->period; |
394 | 16b29ae1 | aliguori | } |
395 | 16b29ae1 | aliguori | if (new_val & HPET_TIMER_TYPE_LEVEL) {
|
396 | 16b29ae1 | aliguori | printf("qemu: level-triggered hpet not supported\n");
|
397 | 16b29ae1 | aliguori | exit (-1);
|
398 | 16b29ae1 | aliguori | } |
399 | 16b29ae1 | aliguori | |
400 | 16b29ae1 | aliguori | break;
|
401 | 16b29ae1 | aliguori | case HPET_TN_CFG + 4: // Interrupt capabilities |
402 | 16b29ae1 | aliguori | dprintf("qemu: invalid HPET_TN_CFG+4 write\n");
|
403 | 16b29ae1 | aliguori | break;
|
404 | 16b29ae1 | aliguori | case HPET_TN_CMP: // comparator register |
405 | 16b29ae1 | aliguori | dprintf("qemu: hpet_ram_writel HPET_TN_CMP \n");
|
406 | 16b29ae1 | aliguori | if (timer->config & HPET_TN_32BIT)
|
407 | 16b29ae1 | aliguori | new_val = (uint32_t)new_val; |
408 | 16b29ae1 | aliguori | if (!timer_is_periodic(timer) ||
|
409 | 16b29ae1 | aliguori | (timer->config & HPET_TN_SETVAL)) |
410 | 16b29ae1 | aliguori | timer->cmp = (timer->cmp & 0xffffffff00000000ULL)
|
411 | 16b29ae1 | aliguori | | new_val; |
412 | 37873241 | aliguori | if (timer_is_periodic(timer)) {
|
413 | 16b29ae1 | aliguori | /*
|
414 | 16b29ae1 | aliguori | * FIXME: Clamp period to reasonable min value?
|
415 | 16b29ae1 | aliguori | * Clamp period to reasonable max value
|
416 | 16b29ae1 | aliguori | */
|
417 | 16b29ae1 | aliguori | new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; |
418 | 16b29ae1 | aliguori | timer->period = (timer->period & 0xffffffff00000000ULL)
|
419 | 16b29ae1 | aliguori | | new_val; |
420 | 16b29ae1 | aliguori | } |
421 | 16b29ae1 | aliguori | timer->config &= ~HPET_TN_SETVAL; |
422 | 16b29ae1 | aliguori | if (hpet_enabled())
|
423 | 16b29ae1 | aliguori | hpet_set_timer(timer); |
424 | 16b29ae1 | aliguori | break;
|
425 | 16b29ae1 | aliguori | case HPET_TN_CMP + 4: // comparator register high order |
426 | 16b29ae1 | aliguori | dprintf("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
|
427 | 16b29ae1 | aliguori | if (!timer_is_periodic(timer) ||
|
428 | 16b29ae1 | aliguori | (timer->config & HPET_TN_SETVAL)) |
429 | 16b29ae1 | aliguori | timer->cmp = (timer->cmp & 0xffffffffULL)
|
430 | 16b29ae1 | aliguori | | new_val << 32;
|
431 | 16b29ae1 | aliguori | else {
|
432 | 16b29ae1 | aliguori | /*
|
433 | 16b29ae1 | aliguori | * FIXME: Clamp period to reasonable min value?
|
434 | 16b29ae1 | aliguori | * Clamp period to reasonable max value
|
435 | 16b29ae1 | aliguori | */
|
436 | c50c2d68 | aurel32 | new_val &= (timer->config |
437 | 16b29ae1 | aliguori | & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; |
438 | 16b29ae1 | aliguori | timer->period = (timer->period & 0xffffffffULL)
|
439 | 16b29ae1 | aliguori | | new_val << 32;
|
440 | 16b29ae1 | aliguori | } |
441 | 16b29ae1 | aliguori | timer->config &= ~HPET_TN_SETVAL; |
442 | 16b29ae1 | aliguori | if (hpet_enabled())
|
443 | 16b29ae1 | aliguori | hpet_set_timer(timer); |
444 | 16b29ae1 | aliguori | break;
|
445 | 16b29ae1 | aliguori | case HPET_TN_ROUTE + 4: |
446 | 16b29ae1 | aliguori | dprintf("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
|
447 | 16b29ae1 | aliguori | break;
|
448 | 16b29ae1 | aliguori | default:
|
449 | 16b29ae1 | aliguori | dprintf("qemu: invalid hpet_ram_writel\n");
|
450 | 16b29ae1 | aliguori | break;
|
451 | 16b29ae1 | aliguori | } |
452 | 16b29ae1 | aliguori | return;
|
453 | 16b29ae1 | aliguori | } else {
|
454 | 16b29ae1 | aliguori | switch (index) {
|
455 | 16b29ae1 | aliguori | case HPET_ID:
|
456 | 16b29ae1 | aliguori | return;
|
457 | 16b29ae1 | aliguori | case HPET_CFG:
|
458 | ce536cfd | Beth Kon | val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); |
459 | ce536cfd | Beth Kon | s->config = (s->config & 0xffffffff00000000ULL) | val;
|
460 | 16b29ae1 | aliguori | if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
|
461 | 16b29ae1 | aliguori | /* Enable main counter and interrupt generation. */
|
462 | 16b29ae1 | aliguori | s->hpet_offset = ticks_to_ns(s->hpet_counter) |
463 | 16b29ae1 | aliguori | - qemu_get_clock(vm_clock); |
464 | 16b29ae1 | aliguori | for (i = 0; i < HPET_NUM_TIMERS; i++) |
465 | 16b29ae1 | aliguori | if ((&s->timer[i])->cmp != ~0ULL) |
466 | 16b29ae1 | aliguori | hpet_set_timer(&s->timer[i]); |
467 | 16b29ae1 | aliguori | } |
468 | 16b29ae1 | aliguori | else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) { |
469 | 16b29ae1 | aliguori | /* Halt main counter and disable interrupt generation. */
|
470 | c50c2d68 | aurel32 | s->hpet_counter = hpet_get_ticks(); |
471 | 16b29ae1 | aliguori | for (i = 0; i < HPET_NUM_TIMERS; i++) |
472 | 16b29ae1 | aliguori | hpet_del_timer(&s->timer[i]); |
473 | 16b29ae1 | aliguori | } |
474 | 16b29ae1 | aliguori | /* i8254 and RTC are disabled when HPET is in legacy mode */
|
475 | 16b29ae1 | aliguori | if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
|
476 | 16b29ae1 | aliguori | hpet_pit_disable(); |
477 | 16b29ae1 | aliguori | } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) { |
478 | 16b29ae1 | aliguori | hpet_pit_enable(); |
479 | 16b29ae1 | aliguori | } |
480 | 16b29ae1 | aliguori | break;
|
481 | c50c2d68 | aurel32 | case HPET_CFG + 4: |
482 | 16b29ae1 | aliguori | dprintf("qemu: invalid HPET_CFG+4 write \n");
|
483 | 16b29ae1 | aliguori | break;
|
484 | 16b29ae1 | aliguori | case HPET_STATUS:
|
485 | 16b29ae1 | aliguori | /* FIXME: need to handle level-triggered interrupts */
|
486 | 16b29ae1 | aliguori | break;
|
487 | 16b29ae1 | aliguori | case HPET_COUNTER:
|
488 | c50c2d68 | aurel32 | if (hpet_enabled())
|
489 | c50c2d68 | aurel32 | printf("qemu: Writing counter while HPET enabled!\n");
|
490 | c50c2d68 | aurel32 | s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL)
|
491 | 16b29ae1 | aliguori | | value; |
492 | 16b29ae1 | aliguori | dprintf("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n", |
493 | 16b29ae1 | aliguori | value, s->hpet_counter); |
494 | 16b29ae1 | aliguori | break;
|
495 | 16b29ae1 | aliguori | case HPET_COUNTER + 4: |
496 | c50c2d68 | aurel32 | if (hpet_enabled())
|
497 | c50c2d68 | aurel32 | printf("qemu: Writing counter while HPET enabled!\n");
|
498 | c50c2d68 | aurel32 | s->hpet_counter = (s->hpet_counter & 0xffffffffULL)
|
499 | 16b29ae1 | aliguori | | (((uint64_t)value) << 32);
|
500 | 16b29ae1 | aliguori | dprintf("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n", |
501 | 16b29ae1 | aliguori | value, s->hpet_counter); |
502 | 16b29ae1 | aliguori | break;
|
503 | 16b29ae1 | aliguori | default:
|
504 | 16b29ae1 | aliguori | dprintf("qemu: invalid hpet_ram_writel\n");
|
505 | 16b29ae1 | aliguori | break;
|
506 | 16b29ae1 | aliguori | } |
507 | 16b29ae1 | aliguori | } |
508 | 16b29ae1 | aliguori | } |
509 | 16b29ae1 | aliguori | |
510 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const hpet_ram_read[] = { |
511 | 16b29ae1 | aliguori | #ifdef HPET_DEBUG
|
512 | 16b29ae1 | aliguori | hpet_ram_readb, |
513 | 16b29ae1 | aliguori | hpet_ram_readw, |
514 | 16b29ae1 | aliguori | #else
|
515 | 16b29ae1 | aliguori | NULL,
|
516 | 16b29ae1 | aliguori | NULL,
|
517 | 16b29ae1 | aliguori | #endif
|
518 | 16b29ae1 | aliguori | hpet_ram_readl, |
519 | 16b29ae1 | aliguori | }; |
520 | 16b29ae1 | aliguori | |
521 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const hpet_ram_write[] = { |
522 | 16b29ae1 | aliguori | #ifdef HPET_DEBUG
|
523 | 16b29ae1 | aliguori | hpet_ram_writeb, |
524 | 16b29ae1 | aliguori | hpet_ram_writew, |
525 | 16b29ae1 | aliguori | #else
|
526 | 16b29ae1 | aliguori | NULL,
|
527 | 16b29ae1 | aliguori | NULL,
|
528 | 16b29ae1 | aliguori | #endif
|
529 | 16b29ae1 | aliguori | hpet_ram_writel, |
530 | 16b29ae1 | aliguori | }; |
531 | 16b29ae1 | aliguori | |
532 | 16b29ae1 | aliguori | static void hpet_reset(void *opaque) { |
533 | 16b29ae1 | aliguori | HPETState *s = opaque; |
534 | 16b29ae1 | aliguori | int i;
|
535 | 16b29ae1 | aliguori | static int count = 0; |
536 | 16b29ae1 | aliguori | |
537 | 16b29ae1 | aliguori | for (i=0; i<HPET_NUM_TIMERS; i++) { |
538 | 16b29ae1 | aliguori | HPETTimer *timer = &s->timer[i]; |
539 | 16b29ae1 | aliguori | hpet_del_timer(timer); |
540 | 16b29ae1 | aliguori | timer->tn = i; |
541 | 16b29ae1 | aliguori | timer->cmp = ~0ULL;
|
542 | 16b29ae1 | aliguori | timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP; |
543 | ce536cfd | Beth Kon | /* advertise availability of ioapic inti2 */
|
544 | ce536cfd | Beth Kon | timer->config |= 0x00000004ULL << 32; |
545 | 16b29ae1 | aliguori | timer->state = s; |
546 | 16b29ae1 | aliguori | timer->period = 0ULL;
|
547 | 16b29ae1 | aliguori | timer->wrap_flag = 0;
|
548 | 16b29ae1 | aliguori | } |
549 | 16b29ae1 | aliguori | |
550 | 16b29ae1 | aliguori | s->hpet_counter = 0ULL;
|
551 | 16b29ae1 | aliguori | s->hpet_offset = 0ULL;
|
552 | 16b29ae1 | aliguori | /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
|
553 | 16b29ae1 | aliguori | s->capability = 0x8086a201ULL;
|
554 | 16b29ae1 | aliguori | s->capability |= ((HPET_CLK_PERIOD) << 32);
|
555 | 7d93b1fa | Beth Kon | s->config = 0ULL;
|
556 | 16b29ae1 | aliguori | if (count > 0) |
557 | c50c2d68 | aurel32 | /* we don't enable pit when hpet_reset is first called (by hpet_init)
|
558 | 16b29ae1 | aliguori | * because hpet is taking over for pit here. On subsequent invocations,
|
559 | 16b29ae1 | aliguori | * hpet_reset is called due to system reset. At this point control must
|
560 | c50c2d68 | aurel32 | * be returned to pit until SW reenables hpet.
|
561 | 16b29ae1 | aliguori | */
|
562 | 16b29ae1 | aliguori | hpet_pit_enable(); |
563 | 16b29ae1 | aliguori | count = 1;
|
564 | 16b29ae1 | aliguori | } |
565 | 16b29ae1 | aliguori | |
566 | 16b29ae1 | aliguori | |
567 | 16b29ae1 | aliguori | void hpet_init(qemu_irq *irq) {
|
568 | 16b29ae1 | aliguori | int i, iomemtype;
|
569 | 16b29ae1 | aliguori | HPETState *s; |
570 | c50c2d68 | aurel32 | |
571 | 16b29ae1 | aliguori | dprintf ("hpet_init\n");
|
572 | 16b29ae1 | aliguori | |
573 | 16b29ae1 | aliguori | s = qemu_mallocz(sizeof(HPETState));
|
574 | 16b29ae1 | aliguori | hpet_statep = s; |
575 | 16b29ae1 | aliguori | s->irqs = irq; |
576 | 16b29ae1 | aliguori | for (i=0; i<HPET_NUM_TIMERS; i++) { |
577 | 16b29ae1 | aliguori | HPETTimer *timer = &s->timer[i]; |
578 | 16b29ae1 | aliguori | timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer); |
579 | 16b29ae1 | aliguori | } |
580 | 16b29ae1 | aliguori | hpet_reset(s); |
581 | e6cb4d45 | Juan Quintela | vmstate_register(-1, &vmstate_hpet, s);
|
582 | a08d4367 | Jan Kiszka | qemu_register_reset(hpet_reset, s); |
583 | 16b29ae1 | aliguori | /* HPET Area */
|
584 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(hpet_ram_read, |
585 | 16b29ae1 | aliguori | hpet_ram_write, s); |
586 | 16b29ae1 | aliguori | cpu_register_physical_memory(HPET_BASE, 0x400, iomemtype);
|
587 | 16b29ae1 | aliguori | } |