Revision 502a5395
| b/Makefile.target | ||
|---|---|---|
| 307 | 307 |
endif |
| 308 | 308 |
|
| 309 | 309 |
# USB layer |
| 310 |
VL_OBJS+= usb.o usb-hub.o usb-uhci.o usb-linux.o usb-hid.o
|
|
| 310 |
VL_OBJS+= usb.o usb-hub.o usb-linux.o usb-hid.o |
|
| 311 | 311 |
|
| 312 | 312 |
# PCI network cards |
| 313 | 313 |
VL_OBJS+= ne2000.o rtl8139.o |
| ... | ... | |
| 316 | 316 |
# Hardware support |
| 317 | 317 |
VL_OBJS+= ide.o pckbd.o ps2.o vga.o $(SOUND_HW) dma.o $(AUDIODRV) |
| 318 | 318 |
VL_OBJS+= fdc.o mc146818rtc.o serial.o i8259.o i8254.o pcspk.o pc.o |
| 319 |
VL_OBJS+= cirrus_vga.o mixeng.o apic.o parallel.o acpi.o |
|
| 319 |
VL_OBJS+= cirrus_vga.o mixeng.o apic.o parallel.o acpi.o piix_pci.o |
|
| 320 |
VL_OBJS+= usb-uhci.o |
|
| 320 | 321 |
DEFINES += -DHAS_AUDIO |
| 321 | 322 |
endif |
| 322 | 323 |
ifeq ($(TARGET_BASE_ARCH), ppc) |
| 323 | 324 |
VL_OBJS+= ppc.o ide.o pckbd.o ps2.o vga.o $(SOUND_HW) dma.o $(AUDIODRV) |
| 324 | 325 |
VL_OBJS+= mc146818rtc.o serial.o i8259.o i8254.o fdc.o m48t59.o |
| 325 | 326 |
VL_OBJS+= ppc_prep.o ppc_chrp.o cuda.o adb.o openpic.o heathrow_pic.o mixeng.o |
| 327 |
VL_OBJS+= grackle_pci.o prep_pci.o unin_pci.o |
|
| 326 | 328 |
DEFINES += -DHAS_AUDIO |
| 327 | 329 |
endif |
| 328 | 330 |
ifeq ($(TARGET_ARCH), mips) |
| ... | ... | |
| 331 | 333 |
endif |
| 332 | 334 |
ifeq ($(TARGET_BASE_ARCH), sparc) |
| 333 | 335 |
ifeq ($(TARGET_ARCH), sparc64) |
| 334 |
VL_OBJS+= sun4u.o ide.o pckbd.o ps2.o vga.o |
|
| 336 |
VL_OBJS+= sun4u.o ide.o pckbd.o ps2.o vga.o apb_pci.o
|
|
| 335 | 337 |
VL_OBJS+= fdc.o mc146818rtc.o serial.o m48t59.o |
| 336 | 338 |
VL_OBJS+= cirrus_vga.o parallel.o |
| 337 | 339 |
else |
| ... | ... | |
| 342 | 344 |
ifeq ($(TARGET_BASE_ARCH), arm) |
| 343 | 345 |
VL_OBJS+= integratorcp.o versatilepb.o ps2.o smc91c111.o arm_pic.o arm_timer.o |
| 344 | 346 |
VL_OBJS+= arm_boot.o pl011.o pl050.o pl080.o pl110.o pl190.o |
| 347 |
VL_OBJS+= versatile_pci.o |
|
| 345 | 348 |
endif |
| 346 | 349 |
ifeq ($(TARGET_BASE_ARCH), sh4) |
| 347 | 350 |
VL_OBJS+= shix.o sh7750.o sh7750_regnames.o tc58128.o |
| b/hw/acpi.c | ||
|---|---|---|
| 220 | 220 |
|
| 221 | 221 |
/* XXX: we still add it to the PIIX3 and we count on the fact that |
| 222 | 222 |
OSes are smart enough to accept this strange configuration */ |
| 223 |
void piix4_pm_init(PCIBus *bus) |
|
| 223 |
void piix4_pm_init(PCIBus *bus, int devfn)
|
|
| 224 | 224 |
{
|
| 225 | 225 |
PIIX4PMState *s; |
| 226 | 226 |
uint8_t *pci_conf; |
| ... | ... | |
| 228 | 228 |
|
| 229 | 229 |
s = (PIIX4PMState *)pci_register_device(bus, |
| 230 | 230 |
"PM", sizeof(PIIX4PMState), |
| 231 |
((PCIDevice *)piix3_state)->devfn + 3, |
|
| 232 |
NULL, NULL); |
|
| 231 |
devfn, NULL, NULL); |
|
| 233 | 232 |
pci_conf = s->dev.config; |
| 234 | 233 |
pci_conf[0x00] = 0x86; |
| 235 | 234 |
pci_conf[0x01] = 0x80; |
| b/hw/apb_pci.c | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
* QEMU Ultrasparc APB PCI host |
|
| 3 |
* |
|
| 4 |
* Copyright (c) 2006 Fabrice Bellard |
|
| 5 |
* |
|
| 6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
|
| 7 |
* of this software and associated documentation files (the "Software"), to deal |
|
| 8 |
* in the Software without restriction, including without limitation the rights |
|
| 9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
|
| 10 |
* copies of the Software, and to permit persons to whom the Software is |
|
| 11 |
* furnished to do so, subject to the following conditions: |
|
| 12 |
* |
|
| 13 |
* The above copyright notice and this permission notice shall be included in |
|
| 14 |
* all copies or substantial portions of the Software. |
|
| 15 |
* |
|
| 16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
|
| 17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
|
| 18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
|
| 19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
|
| 20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
|
| 21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
|
| 22 |
* THE SOFTWARE. |
|
| 23 |
*/ |
|
| 24 |
#include "vl.h" |
|
| 25 |
typedef target_phys_addr_t pci_addr_t; |
|
| 26 |
#include "pci_host.h" |
|
| 27 |
|
|
| 28 |
typedef PCIHostState APBState; |
|
| 29 |
|
|
| 30 |
static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr, |
|
| 31 |
uint32_t val) |
|
| 32 |
{
|
|
| 33 |
APBState *s = opaque; |
|
| 34 |
int i; |
|
| 35 |
|
|
| 36 |
for (i = 11; i < 32; i++) {
|
|
| 37 |
if ((val & (1 << i)) != 0) |
|
| 38 |
break; |
|
| 39 |
} |
|
| 40 |
s->config_reg = (1 << 16) | (val & 0x7FC) | (i << 11); |
|
| 41 |
} |
|
| 42 |
|
|
| 43 |
static uint32_t pci_apb_config_readl (void *opaque, |
|
| 44 |
target_phys_addr_t addr) |
|
| 45 |
{
|
|
| 46 |
APBState *s = opaque; |
|
| 47 |
uint32_t val; |
|
| 48 |
int devfn; |
|
| 49 |
|
|
| 50 |
devfn = (s->config_reg >> 8) & 0xFF; |
|
| 51 |
val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC); |
|
| 52 |
return val; |
|
| 53 |
} |
|
| 54 |
|
|
| 55 |
static CPUWriteMemoryFunc *pci_apb_config_write[] = {
|
|
| 56 |
&pci_apb_config_writel, |
|
| 57 |
&pci_apb_config_writel, |
|
| 58 |
&pci_apb_config_writel, |
|
| 59 |
}; |
|
| 60 |
|
|
| 61 |
static CPUReadMemoryFunc *pci_apb_config_read[] = {
|
|
| 62 |
&pci_apb_config_readl, |
|
| 63 |
&pci_apb_config_readl, |
|
| 64 |
&pci_apb_config_readl, |
|
| 65 |
}; |
|
| 66 |
|
|
| 67 |
static void apb_config_writel (void *opaque, target_phys_addr_t addr, |
|
| 68 |
uint32_t val) |
|
| 69 |
{
|
|
| 70 |
//PCIBus *s = opaque; |
|
| 71 |
|
|
| 72 |
switch (addr & 0x3f) {
|
|
| 73 |
case 0x00: // Control/Status |
|
| 74 |
case 0x10: // AFSR |
|
| 75 |
case 0x18: // AFAR |
|
| 76 |
case 0x20: // Diagnostic |
|
| 77 |
case 0x28: // Target address space |
|
| 78 |
// XXX |
|
| 79 |
default: |
|
| 80 |
break; |
|
| 81 |
} |
|
| 82 |
} |
|
| 83 |
|
|
| 84 |
static uint32_t apb_config_readl (void *opaque, |
|
| 85 |
target_phys_addr_t addr) |
|
| 86 |
{
|
|
| 87 |
//PCIBus *s = opaque; |
|
| 88 |
uint32_t val; |
|
| 89 |
|
|
| 90 |
switch (addr & 0x3f) {
|
|
| 91 |
case 0x00: // Control/Status |
|
| 92 |
case 0x10: // AFSR |
|
| 93 |
case 0x18: // AFAR |
|
| 94 |
case 0x20: // Diagnostic |
|
| 95 |
case 0x28: // Target address space |
|
| 96 |
// XXX |
|
| 97 |
default: |
|
| 98 |
val = 0; |
|
| 99 |
break; |
|
| 100 |
} |
|
| 101 |
return val; |
|
| 102 |
} |
|
| 103 |
|
|
| 104 |
static CPUWriteMemoryFunc *apb_config_write[] = {
|
|
| 105 |
&apb_config_writel, |
|
| 106 |
&apb_config_writel, |
|
| 107 |
&apb_config_writel, |
|
| 108 |
}; |
|
| 109 |
|
|
| 110 |
static CPUReadMemoryFunc *apb_config_read[] = {
|
|
| 111 |
&apb_config_readl, |
|
| 112 |
&apb_config_readl, |
|
| 113 |
&apb_config_readl, |
|
| 114 |
}; |
|
| 115 |
|
|
| 116 |
static CPUWriteMemoryFunc *pci_apb_write[] = {
|
|
| 117 |
&pci_host_data_writeb, |
|
| 118 |
&pci_host_data_writew, |
|
| 119 |
&pci_host_data_writel, |
|
| 120 |
}; |
|
| 121 |
|
|
| 122 |
static CPUReadMemoryFunc *pci_apb_read[] = {
|
|
| 123 |
&pci_host_data_readb, |
|
| 124 |
&pci_host_data_readw, |
|
| 125 |
&pci_host_data_readl, |
|
| 126 |
}; |
|
| 127 |
|
|
| 128 |
static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr, |
|
| 129 |
uint32_t val) |
|
| 130 |
{
|
|
| 131 |
cpu_outb(NULL, addr & 0xffff, val); |
|
| 132 |
} |
|
| 133 |
|
|
| 134 |
static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr, |
|
| 135 |
uint32_t val) |
|
| 136 |
{
|
|
| 137 |
cpu_outw(NULL, addr & 0xffff, val); |
|
| 138 |
} |
|
| 139 |
|
|
| 140 |
static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr, |
|
| 141 |
uint32_t val) |
|
| 142 |
{
|
|
| 143 |
cpu_outl(NULL, addr & 0xffff, val); |
|
| 144 |
} |
|
| 145 |
|
|
| 146 |
static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr) |
|
| 147 |
{
|
|
| 148 |
uint32_t val; |
|
| 149 |
|
|
| 150 |
val = cpu_inb(NULL, addr & 0xffff); |
|
| 151 |
return val; |
|
| 152 |
} |
|
| 153 |
|
|
| 154 |
static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr) |
|
| 155 |
{
|
|
| 156 |
uint32_t val; |
|
| 157 |
|
|
| 158 |
val = cpu_inw(NULL, addr & 0xffff); |
|
| 159 |
return val; |
|
| 160 |
} |
|
| 161 |
|
|
| 162 |
static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr) |
|
| 163 |
{
|
|
| 164 |
uint32_t val; |
|
| 165 |
|
|
| 166 |
val = cpu_inl(NULL, addr & 0xffff); |
|
| 167 |
return val; |
|
| 168 |
} |
|
| 169 |
|
|
| 170 |
static CPUWriteMemoryFunc *pci_apb_iowrite[] = {
|
|
| 171 |
&pci_apb_iowriteb, |
|
| 172 |
&pci_apb_iowritew, |
|
| 173 |
&pci_apb_iowritel, |
|
| 174 |
}; |
|
| 175 |
|
|
| 176 |
static CPUReadMemoryFunc *pci_apb_ioread[] = {
|
|
| 177 |
&pci_apb_ioreadb, |
|
| 178 |
&pci_apb_ioreadw, |
|
| 179 |
&pci_apb_ioreadl, |
|
| 180 |
}; |
|
| 181 |
|
|
| 182 |
/* ??? This is probably wrong. */ |
|
| 183 |
static void pci_apb_set_irq(PCIDevice *d, void *pic, int irq_num, int level) |
|
| 184 |
{
|
|
| 185 |
pic_set_irq_new(pic, d->config[PCI_INTERRUPT_LINE], level); |
|
| 186 |
} |
|
| 187 |
|
|
| 188 |
PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base, |
|
| 189 |
void *pic) |
|
| 190 |
{
|
|
| 191 |
APBState *s; |
|
| 192 |
PCIDevice *d; |
|
| 193 |
int pci_mem_config, pci_mem_data, apb_config, pci_ioport; |
|
| 194 |
|
|
| 195 |
s = qemu_mallocz(sizeof(APBState)); |
|
| 196 |
/* Ultrasparc APB main bus */ |
|
| 197 |
s->bus = pci_register_bus(pci_apb_set_irq, pic, 0); |
|
| 198 |
|
|
| 199 |
pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read, |
|
| 200 |
pci_apb_config_write, s); |
|
| 201 |
apb_config = cpu_register_io_memory(0, apb_config_read, |
|
| 202 |
apb_config_write, s); |
|
| 203 |
pci_mem_data = cpu_register_io_memory(0, pci_apb_read, |
|
| 204 |
pci_apb_write, s); |
|
| 205 |
pci_ioport = cpu_register_io_memory(0, pci_apb_ioread, |
|
| 206 |
pci_apb_iowrite, s); |
|
| 207 |
|
|
| 208 |
cpu_register_physical_memory(special_base + 0x2000ULL, 0x40, apb_config); |
|
| 209 |
cpu_register_physical_memory(special_base + 0x1000000ULL, 0x10, pci_mem_config); |
|
| 210 |
cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000, pci_ioport); |
|
| 211 |
cpu_register_physical_memory(mem_base, 0x10000000, pci_mem_data); // XXX size should be 4G-prom |
|
| 212 |
|
|
| 213 |
d = pci_register_device(s->bus, "Advanced PCI Bus", sizeof(PCIDevice), |
|
| 214 |
-1, NULL, NULL); |
|
| 215 |
d->config[0x00] = 0x8e; // vendor_id : Sun |
|
| 216 |
d->config[0x01] = 0x10; |
|
| 217 |
d->config[0x02] = 0x00; // device_id |
|
| 218 |
d->config[0x03] = 0xa0; |
|
| 219 |
d->config[0x04] = 0x06; // command = bus master, pci mem |
|
| 220 |
d->config[0x05] = 0x00; |
|
| 221 |
d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
|
| 222 |
d->config[0x07] = 0x03; // status = medium devsel |
|
| 223 |
d->config[0x08] = 0x00; // revision |
|
| 224 |
d->config[0x09] = 0x00; // programming i/f |
|
| 225 |
d->config[0x0A] = 0x00; // class_sub = pci host |
|
| 226 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
|
| 227 |
d->config[0x0D] = 0x10; // latency_timer |
|
| 228 |
d->config[0x0E] = 0x00; // header_type |
|
| 229 |
return s->bus; |
|
| 230 |
} |
|
| 231 |
|
|
| 232 |
|
|
| b/hw/grackle_pci.c | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
* QEMU Grackle (heathrow PPC) PCI host |
|
| 3 |
* |
|
| 4 |
* Copyright (c) 2006 Fabrice Bellard |
|
| 5 |
* |
|
| 6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy |
|
| 7 |
* of this software and associated documentation files (the "Software"), to deal |
|
| 8 |
* in the Software without restriction, including without limitation the rights |
|
| 9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
|
| 10 |
* copies of the Software, and to permit persons to whom the Software is |
|
| 11 |
* furnished to do so, subject to the following conditions: |
|
| 12 |
* |
|
| 13 |
* The above copyright notice and this permission notice shall be included in |
|
| 14 |
* all copies or substantial portions of the Software. |
|
| 15 |
* |
|
| 16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
|
| 17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
|
| 18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
|
| 19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
|
| 20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
|
| 21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
|
| 22 |
* THE SOFTWARE. |
|
| 23 |
*/ |
|
| 24 |
|
|
| 25 |
#include "vl.h" |
|
| 26 |
typedef target_phys_addr_t pci_addr_t; |
|
| 27 |
#include "pci_host.h" |
|
| 28 |
|
|
| 29 |
typedef PCIHostState GrackleState; |
|
| 30 |
|
|
| 31 |
static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr, |
|
| 32 |
uint32_t val) |
|
| 33 |
{
|
|
| 34 |
GrackleState *s = opaque; |
|
| 35 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 36 |
val = bswap32(val); |
|
| 37 |
#endif |
|
| 38 |
s->config_reg = val; |
|
| 39 |
} |
|
| 40 |
|
|
| 41 |
static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr) |
|
| 42 |
{
|
|
| 43 |
GrackleState *s = opaque; |
|
| 44 |
uint32_t val; |
|
| 45 |
|
|
| 46 |
val = s->config_reg; |
|
| 47 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 48 |
val = bswap32(val); |
|
| 49 |
#endif |
|
| 50 |
return val; |
|
| 51 |
} |
|
| 52 |
|
|
| 53 |
static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
|
|
| 54 |
&pci_grackle_config_writel, |
|
| 55 |
&pci_grackle_config_writel, |
|
| 56 |
&pci_grackle_config_writel, |
|
| 57 |
}; |
|
| 58 |
|
|
| 59 |
static CPUReadMemoryFunc *pci_grackle_config_read[] = {
|
|
| 60 |
&pci_grackle_config_readl, |
|
| 61 |
&pci_grackle_config_readl, |
|
| 62 |
&pci_grackle_config_readl, |
|
| 63 |
}; |
|
| 64 |
|
|
| 65 |
static CPUWriteMemoryFunc *pci_grackle_write[] = {
|
|
| 66 |
&pci_host_data_writeb, |
|
| 67 |
&pci_host_data_writew, |
|
| 68 |
&pci_host_data_writel, |
|
| 69 |
}; |
|
| 70 |
|
|
| 71 |
static CPUReadMemoryFunc *pci_grackle_read[] = {
|
|
| 72 |
&pci_host_data_readb, |
|
| 73 |
&pci_host_data_readw, |
|
| 74 |
&pci_host_data_readl, |
|
| 75 |
}; |
|
| 76 |
|
|
| 77 |
/* XXX: we do not simulate the hardware - we rely on the BIOS to |
|
| 78 |
set correctly for irq line field */ |
|
| 79 |
static void pci_grackle_set_irq(PCIDevice *d, void *pic, int irq_num, int level) |
|
| 80 |
{
|
|
| 81 |
heathrow_pic_set_irq(pic, d->config[PCI_INTERRUPT_LINE], level); |
|
| 82 |
} |
|
| 83 |
|
|
| 84 |
PCIBus *pci_grackle_init(uint32_t base, void *pic) |
|
| 85 |
{
|
|
| 86 |
GrackleState *s; |
|
| 87 |
PCIDevice *d; |
|
| 88 |
int pci_mem_config, pci_mem_data; |
|
| 89 |
|
|
| 90 |
s = qemu_mallocz(sizeof(GrackleState)); |
|
| 91 |
s->bus = pci_register_bus(pci_grackle_set_irq, pic, 0); |
|
| 92 |
|
|
| 93 |
pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read, |
|
| 94 |
pci_grackle_config_write, s); |
|
| 95 |
pci_mem_data = cpu_register_io_memory(0, pci_grackle_read, |
|
| 96 |
pci_grackle_write, s); |
|
| 97 |
cpu_register_physical_memory(base, 0x1000, pci_mem_config); |
|
| 98 |
cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data); |
|
| 99 |
d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice), |
|
| 100 |
0, NULL, NULL); |
|
| 101 |
d->config[0x00] = 0x57; // vendor_id |
|
| 102 |
d->config[0x01] = 0x10; |
|
| 103 |
d->config[0x02] = 0x02; // device_id |
|
| 104 |
d->config[0x03] = 0x00; |
|
| 105 |
d->config[0x08] = 0x00; // revision |
|
| 106 |
d->config[0x09] = 0x01; |
|
| 107 |
d->config[0x0a] = 0x00; // class_sub = host |
|
| 108 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
|
| 109 |
d->config[0x0e] = 0x00; // header_type |
|
| 110 |
|
|
| 111 |
d->config[0x18] = 0x00; // primary_bus |
|
| 112 |
d->config[0x19] = 0x01; // secondary_bus |
|
| 113 |
d->config[0x1a] = 0x00; // subordinate_bus |
|
| 114 |
d->config[0x1c] = 0x00; |
|
| 115 |
d->config[0x1d] = 0x00; |
|
| 116 |
|
|
| 117 |
d->config[0x20] = 0x00; // memory_base |
|
| 118 |
d->config[0x21] = 0x00; |
|
| 119 |
d->config[0x22] = 0x01; // memory_limit |
|
| 120 |
d->config[0x23] = 0x00; |
|
| 121 |
|
|
| 122 |
d->config[0x24] = 0x00; // prefetchable_memory_base |
|
| 123 |
d->config[0x25] = 0x00; |
|
| 124 |
d->config[0x26] = 0x00; // prefetchable_memory_limit |
|
| 125 |
d->config[0x27] = 0x00; |
|
| 126 |
|
|
| 127 |
#if 0 |
|
| 128 |
/* PCI2PCI bridge same values as PearPC - check this */ |
|
| 129 |
d->config[0x00] = 0x11; // vendor_id |
|
| 130 |
d->config[0x01] = 0x10; |
|
| 131 |
d->config[0x02] = 0x26; // device_id |
|
| 132 |
d->config[0x03] = 0x00; |
|
| 133 |
d->config[0x08] = 0x02; // revision |
|
| 134 |
d->config[0x0a] = 0x04; // class_sub = pci2pci |
|
| 135 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
|
| 136 |
d->config[0x0e] = 0x01; // header_type |
|
| 137 |
|
|
| 138 |
d->config[0x18] = 0x0; // primary_bus |
|
| 139 |
d->config[0x19] = 0x1; // secondary_bus |
|
| 140 |
d->config[0x1a] = 0x1; // subordinate_bus |
|
| 141 |
d->config[0x1c] = 0x10; // io_base |
|
| 142 |
d->config[0x1d] = 0x20; // io_limit |
|
| 143 |
|
|
| 144 |
d->config[0x20] = 0x80; // memory_base |
|
| 145 |
d->config[0x21] = 0x80; |
|
| 146 |
d->config[0x22] = 0x90; // memory_limit |
|
| 147 |
d->config[0x23] = 0x80; |
|
| 148 |
|
|
| 149 |
d->config[0x24] = 0x00; // prefetchable_memory_base |
|
| 150 |
d->config[0x25] = 0x84; |
|
| 151 |
d->config[0x26] = 0x00; // prefetchable_memory_limit |
|
| 152 |
d->config[0x27] = 0x85; |
|
| 153 |
#endif |
|
| 154 |
return s->bus; |
|
| 155 |
} |
|
| 156 |
|
|
| b/hw/ide.c | ||
|---|---|---|
| 2490 | 2490 |
|
| 2491 | 2491 |
/* hd_table must contain 4 block drivers */ |
| 2492 | 2492 |
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ |
| 2493 |
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table) |
|
| 2493 |
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn)
|
|
| 2494 | 2494 |
{
|
| 2495 | 2495 |
PCIIDEState *d; |
| 2496 | 2496 |
uint8_t *pci_conf; |
| ... | ... | |
| 2498 | 2498 |
/* register a function 1 of PIIX3 */ |
| 2499 | 2499 |
d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE", |
| 2500 | 2500 |
sizeof(PCIIDEState), |
| 2501 |
((PCIDevice *)piix3_state)->devfn + 1,
|
|
| 2501 |
devfn,
|
|
| 2502 | 2502 |
NULL, NULL); |
| 2503 | 2503 |
d->type = IDE_TYPE_PIIX3; |
| 2504 | 2504 |
|
| b/hw/pc.c | ||
|---|---|---|
| 611 | 611 |
unsigned long bios_offset, vga_bios_offset; |
| 612 | 612 |
int bios_size, isa_bios_size; |
| 613 | 613 |
PCIBus *pci_bus; |
| 614 |
int piix3_devfn; |
|
| 614 | 615 |
CPUState *env; |
| 615 | 616 |
NICInfo *nd; |
| 616 | 617 |
|
| ... | ... | |
| 741 | 742 |
|
| 742 | 743 |
if (pci_enabled) {
|
| 743 | 744 |
pci_bus = i440fx_init(); |
| 744 |
piix3_init(pci_bus); |
|
| 745 |
piix3_devfn = piix3_init(pci_bus);
|
|
| 745 | 746 |
} else {
|
| 746 | 747 |
pci_bus = NULL; |
| 747 | 748 |
} |
| ... | ... | |
| 813 | 814 |
} |
| 814 | 815 |
|
| 815 | 816 |
if (pci_enabled) {
|
| 816 |
pci_piix3_ide_init(pci_bus, bs_table); |
|
| 817 |
pci_piix3_ide_init(pci_bus, bs_table, piix3_devfn + 1);
|
|
| 817 | 818 |
} else {
|
| 818 | 819 |
for(i = 0; i < 2; i++) {
|
| 819 | 820 |
isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
| ... | ... | |
| 832 | 833 |
cmos_init(ram_size, boot_device, bs_table); |
| 833 | 834 |
|
| 834 | 835 |
if (pci_enabled && usb_enabled) {
|
| 835 |
usb_uhci_init(pci_bus, usb_root_ports); |
|
| 836 |
usb_uhci_init(pci_bus, usb_root_ports, piix3_devfn + 2);
|
|
| 836 | 837 |
usb_attach(usb_root_ports[0], vm_usb_hub); |
| 837 | 838 |
} |
| 838 | 839 |
|
| 839 | 840 |
if (pci_enabled && acpi_enabled) {
|
| 840 |
piix4_pm_init(pci_bus); |
|
| 841 |
piix4_pm_init(pci_bus, piix3_devfn + 3);
|
|
| 841 | 842 |
} |
| 842 | 843 |
/* must be done after all PCI devices are instanciated */ |
| 843 | 844 |
/* XXX: should be done in the Bochs BIOS */ |
| b/hw/pci.c | ||
|---|---|---|
| 25 | 25 |
|
| 26 | 26 |
//#define DEBUG_PCI |
| 27 | 27 |
|
| 28 |
#define PCI_VENDOR_ID 0x00 /* 16 bits */ |
|
| 29 |
#define PCI_DEVICE_ID 0x02 /* 16 bits */ |
|
| 30 |
#define PCI_COMMAND 0x04 /* 16 bits */ |
|
| 31 |
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
|
| 32 |
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
|
| 33 |
#define PCI_CLASS_DEVICE 0x0a /* Device class */ |
|
| 34 |
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
|
| 35 |
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
|
| 36 |
#define PCI_MIN_GNT 0x3e /* 8 bits */ |
|
| 37 |
#define PCI_MAX_LAT 0x3f /* 8 bits */ |
|
| 38 |
|
|
| 39 |
/* just used for simpler irq handling. */ |
|
| 40 |
#define PCI_DEVICES_MAX 64 |
|
| 41 |
#define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32) |
|
| 42 |
|
|
| 43 | 28 |
struct PCIBus {
|
| 44 | 29 |
int bus_num; |
| 45 | 30 |
int devfn_min; |
| 46 |
void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level);
|
|
| 31 |
pci_set_irq_fn set_irq;
|
|
| 47 | 32 |
uint32_t config_reg; /* XXX: suppress */ |
| 48 | 33 |
/* low level pic */ |
| 49 | 34 |
SetIRQFunc *low_set_irq; |
| ... | ... | |
| 53 | 38 |
|
| 54 | 39 |
target_phys_addr_t pci_mem_base; |
| 55 | 40 |
static int pci_irq_index; |
| 56 |
static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS]; |
|
| 57 | 41 |
static PCIBus *first_bus; |
| 58 | 42 |
|
| 59 |
static PCIBus *pci_register_bus(void)
|
|
| 43 |
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, void *pic, int devfn_min)
|
|
| 60 | 44 |
{
|
| 61 | 45 |
PCIBus *bus; |
| 62 | 46 |
bus = qemu_mallocz(sizeof(PCIBus)); |
| 47 |
bus->set_irq = set_irq; |
|
| 48 |
bus->irq_opaque = pic; |
|
| 49 |
bus->devfn_min = devfn_min; |
|
| 63 | 50 |
first_bus = bus; |
| 64 | 51 |
return bus; |
| 65 | 52 |
} |
| 66 | 53 |
|
| 54 |
int pci_bus_num(PCIBus *s) |
|
| 55 |
{
|
|
| 56 |
return s->bus_num; |
|
| 57 |
} |
|
| 58 |
|
|
| 67 | 59 |
void generic_pci_save(QEMUFile* f, void *opaque) |
| 68 | 60 |
{
|
| 69 | 61 |
PCIDevice* s=(PCIDevice*)opaque; |
| ... | ... | |
| 141 | 133 |
*(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); |
| 142 | 134 |
} |
| 143 | 135 |
|
| 144 |
static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val) |
|
| 145 |
{
|
|
| 146 |
PCIBus *s = opaque; |
|
| 147 |
s->config_reg = val; |
|
| 148 |
} |
|
| 149 |
|
|
| 150 |
static uint32_t pci_addr_readl(void* opaque, uint32_t addr) |
|
| 136 |
target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr) |
|
| 151 | 137 |
{
|
| 152 |
PCIBus *s = opaque; |
|
| 153 |
return s->config_reg; |
|
| 138 |
return addr + pci_mem_base; |
|
| 154 | 139 |
} |
| 155 | 140 |
|
| 156 | 141 |
static void pci_update_mappings(PCIDevice *d) |
| ... | ... | |
| 218 | 203 |
isa_unassign_ioport(r->addr, r->size); |
| 219 | 204 |
} |
| 220 | 205 |
} else {
|
| 221 |
cpu_register_physical_memory(r->addr + pci_mem_base,
|
|
| 206 |
cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
|
|
| 222 | 207 |
r->size, |
| 223 | 208 |
IO_MEM_UNASSIGNED); |
| 224 | 209 |
} |
| ... | ... | |
| 346 | 331 |
} |
| 347 | 332 |
} |
| 348 | 333 |
|
| 349 |
static void pci_data_write(void *opaque, uint32_t addr, |
|
| 350 |
uint32_t val, int len) |
|
| 334 |
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) |
|
| 351 | 335 |
{
|
| 352 | 336 |
PCIBus *s = opaque; |
| 353 | 337 |
PCIDevice *pci_dev; |
| ... | ... | |
| 355 | 339 |
|
| 356 | 340 |
#if defined(DEBUG_PCI) && 0 |
| 357 | 341 |
printf("pci_data_write: addr=%08x val=%08x len=%d\n",
|
| 358 |
s->config_reg, val, len);
|
|
| 342 |
addr, val, len);
|
|
| 359 | 343 |
#endif |
| 360 |
if (!(s->config_reg & (1 << 31))) {
|
|
| 361 |
return; |
|
| 362 |
} |
|
| 363 |
bus_num = (s->config_reg >> 16) & 0xff; |
|
| 344 |
bus_num = (addr >> 16) & 0xff; |
|
| 364 | 345 |
if (bus_num != 0) |
| 365 | 346 |
return; |
| 366 |
pci_dev = s->devices[(s->config_reg >> 8) & 0xff];
|
|
| 347 |
pci_dev = s->devices[(addr >> 8) & 0xff];
|
|
| 367 | 348 |
if (!pci_dev) |
| 368 | 349 |
return; |
| 369 |
config_addr = (s->config_reg & 0xfc) | (addr & 3);
|
|
| 350 |
config_addr = addr & 0xff;
|
|
| 370 | 351 |
#if defined(DEBUG_PCI) |
| 371 | 352 |
printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
|
| 372 | 353 |
pci_dev->name, config_addr, val, len); |
| ... | ... | |
| 374 | 355 |
pci_dev->config_write(pci_dev, config_addr, val, len); |
| 375 | 356 |
} |
| 376 | 357 |
|
| 377 |
static uint32_t pci_data_read(void *opaque, uint32_t addr, |
|
| 378 |
int len) |
|
| 358 |
uint32_t pci_data_read(void *opaque, uint32_t addr, int len) |
|
| 379 | 359 |
{
|
| 380 | 360 |
PCIBus *s = opaque; |
| 381 | 361 |
PCIDevice *pci_dev; |
| 382 | 362 |
int config_addr, bus_num; |
| 383 | 363 |
uint32_t val; |
| 384 | 364 |
|
| 385 |
if (!(s->config_reg & (1 << 31))) |
|
| 386 |
goto fail; |
|
| 387 |
bus_num = (s->config_reg >> 16) & 0xff; |
|
| 365 |
bus_num = (addr >> 16) & 0xff; |
|
| 388 | 366 |
if (bus_num != 0) |
| 389 | 367 |
goto fail; |
| 390 |
pci_dev = s->devices[(s->config_reg >> 8) & 0xff];
|
|
| 368 |
pci_dev = s->devices[(addr >> 8) & 0xff];
|
|
| 391 | 369 |
if (!pci_dev) {
|
| 392 | 370 |
fail: |
| 393 | 371 |
switch(len) {
|
| ... | ... | |
| 404 | 382 |
} |
| 405 | 383 |
goto the_end; |
| 406 | 384 |
} |
| 407 |
config_addr = (s->config_reg & 0xfc) | (addr & 3);
|
|
| 385 |
config_addr = addr & 0xff;
|
|
| 408 | 386 |
val = pci_dev->config_read(pci_dev, config_addr, len); |
| 409 | 387 |
#if defined(DEBUG_PCI) |
| 410 | 388 |
printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
|
| ... | ... | |
| 413 | 391 |
the_end: |
| 414 | 392 |
#if defined(DEBUG_PCI) && 0 |
| 415 | 393 |
printf("pci_data_read: addr=%08x val=%08x len=%d\n",
|
| 416 |
s->config_reg, val, len);
|
|
| 394 |
addr, val, len);
|
|
| 417 | 395 |
#endif |
| 418 | 396 |
return val; |
| 419 | 397 |
} |
| 420 | 398 |
|
| 421 |
static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val) |
|
| 422 |
{
|
|
| 423 |
pci_data_write(opaque, addr, val, 1); |
|
| 424 |
} |
|
| 425 |
|
|
| 426 |
static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val) |
|
| 427 |
{
|
|
| 428 |
pci_data_write(opaque, addr, val, 2); |
|
| 429 |
} |
|
| 430 |
|
|
| 431 |
static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val) |
|
| 432 |
{
|
|
| 433 |
pci_data_write(opaque, addr, val, 4); |
|
| 434 |
} |
|
| 435 |
|
|
| 436 |
static uint32_t pci_data_readb(void* opaque, uint32_t addr) |
|
| 437 |
{
|
|
| 438 |
return pci_data_read(opaque, addr, 1); |
|
| 439 |
} |
|
| 440 |
|
|
| 441 |
static uint32_t pci_data_readw(void* opaque, uint32_t addr) |
|
| 442 |
{
|
|
| 443 |
return pci_data_read(opaque, addr, 2); |
|
| 444 |
} |
|
| 445 |
|
|
| 446 |
static uint32_t pci_data_readl(void* opaque, uint32_t addr) |
|
| 447 |
{
|
|
| 448 |
return pci_data_read(opaque, addr, 4); |
|
| 449 |
} |
|
| 450 |
|
|
| 451 |
/* i440FX PCI bridge */ |
|
| 452 |
|
|
| 453 |
static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level); |
|
| 399 |
/***********************************************************/ |
|
| 400 |
/* generic PCI irq support */ |
|
| 454 | 401 |
|
| 455 |
PCIBus *i440fx_init(void) |
|
| 402 |
/* 0 <= irq_num <= 3. level must be 0 or 1 */ |
|
| 403 |
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level) |
|
| 456 | 404 |
{
|
| 457 |
PCIBus *s; |
|
| 458 |
PCIDevice *d; |
|
| 459 |
|
|
| 460 |
s = pci_register_bus(); |
|
| 461 |
s->set_irq = piix3_set_irq; |
|
| 462 |
|
|
| 463 |
register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s); |
|
| 464 |
register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s); |
|
| 465 |
|
|
| 466 |
register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s); |
|
| 467 |
register_ioport_write(0xcfc, 4, 2, pci_data_writew, s); |
|
| 468 |
register_ioport_write(0xcfc, 4, 4, pci_data_writel, s); |
|
| 469 |
register_ioport_read(0xcfc, 4, 1, pci_data_readb, s); |
|
| 470 |
register_ioport_read(0xcfc, 4, 2, pci_data_readw, s); |
|
| 471 |
register_ioport_read(0xcfc, 4, 4, pci_data_readl, s); |
|
| 472 |
|
|
| 473 |
d = pci_register_device(s, "i440FX", sizeof(PCIDevice), 0, |
|
| 474 |
NULL, NULL); |
|
| 475 |
|
|
| 476 |
d->config[0x00] = 0x86; // vendor_id |
|
| 477 |
d->config[0x01] = 0x80; |
|
| 478 |
d->config[0x02] = 0x37; // device_id |
|
| 479 |
d->config[0x03] = 0x12; |
|
| 480 |
d->config[0x08] = 0x02; // revision |
|
| 481 |
d->config[0x0a] = 0x00; // class_sub = host2pci |
|
| 482 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
|
| 483 |
d->config[0x0e] = 0x00; // header_type |
|
| 484 |
return s; |
|
| 405 |
PCIBus *bus = pci_dev->bus; |
|
| 406 |
bus->set_irq(pci_dev, bus->irq_opaque, irq_num, level); |
|
| 485 | 407 |
} |
| 486 | 408 |
|
| 487 |
/* PIIX3 PCI to ISA bridge */ |
|
| 488 |
|
|
| 489 |
typedef struct PIIX3State {
|
|
| 490 |
PCIDevice dev; |
|
| 491 |
} PIIX3State; |
|
| 492 |
|
|
| 493 |
PIIX3State *piix3_state; |
|
| 409 |
/***********************************************************/ |
|
| 410 |
/* monitor info on PCI */ |
|
| 494 | 411 |
|
| 495 |
/* return the global irq number corresponding to a given device irq |
|
| 496 |
pin. We could also use the bus number to have a more precise |
|
| 497 |
mapping. */ |
|
| 498 |
static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) |
|
| 412 |
static void pci_info_device(PCIDevice *d) |
|
| 499 | 413 |
{
|
| 500 |
int slot_addend; |
|
| 501 |
slot_addend = (pci_dev->devfn >> 3) - 1; |
|
| 502 |
return (irq_num + slot_addend) & 3; |
|
| 503 |
} |
|
| 414 |
int i, class; |
|
| 415 |
PCIIORegion *r; |
|
| 504 | 416 |
|
| 505 |
static inline int get_pci_irq_level(int irq_num) |
|
| 506 |
{
|
|
| 507 |
int pic_level; |
|
| 508 |
#if (PCI_IRQ_WORDS == 2) |
|
| 509 |
pic_level = ((pci_irq_levels[irq_num][0] | |
|
| 510 |
pci_irq_levels[irq_num][1]) != 0); |
|
| 511 |
#else |
|
| 512 |
{
|
|
| 513 |
int i; |
|
| 514 |
pic_level = 0; |
|
| 515 |
for(i = 0; i < PCI_IRQ_WORDS; i++) {
|
|
| 516 |
if (pci_irq_levels[irq_num][i]) {
|
|
| 517 |
pic_level = 1; |
|
| 518 |
break; |
|
| 519 |
} |
|
| 520 |
} |
|
| 417 |
term_printf(" Bus %2d, device %3d, function %d:\n",
|
|
| 418 |
d->bus->bus_num, d->devfn >> 3, d->devfn & 7); |
|
| 419 |
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
|
| 420 |
term_printf(" ");
|
|
| 421 |
switch(class) {
|
|
| 422 |
case 0x0101: |
|
| 423 |
term_printf("IDE controller");
|
|
| 424 |
break; |
|
| 425 |
case 0x0200: |
|
| 426 |
term_printf("Ethernet controller");
|
|
| 427 |
break; |
|
| 428 |
case 0x0300: |
|
| 429 |
term_printf("VGA controller");
|
|
| 430 |
break; |
|
| 431 |
default: |
|
| 432 |
term_printf("Class %04x", class);
|
|
| 433 |
break; |
|
| 521 | 434 |
} |
| 522 |
#endif |
|
| 523 |
return pic_level; |
|
| 524 |
} |
|
| 525 |
|
|
| 526 |
static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level) |
|
| 527 |
{
|
|
| 528 |
int irq_index, shift, pic_irq, pic_level; |
|
| 529 |
uint32_t *p; |
|
| 530 |
|
|
| 531 |
irq_num = pci_slot_get_pirq(pci_dev, irq_num); |
|
| 532 |
irq_index = pci_dev->irq_index; |
|
| 533 |
p = &pci_irq_levels[irq_num][irq_index >> 5]; |
|
| 534 |
shift = (irq_index & 0x1f); |
|
| 535 |
*p = (*p & ~(1 << shift)) | (level << shift); |
|
| 435 |
term_printf(": PCI device %04x:%04x\n",
|
|
| 436 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
|
| 437 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
|
| 536 | 438 |
|
| 537 |
/* now we change the pic irq level according to the piix irq mappings */ |
|
| 538 |
/* XXX: optimize */ |
|
| 539 |
pic_irq = piix3_state->dev.config[0x60 + irq_num]; |
|
| 540 |
if (pic_irq < 16) {
|
|
| 541 |
/* the pic level is the logical OR of all the PCI irqs mapped |
|
| 542 |
to it */ |
|
| 543 |
pic_level = 0; |
|
| 544 |
if (pic_irq == piix3_state->dev.config[0x60]) |
|
| 545 |
pic_level |= get_pci_irq_level(0); |
|
| 546 |
if (pic_irq == piix3_state->dev.config[0x61]) |
|
| 547 |
pic_level |= get_pci_irq_level(1); |
|
| 548 |
if (pic_irq == piix3_state->dev.config[0x62]) |
|
| 549 |
pic_level |= get_pci_irq_level(2); |
|
| 550 |
if (pic_irq == piix3_state->dev.config[0x63]) |
|
| 551 |
pic_level |= get_pci_irq_level(3); |
|
| 552 |
pic_set_irq(pic_irq, pic_level); |
|
| 439 |
if (d->config[PCI_INTERRUPT_PIN] != 0) {
|
|
| 440 |
term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
|
|
| 553 | 441 |
} |
| 554 |
} |
|
| 555 |
|
|
| 556 |
static void piix3_reset(PIIX3State *d) |
|
| 557 |
{
|
|
| 558 |
uint8_t *pci_conf = d->dev.config; |
|
| 559 |
|
|
| 560 |
pci_conf[0x04] = 0x07; // master, memory and I/O |
|
| 561 |
pci_conf[0x05] = 0x00; |
|
| 562 |
pci_conf[0x06] = 0x00; |
|
| 563 |
pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
|
| 564 |
pci_conf[0x4c] = 0x4d; |
|
| 565 |
pci_conf[0x4e] = 0x03; |
|
| 566 |
pci_conf[0x4f] = 0x00; |
|
| 567 |
pci_conf[0x60] = 0x80; |
|
| 568 |
pci_conf[0x69] = 0x02; |
|
| 569 |
pci_conf[0x70] = 0x80; |
|
| 570 |
pci_conf[0x76] = 0x0c; |
|
| 571 |
pci_conf[0x77] = 0x0c; |
|
| 572 |
pci_conf[0x78] = 0x02; |
|
| 573 |
pci_conf[0x79] = 0x00; |
|
| 574 |
pci_conf[0x80] = 0x00; |
|
| 575 |
pci_conf[0x82] = 0x00; |
|
| 576 |
pci_conf[0xa0] = 0x08; |
|
| 577 |
pci_conf[0xa0] = 0x08; |
|
| 578 |
pci_conf[0xa2] = 0x00; |
|
| 579 |
pci_conf[0xa3] = 0x00; |
|
| 580 |
pci_conf[0xa4] = 0x00; |
|
| 581 |
pci_conf[0xa5] = 0x00; |
|
| 582 |
pci_conf[0xa6] = 0x00; |
|
| 583 |
pci_conf[0xa7] = 0x00; |
|
| 584 |
pci_conf[0xa8] = 0x0f; |
|
| 585 |
pci_conf[0xaa] = 0x00; |
|
| 586 |
pci_conf[0xab] = 0x00; |
|
| 587 |
pci_conf[0xac] = 0x00; |
|
| 588 |
pci_conf[0xae] = 0x00; |
|
| 589 |
} |
|
| 590 |
|
|
| 591 |
void piix3_init(PCIBus *bus) |
|
| 592 |
{
|
|
| 593 |
PIIX3State *d; |
|
| 594 |
uint8_t *pci_conf; |
|
| 595 |
|
|
| 596 |
d = (PIIX3State *)pci_register_device(bus, "PIIX3", sizeof(PIIX3State), |
|
| 597 |
-1, NULL, NULL); |
|
| 598 |
register_savevm("PIIX3", 0, 1, generic_pci_save, generic_pci_load, d);
|
|
| 599 |
|
|
| 600 |
piix3_state = d; |
|
| 601 |
pci_conf = d->dev.config; |
|
| 602 |
|
|
| 603 |
pci_conf[0x00] = 0x86; // Intel |
|
| 604 |
pci_conf[0x01] = 0x80; |
|
| 605 |
pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) |
|
| 606 |
pci_conf[0x03] = 0x70; |
|
| 607 |
pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
|
| 608 |
pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
|
| 609 |
pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
|
| 610 |
|
|
| 611 |
piix3_reset(d); |
|
| 612 |
} |
|
| 613 |
|
|
| 614 |
/* PREP pci init */ |
|
| 615 |
|
|
| 616 |
static inline void set_config(PCIBus *s, target_phys_addr_t addr) |
|
| 617 |
{
|
|
| 618 |
int devfn, i; |
|
| 619 |
|
|
| 620 |
for(i = 0; i < 11; i++) {
|
|
| 621 |
if ((addr & (1 << (11 + i))) != 0) |
|
| 622 |
break; |
|
| 442 |
for(i = 0;i < PCI_NUM_REGIONS; i++) {
|
|
| 443 |
r = &d->io_regions[i]; |
|
| 444 |
if (r->size != 0) {
|
|
| 445 |
term_printf(" BAR%d: ", i);
|
|
| 446 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
|
| 447 |
term_printf("I/O at 0x%04x [0x%04x].\n",
|
|
| 448 |
r->addr, r->addr + r->size - 1); |
|
| 449 |
} else {
|
|
| 450 |
term_printf("32 bit memory at 0x%08x [0x%08x].\n",
|
|
| 451 |
r->addr, r->addr + r->size - 1); |
|
| 452 |
} |
|
| 453 |
} |
|
| 623 | 454 |
} |
| 624 |
devfn = ((addr >> 8) & 7) | (i << 3); |
|
| 625 |
s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8); |
|
| 626 |
} |
|
| 627 |
|
|
| 628 |
static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) |
|
| 629 |
{
|
|
| 630 |
PCIBus *s = opaque; |
|
| 631 |
set_config(s, addr); |
|
| 632 |
pci_data_write(s, addr, val, 1); |
|
| 633 |
} |
|
| 634 |
|
|
| 635 |
static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val) |
|
| 636 |
{
|
|
| 637 |
PCIBus *s = opaque; |
|
| 638 |
set_config(s, addr); |
|
| 639 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 640 |
val = bswap16(val); |
|
| 641 |
#endif |
|
| 642 |
pci_data_write(s, addr, val, 2); |
|
| 643 |
} |
|
| 644 |
|
|
| 645 |
static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val) |
|
| 646 |
{
|
|
| 647 |
PCIBus *s = opaque; |
|
| 648 |
set_config(s, addr); |
|
| 649 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 650 |
val = bswap32(val); |
|
| 651 |
#endif |
|
| 652 |
pci_data_write(s, addr, val, 4); |
|
| 653 |
} |
|
| 654 |
|
|
| 655 |
static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr) |
|
| 656 |
{
|
|
| 657 |
PCIBus *s = opaque; |
|
| 658 |
uint32_t val; |
|
| 659 |
set_config(s, addr); |
|
| 660 |
val = pci_data_read(s, addr, 1); |
|
| 661 |
return val; |
|
| 662 |
} |
|
| 663 |
|
|
| 664 |
static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr) |
|
| 665 |
{
|
|
| 666 |
PCIBus *s = opaque; |
|
| 667 |
uint32_t val; |
|
| 668 |
set_config(s, addr); |
|
| 669 |
val = pci_data_read(s, addr, 2); |
|
| 670 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 671 |
val = bswap16(val); |
|
| 672 |
#endif |
|
| 673 |
return val; |
|
| 674 |
} |
|
| 675 |
|
|
| 676 |
static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr) |
|
| 677 |
{
|
|
| 678 |
PCIBus *s = opaque; |
|
| 679 |
uint32_t val; |
|
| 680 |
set_config(s, addr); |
|
| 681 |
val = pci_data_read(s, addr, 4); |
|
| 682 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 683 |
val = bswap32(val); |
|
| 684 |
#endif |
|
| 685 |
return val; |
|
| 686 |
} |
|
| 687 |
|
|
| 688 |
static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
|
|
| 689 |
&PPC_PCIIO_writeb, |
|
| 690 |
&PPC_PCIIO_writew, |
|
| 691 |
&PPC_PCIIO_writel, |
|
| 692 |
}; |
|
| 693 |
|
|
| 694 |
static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
|
|
| 695 |
&PPC_PCIIO_readb, |
|
| 696 |
&PPC_PCIIO_readw, |
|
| 697 |
&PPC_PCIIO_readl, |
|
| 698 |
}; |
|
| 699 |
|
|
| 700 |
static void prep_set_irq(PCIDevice *d, int irq_num, int level) |
|
| 701 |
{
|
|
| 702 |
/* XXX: we do not simulate the hardware - we rely on the BIOS to |
|
| 703 |
set correctly for irq line field */ |
|
| 704 |
pic_set_irq(d->config[PCI_INTERRUPT_LINE], level); |
|
| 705 |
} |
|
| 706 |
|
|
| 707 |
PCIBus *pci_prep_init(void) |
|
| 708 |
{
|
|
| 709 |
PCIBus *s; |
|
| 710 |
PCIDevice *d; |
|
| 711 |
int PPC_io_memory; |
|
| 712 |
|
|
| 713 |
s = pci_register_bus(); |
|
| 714 |
s->set_irq = prep_set_irq; |
|
| 715 |
|
|
| 716 |
register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s); |
|
| 717 |
register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s); |
|
| 718 |
|
|
| 719 |
register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s); |
|
| 720 |
register_ioport_write(0xcfc, 4, 2, pci_data_writew, s); |
|
| 721 |
register_ioport_write(0xcfc, 4, 4, pci_data_writel, s); |
|
| 722 |
register_ioport_read(0xcfc, 4, 1, pci_data_readb, s); |
|
| 723 |
register_ioport_read(0xcfc, 4, 2, pci_data_readw, s); |
|
| 724 |
register_ioport_read(0xcfc, 4, 4, pci_data_readl, s); |
|
| 725 |
|
|
| 726 |
PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read, |
|
| 727 |
PPC_PCIIO_write, s); |
|
| 728 |
cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory); |
|
| 729 |
|
|
| 730 |
/* PCI host bridge */ |
|
| 731 |
d = pci_register_device(s, "PREP Host Bridge - Motorola Raven", |
|
| 732 |
sizeof(PCIDevice), 0, NULL, NULL); |
|
| 733 |
d->config[0x00] = 0x57; // vendor_id : Motorola |
|
| 734 |
d->config[0x01] = 0x10; |
|
| 735 |
d->config[0x02] = 0x01; // device_id : Raven |
|
| 736 |
d->config[0x03] = 0x48; |
|
| 737 |
d->config[0x08] = 0x00; // revision |
|
| 738 |
d->config[0x0A] = 0x00; // class_sub = pci host |
|
| 739 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
|
| 740 |
d->config[0x0C] = 0x08; // cache_line_size |
|
| 741 |
d->config[0x0D] = 0x10; // latency_timer |
|
| 742 |
d->config[0x0E] = 0x00; // header_type |
|
| 743 |
d->config[0x34] = 0x00; // capabilities_pointer |
|
| 744 |
|
|
| 745 |
return s; |
|
| 746 |
} |
|
| 747 |
|
|
| 748 |
|
|
| 749 |
/* Grackle PCI host */ |
|
| 750 |
static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr, |
|
| 751 |
uint32_t val) |
|
| 752 |
{
|
|
| 753 |
PCIBus *s = opaque; |
|
| 754 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 755 |
val = bswap32(val); |
|
| 756 |
#endif |
|
| 757 |
s->config_reg = val; |
|
| 758 |
} |
|
| 759 |
|
|
| 760 |
static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr) |
|
| 761 |
{
|
|
| 762 |
PCIBus *s = opaque; |
|
| 763 |
uint32_t val; |
|
| 764 |
|
|
| 765 |
val = s->config_reg; |
|
| 766 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 767 |
val = bswap32(val); |
|
| 768 |
#endif |
|
| 769 |
return val; |
|
| 770 |
} |
|
| 771 |
|
|
| 772 |
static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
|
|
| 773 |
&pci_grackle_config_writel, |
|
| 774 |
&pci_grackle_config_writel, |
|
| 775 |
&pci_grackle_config_writel, |
|
| 776 |
}; |
|
| 777 |
|
|
| 778 |
static CPUReadMemoryFunc *pci_grackle_config_read[] = {
|
|
| 779 |
&pci_grackle_config_readl, |
|
| 780 |
&pci_grackle_config_readl, |
|
| 781 |
&pci_grackle_config_readl, |
|
| 782 |
}; |
|
| 783 |
|
|
| 784 |
static void pci_grackle_writeb (void *opaque, target_phys_addr_t addr, |
|
| 785 |
uint32_t val) |
|
| 786 |
{
|
|
| 787 |
PCIBus *s = opaque; |
|
| 788 |
pci_data_write(s, addr, val, 1); |
|
| 789 |
} |
|
| 790 |
|
|
| 791 |
static void pci_grackle_writew (void *opaque, target_phys_addr_t addr, |
|
| 792 |
uint32_t val) |
|
| 793 |
{
|
|
| 794 |
PCIBus *s = opaque; |
|
| 795 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 796 |
val = bswap16(val); |
|
| 797 |
#endif |
|
| 798 |
pci_data_write(s, addr, val, 2); |
|
| 799 |
} |
|
| 800 |
|
|
| 801 |
static void pci_grackle_writel (void *opaque, target_phys_addr_t addr, |
|
| 802 |
uint32_t val) |
|
| 803 |
{
|
|
| 804 |
PCIBus *s = opaque; |
|
| 805 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 806 |
val = bswap32(val); |
|
| 807 |
#endif |
|
| 808 |
pci_data_write(s, addr, val, 4); |
|
| 809 |
} |
|
| 810 |
|
|
| 811 |
static uint32_t pci_grackle_readb (void *opaque, target_phys_addr_t addr) |
|
| 812 |
{
|
|
| 813 |
PCIBus *s = opaque; |
|
| 814 |
uint32_t val; |
|
| 815 |
val = pci_data_read(s, addr, 1); |
|
| 816 |
return val; |
|
| 817 |
} |
|
| 818 |
|
|
| 819 |
static uint32_t pci_grackle_readw (void *opaque, target_phys_addr_t addr) |
|
| 820 |
{
|
|
| 821 |
PCIBus *s = opaque; |
|
| 822 |
uint32_t val; |
|
| 823 |
val = pci_data_read(s, addr, 2); |
|
| 824 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 825 |
val = bswap16(val); |
|
| 826 |
#endif |
|
| 827 |
return val; |
|
| 828 |
} |
|
| 829 |
|
|
| 830 |
static uint32_t pci_grackle_readl (void *opaque, target_phys_addr_t addr) |
|
| 831 |
{
|
|
| 832 |
PCIBus *s = opaque; |
|
| 833 |
uint32_t val; |
|
| 834 |
|
|
| 835 |
val = pci_data_read(s, addr, 4); |
|
| 836 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 837 |
val = bswap32(val); |
|
| 838 |
#endif |
|
| 839 |
return val; |
|
| 840 |
} |
|
| 841 |
|
|
| 842 |
static CPUWriteMemoryFunc *pci_grackle_write[] = {
|
|
| 843 |
&pci_grackle_writeb, |
|
| 844 |
&pci_grackle_writew, |
|
| 845 |
&pci_grackle_writel, |
|
| 846 |
}; |
|
| 847 |
|
|
| 848 |
static CPUReadMemoryFunc *pci_grackle_read[] = {
|
|
| 849 |
&pci_grackle_readb, |
|
| 850 |
&pci_grackle_readw, |
|
| 851 |
&pci_grackle_readl, |
|
| 852 |
}; |
|
| 853 |
|
|
| 854 |
void pci_set_pic(PCIBus *bus, SetIRQFunc *set_irq, void *irq_opaque) |
|
| 855 |
{
|
|
| 856 |
bus->low_set_irq = set_irq; |
|
| 857 |
bus->irq_opaque = irq_opaque; |
|
| 858 |
} |
|
| 859 |
|
|
| 860 |
/* XXX: we do not simulate the hardware - we rely on the BIOS to |
|
| 861 |
set correctly for irq line field */ |
|
| 862 |
static void pci_set_irq_simple(PCIDevice *d, int irq_num, int level) |
|
| 863 |
{
|
|
| 864 |
PCIBus *s = d->bus; |
|
| 865 |
s->low_set_irq(s->irq_opaque, d->config[PCI_INTERRUPT_LINE], level); |
|
| 866 | 455 |
} |
| 867 | 456 |
|
| 868 |
PCIBus *pci_grackle_init(uint32_t base)
|
|
| 457 |
void pci_for_each_device(void (*fn)(PCIDevice *d))
|
|
| 869 | 458 |
{
|
| 870 |
PCIBus *s; |
|
| 459 |
PCIBus *bus = first_bus;
|
|
| 871 | 460 |
PCIDevice *d; |
| 872 |
int pci_mem_config, pci_mem_data; |
|
| 873 |
|
|
| 874 |
s = pci_register_bus(); |
|
| 875 |
s->set_irq = pci_set_irq_simple; |
|
| 876 |
|
|
| 877 |
pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read, |
|
| 878 |
pci_grackle_config_write, s); |
|
| 879 |
pci_mem_data = cpu_register_io_memory(0, pci_grackle_read, |
|
| 880 |
pci_grackle_write, s); |
|
| 881 |
cpu_register_physical_memory(base, 0x1000, pci_mem_config); |
|
| 882 |
cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data); |
|
| 883 |
d = pci_register_device(s, "Grackle host bridge", sizeof(PCIDevice), |
|
| 884 |
0, NULL, NULL); |
|
| 885 |
d->config[0x00] = 0x57; // vendor_id |
|
| 886 |
d->config[0x01] = 0x10; |
|
| 887 |
d->config[0x02] = 0x02; // device_id |
|
| 888 |
d->config[0x03] = 0x00; |
|
| 889 |
d->config[0x08] = 0x00; // revision |
|
| 890 |
d->config[0x09] = 0x01; |
|
| 891 |
d->config[0x0a] = 0x00; // class_sub = host |
|
| 892 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
|
| 893 |
d->config[0x0e] = 0x00; // header_type |
|
| 894 |
|
|
| 895 |
d->config[0x18] = 0x00; // primary_bus |
|
| 896 |
d->config[0x19] = 0x01; // secondary_bus |
|
| 897 |
d->config[0x1a] = 0x00; // subordinate_bus |
|
| 898 |
d->config[0x1c] = 0x00; |
|
| 899 |
d->config[0x1d] = 0x00; |
|
| 900 |
|
|
| 901 |
d->config[0x20] = 0x00; // memory_base |
|
| 902 |
d->config[0x21] = 0x00; |
|
| 903 |
d->config[0x22] = 0x01; // memory_limit |
|
| 904 |
d->config[0x23] = 0x00; |
|
| 905 |
|
|
| 906 |
d->config[0x24] = 0x00; // prefetchable_memory_base |
|
| 907 |
d->config[0x25] = 0x00; |
|
| 908 |
d->config[0x26] = 0x00; // prefetchable_memory_limit |
|
| 909 |
d->config[0x27] = 0x00; |
|
| 910 |
|
|
| 911 |
#if 0 |
|
| 912 |
/* PCI2PCI bridge same values as PearPC - check this */ |
|
| 913 |
d->config[0x00] = 0x11; // vendor_id |
|
| 914 |
d->config[0x01] = 0x10; |
|
| 915 |
d->config[0x02] = 0x26; // device_id |
|
| 916 |
d->config[0x03] = 0x00; |
|
| 917 |
d->config[0x08] = 0x02; // revision |
|
| 918 |
d->config[0x0a] = 0x04; // class_sub = pci2pci |
|
| 919 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
|
| 920 |
d->config[0x0e] = 0x01; // header_type |
|
| 921 |
|
|
| 922 |
d->config[0x18] = 0x0; // primary_bus |
|
| 923 |
d->config[0x19] = 0x1; // secondary_bus |
|
| 924 |
d->config[0x1a] = 0x1; // subordinate_bus |
|
| 925 |
d->config[0x1c] = 0x10; // io_base |
|
| 926 |
d->config[0x1d] = 0x20; // io_limit |
|
| 927 |
|
|
| 928 |
d->config[0x20] = 0x80; // memory_base |
|
| 929 |
d->config[0x21] = 0x80; |
|
| 930 |
d->config[0x22] = 0x90; // memory_limit |
|
| 931 |
d->config[0x23] = 0x80; |
|
| 461 |
int devfn; |
|
| 932 | 462 |
|
| 933 |
d->config[0x24] = 0x00; // prefetchable_memory_base |
|
| 934 |
d->config[0x25] = 0x84; |
|
| 935 |
d->config[0x26] = 0x00; // prefetchable_memory_limit |
|
| 936 |
d->config[0x27] = 0x85; |
|
| 937 |
#endif |
|
| 938 |
return s; |
|
| 939 |
} |
|
| 940 |
|
|
| 941 |
/* Uninorth PCI host (for all Mac99 and newer machines */ |
|
| 942 |
static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr, |
|
| 943 |
uint32_t val) |
|
| 944 |
{
|
|
| 945 |
PCIBus *s = opaque; |
|
| 946 |
int i; |
|
| 947 |
|
|
| 948 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 949 |
val = bswap32(val); |
|
| 950 |
#endif |
|
| 951 |
|
|
| 952 |
for (i = 11; i < 32; i++) {
|
|
| 953 |
if ((val & (1 << i)) != 0) |
|
| 954 |
break; |
|
| 463 |
if (bus) {
|
|
| 464 |
for(devfn = 0; devfn < 256; devfn++) {
|
|
| 465 |
d = bus->devices[devfn]; |
|
| 466 |
if (d) |
|
| 467 |
fn(d); |
|
| 468 |
} |
|
| 955 | 469 |
} |
| 956 |
#if 0 |
|
| 957 |
s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11); |
|
| 958 |
#else |
|
| 959 |
s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11); |
|
| 960 |
#endif |
|
| 961 | 470 |
} |
| 962 | 471 |
|
| 963 |
static uint32_t pci_unin_main_config_readl (void *opaque, |
|
| 964 |
target_phys_addr_t addr) |
|
| 472 |
void pci_info(void) |
|
| 965 | 473 |
{
|
| 966 |
PCIBus *s = opaque; |
|
| 967 |
uint32_t val; |
|
| 968 |
int devfn; |
|
| 969 |
|
|
| 970 |
devfn = (s->config_reg >> 8) & 0xFF; |
|
| 971 |
val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC); |
|
| 972 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 973 |
val = bswap32(val); |
|
| 974 |
#endif |
|
| 975 |
|
|
| 976 |
return val; |
|
| 977 |
} |
|
| 978 |
|
|
| 979 |
static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
|
|
| 980 |
&pci_unin_main_config_writel, |
|
| 981 |
&pci_unin_main_config_writel, |
|
| 982 |
&pci_unin_main_config_writel, |
|
| 983 |
}; |
|
| 984 |
|
|
| 985 |
static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
|
|
| 986 |
&pci_unin_main_config_readl, |
|
| 987 |
&pci_unin_main_config_readl, |
|
| 988 |
&pci_unin_main_config_readl, |
|
| 989 |
}; |
|
| 990 |
|
|
| 991 |
static void pci_unin_main_writeb (void *opaque, target_phys_addr_t addr, |
|
| 992 |
uint32_t val) |
|
| 993 |
{
|
|
| 994 |
PCIBus *s = opaque; |
|
| 995 |
pci_data_write(s, addr & 7, val, 1); |
|
| 996 |
} |
|
| 997 |
|
|
| 998 |
static void pci_unin_main_writew (void *opaque, target_phys_addr_t addr, |
|
| 999 |
uint32_t val) |
|
| 1000 |
{
|
|
| 1001 |
PCIBus *s = opaque; |
|
| 1002 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 1003 |
val = bswap16(val); |
|
| 1004 |
#endif |
|
| 1005 |
pci_data_write(s, addr & 7, val, 2); |
|
| 1006 |
} |
|
| 1007 |
|
|
| 1008 |
static void pci_unin_main_writel (void *opaque, target_phys_addr_t addr, |
|
| 1009 |
uint32_t val) |
|
| 1010 |
{
|
|
| 1011 |
PCIBus *s = opaque; |
|
| 1012 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 1013 |
val = bswap32(val); |
|
| 1014 |
#endif |
|
| 1015 |
pci_data_write(s, addr & 7, val, 4); |
|
| 1016 |
} |
|
| 1017 |
|
|
| 1018 |
static uint32_t pci_unin_main_readb (void *opaque, target_phys_addr_t addr) |
|
| 1019 |
{
|
|
| 1020 |
PCIBus *s = opaque; |
|
| 1021 |
uint32_t val; |
|
| 1022 |
|
|
| 1023 |
val = pci_data_read(s, addr & 7, 1); |
|
| 1024 |
|
|
| 1025 |
return val; |
|
| 1026 |
} |
|
| 1027 |
|
|
| 1028 |
static uint32_t pci_unin_main_readw (void *opaque, target_phys_addr_t addr) |
|
| 1029 |
{
|
|
| 1030 |
PCIBus *s = opaque; |
|
| 1031 |
uint32_t val; |
|
| 1032 |
|
|
| 1033 |
val = pci_data_read(s, addr & 7, 2); |
|
| 1034 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 1035 |
val = bswap16(val); |
|
| 1036 |
#endif |
|
| 1037 |
|
|
| 1038 |
return val; |
|
| 1039 |
} |
|
| 1040 |
|
|
| 1041 |
static uint32_t pci_unin_main_readl (void *opaque, target_phys_addr_t addr) |
|
| 1042 |
{
|
|
| 1043 |
PCIBus *s = opaque; |
|
| 1044 |
uint32_t val; |
|
| 1045 |
|
|
| 1046 |
val = pci_data_read(s, addr, 4); |
|
| 1047 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 1048 |
val = bswap32(val); |
|
| 1049 |
#endif |
|
| 1050 |
|
|
| 1051 |
return val; |
|
| 1052 |
} |
|
| 1053 |
|
|
| 1054 |
static CPUWriteMemoryFunc *pci_unin_main_write[] = {
|
|
| 1055 |
&pci_unin_main_writeb, |
|
| 1056 |
&pci_unin_main_writew, |
|
| 1057 |
&pci_unin_main_writel, |
|
| 1058 |
}; |
|
| 1059 |
|
|
| 1060 |
static CPUReadMemoryFunc *pci_unin_main_read[] = {
|
|
| 1061 |
&pci_unin_main_readb, |
|
| 1062 |
&pci_unin_main_readw, |
|
| 1063 |
&pci_unin_main_readl, |
|
| 1064 |
}; |
|
| 1065 |
|
|
| 1066 |
#if 0 |
|
| 1067 |
|
|
| 1068 |
static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr, |
|
| 1069 |
uint32_t val) |
|
| 1070 |
{
|
|
| 1071 |
PCIBus *s = opaque; |
|
| 1072 |
|
|
| 1073 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 1074 |
val = bswap32(val); |
|
| 1075 |
#endif |
|
| 1076 |
s->config_reg = 0x80000000 | (val & ~0x00000001); |
|
| 1077 |
} |
|
| 1078 |
|
|
| 1079 |
static uint32_t pci_unin_config_readl (void *opaque, |
|
| 1080 |
target_phys_addr_t addr) |
|
| 1081 |
{
|
|
| 1082 |
PCIBus *s = opaque; |
|
| 1083 |
uint32_t val; |
|
| 1084 |
|
|
| 1085 |
val = (s->config_reg | 0x00000001) & ~0x80000000; |
|
| 1086 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 1087 |
val = bswap32(val); |
|
| 1088 |
#endif |
|
| 1089 |
|
|
| 1090 |
return val; |
|
| 1091 |
} |
|
| 1092 |
|
|
| 1093 |
static CPUWriteMemoryFunc *pci_unin_config_write[] = {
|
|
| 1094 |
&pci_unin_config_writel, |
|
| 1095 |
&pci_unin_config_writel, |
|
| 1096 |
&pci_unin_config_writel, |
|
| 1097 |
}; |
|
| 1098 |
|
|
| 1099 |
static CPUReadMemoryFunc *pci_unin_config_read[] = {
|
|
| 1100 |
&pci_unin_config_readl, |
|
| 1101 |
&pci_unin_config_readl, |
|
| 1102 |
&pci_unin_config_readl, |
|
| 1103 |
}; |
|
| 1104 |
|
|
| 1105 |
static void pci_unin_writeb (void *opaque, target_phys_addr_t addr, |
|
| 1106 |
uint32_t val) |
|
| 1107 |
{
|
|
| 1108 |
PCIBus *s = opaque; |
|
| 1109 |
pci_data_write(s, addr & 3, val, 1); |
|
| 1110 |
} |
|
| 1111 |
|
|
| 1112 |
static void pci_unin_writew (void *opaque, target_phys_addr_t addr, |
|
| 1113 |
uint32_t val) |
|
| 1114 |
{
|
|
| 1115 |
PCIBus *s = opaque; |
|
| 1116 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 1117 |
val = bswap16(val); |
|
| 1118 |
#endif |
|
| 1119 |
pci_data_write(s, addr & 3, val, 2); |
|
| 1120 |
} |
|
| 1121 |
|
|
| 1122 |
static void pci_unin_writel (void *opaque, target_phys_addr_t addr, |
|
| 1123 |
uint32_t val) |
|
| 1124 |
{
|
|
| 1125 |
PCIBus *s = opaque; |
|
| 1126 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 1127 |
val = bswap32(val); |
|
| 1128 |
#endif |
|
| 1129 |
pci_data_write(s, addr & 3, val, 4); |
|
| 1130 |
} |
|
| 1131 |
|
|
| 1132 |
static uint32_t pci_unin_readb (void *opaque, target_phys_addr_t addr) |
|
| 1133 |
{
|
|
| 1134 |
PCIBus *s = opaque; |
|
| 1135 |
uint32_t val; |
|
| 1136 |
|
|
| 1137 |
val = pci_data_read(s, addr & 3, 1); |
|
| 1138 |
|
|
| 1139 |
return val; |
|
| 1140 |
} |
|
| 1141 |
|
|
| 1142 |
static uint32_t pci_unin_readw (void *opaque, target_phys_addr_t addr) |
|
| 1143 |
{
|
|
| 1144 |
PCIBus *s = opaque; |
|
| 1145 |
uint32_t val; |
|
| 1146 |
|
|
| 1147 |
val = pci_data_read(s, addr & 3, 2); |
|
| 1148 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 1149 |
val = bswap16(val); |
|
| 1150 |
#endif |
|
| 1151 |
|
|
| 1152 |
return val; |
|
| 1153 |
} |
|
| 1154 |
|
|
| 1155 |
static uint32_t pci_unin_readl (void *opaque, target_phys_addr_t addr) |
|
| 1156 |
{
|
|
| 1157 |
PCIBus *s = opaque; |
|
Also available in: Unified diff