root / hw / versatile_pci.c @ 5041fccd
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1 | 5fafdf24 | ths | /*
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2 | 502a5395 | pbrook | * ARM Versatile/PB PCI host controller
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3 | 502a5395 | pbrook | *
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4 | 0027b06d | Paul Brook | * Copyright (c) 2006-2009 CodeSourcery.
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5 | 502a5395 | pbrook | * Written by Paul Brook
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6 | 502a5395 | pbrook | *
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7 | 502a5395 | pbrook | * This code is licenced under the LGPL.
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8 | 502a5395 | pbrook | */
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9 | 502a5395 | pbrook | |
10 | 0027b06d | Paul Brook | #include "sysbus.h" |
11 | 87ecb68b | pbrook | #include "pci.h" |
12 | 0027b06d | Paul Brook | |
13 | 0027b06d | Paul Brook | typedef struct { |
14 | 0027b06d | Paul Brook | SysBusDevice busdev; |
15 | 0027b06d | Paul Brook | qemu_irq irq[4];
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16 | 0027b06d | Paul Brook | int realview;
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17 | 0027b06d | Paul Brook | int mem_config;
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18 | 0027b06d | Paul Brook | } PCIVPBState; |
19 | 502a5395 | pbrook | |
20 | c227f099 | Anthony Liguori | static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr) |
21 | 502a5395 | pbrook | { |
22 | 80b3ada7 | pbrook | return addr & 0xffffff; |
23 | 502a5395 | pbrook | } |
24 | 502a5395 | pbrook | |
25 | c227f099 | Anthony Liguori | static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr, |
26 | 502a5395 | pbrook | uint32_t val) |
27 | 502a5395 | pbrook | { |
28 | 502a5395 | pbrook | pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1);
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29 | 502a5395 | pbrook | } |
30 | 502a5395 | pbrook | |
31 | c227f099 | Anthony Liguori | static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr, |
32 | 502a5395 | pbrook | uint32_t val) |
33 | 502a5395 | pbrook | { |
34 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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35 | 502a5395 | pbrook | val = bswap16(val); |
36 | 502a5395 | pbrook | #endif
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37 | 502a5395 | pbrook | pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2);
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38 | 502a5395 | pbrook | } |
39 | 502a5395 | pbrook | |
40 | c227f099 | Anthony Liguori | static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr, |
41 | 502a5395 | pbrook | uint32_t val) |
42 | 502a5395 | pbrook | { |
43 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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44 | 502a5395 | pbrook | val = bswap32(val); |
45 | 502a5395 | pbrook | #endif
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46 | 502a5395 | pbrook | pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4);
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47 | 502a5395 | pbrook | } |
48 | 502a5395 | pbrook | |
49 | c227f099 | Anthony Liguori | static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr) |
50 | 502a5395 | pbrook | { |
51 | 502a5395 | pbrook | uint32_t val; |
52 | 502a5395 | pbrook | val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1);
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53 | 502a5395 | pbrook | return val;
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54 | 502a5395 | pbrook | } |
55 | 502a5395 | pbrook | |
56 | c227f099 | Anthony Liguori | static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr) |
57 | 502a5395 | pbrook | { |
58 | 502a5395 | pbrook | uint32_t val; |
59 | 502a5395 | pbrook | val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2);
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60 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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61 | 502a5395 | pbrook | val = bswap16(val); |
62 | 502a5395 | pbrook | #endif
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63 | 502a5395 | pbrook | return val;
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64 | 502a5395 | pbrook | } |
65 | 502a5395 | pbrook | |
66 | c227f099 | Anthony Liguori | static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr) |
67 | 502a5395 | pbrook | { |
68 | 502a5395 | pbrook | uint32_t val; |
69 | 502a5395 | pbrook | val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
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70 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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71 | 502a5395 | pbrook | val = bswap32(val); |
72 | 502a5395 | pbrook | #endif
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73 | 502a5395 | pbrook | return val;
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74 | 502a5395 | pbrook | } |
75 | 502a5395 | pbrook | |
76 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pci_vpb_config_write[] = { |
77 | 502a5395 | pbrook | &pci_vpb_config_writeb, |
78 | 502a5395 | pbrook | &pci_vpb_config_writew, |
79 | 502a5395 | pbrook | &pci_vpb_config_writel, |
80 | 502a5395 | pbrook | }; |
81 | 502a5395 | pbrook | |
82 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pci_vpb_config_read[] = { |
83 | 502a5395 | pbrook | &pci_vpb_config_readb, |
84 | 502a5395 | pbrook | &pci_vpb_config_readw, |
85 | 502a5395 | pbrook | &pci_vpb_config_readl, |
86 | 502a5395 | pbrook | }; |
87 | 502a5395 | pbrook | |
88 | d2b59317 | pbrook | static int pci_vpb_map_irq(PCIDevice *d, int irq_num) |
89 | d2b59317 | pbrook | { |
90 | d2b59317 | pbrook | return irq_num;
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91 | d2b59317 | pbrook | } |
92 | d2b59317 | pbrook | |
93 | 5d4e84c8 | Juan Quintela | static void pci_vpb_set_irq(void *opaque, int irq_num, int level) |
94 | 502a5395 | pbrook | { |
95 | 5d4e84c8 | Juan Quintela | qemu_irq *pic = opaque; |
96 | 5d4e84c8 | Juan Quintela | |
97 | 97aff481 | Paul Brook | qemu_set_irq(pic[irq_num], level); |
98 | 502a5395 | pbrook | } |
99 | 502a5395 | pbrook | |
100 | c227f099 | Anthony Liguori | static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base) |
101 | 502a5395 | pbrook | { |
102 | 0027b06d | Paul Brook | PCIVPBState *s = (PCIVPBState *)dev; |
103 | 0027b06d | Paul Brook | /* Selfconfig area. */
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104 | 0027b06d | Paul Brook | cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config); |
105 | 0027b06d | Paul Brook | /* Normal config area. */
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106 | 0027b06d | Paul Brook | cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config); |
107 | 0027b06d | Paul Brook | |
108 | 0027b06d | Paul Brook | if (s->realview) {
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109 | 0027b06d | Paul Brook | /* IO memory area. */
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110 | 0027b06d | Paul Brook | isa_mmio_init(base + 0x03000000, 0x00100000); |
111 | 0027b06d | Paul Brook | } |
112 | 0027b06d | Paul Brook | } |
113 | 0027b06d | Paul Brook | |
114 | 81a322d4 | Gerd Hoffmann | static int pci_vpb_init(SysBusDevice *dev) |
115 | 0027b06d | Paul Brook | { |
116 | 0027b06d | Paul Brook | PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev); |
117 | 0027b06d | Paul Brook | PCIBus *bus; |
118 | 97aff481 | Paul Brook | int i;
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119 | e69954b9 | pbrook | |
120 | 97aff481 | Paul Brook | for (i = 0; i < 4; i++) { |
121 | 0027b06d | Paul Brook | sysbus_init_irq(dev, &s->irq[i]); |
122 | e69954b9 | pbrook | } |
123 | 02e2da45 | Paul Brook | bus = pci_register_bus(&dev->qdev, "pci",
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124 | 02e2da45 | Paul Brook | pci_vpb_set_irq, pci_vpb_map_irq, s->irq, |
125 | 0027b06d | Paul Brook | 11 << 3, 4); |
126 | 0027b06d | Paul Brook | |
127 | 502a5395 | pbrook | /* ??? Register memory space. */
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128 | 502a5395 | pbrook | |
129 | 1eed09cb | Avi Kivity | s->mem_config = cpu_register_io_memory(pci_vpb_config_read, |
130 | 0027b06d | Paul Brook | pci_vpb_config_write, bus); |
131 | 0027b06d | Paul Brook | sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map);
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132 | e69954b9 | pbrook | |
133 | 0027b06d | Paul Brook | pci_create_simple(bus, -1, "versatile_pci_host"); |
134 | 81a322d4 | Gerd Hoffmann | return 0; |
135 | 0027b06d | Paul Brook | } |
136 | e69954b9 | pbrook | |
137 | 81a322d4 | Gerd Hoffmann | static int pci_realview_init(SysBusDevice *dev) |
138 | 0027b06d | Paul Brook | { |
139 | 0027b06d | Paul Brook | PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev); |
140 | 0027b06d | Paul Brook | s->realview = 1;
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141 | 81a322d4 | Gerd Hoffmann | return pci_vpb_init(dev);
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142 | 0027b06d | Paul Brook | } |
143 | 502a5395 | pbrook | |
144 | 81a322d4 | Gerd Hoffmann | static int versatile_pci_host_init(PCIDevice *d) |
145 | 0027b06d | Paul Brook | { |
146 | deb54399 | aliguori | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_XILINX); |
147 | e69954b9 | pbrook | /* Both boards have the same device ID. Oh well. */
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148 | a770dc7e | aliguori | pci_config_set_device_id(d->config, PCI_DEVICE_ID_XILINX_XC2VP30); |
149 | 502a5395 | pbrook | d->config[0x04] = 0x00; |
150 | 502a5395 | pbrook | d->config[0x05] = 0x00; |
151 | 502a5395 | pbrook | d->config[0x06] = 0x20; |
152 | 502a5395 | pbrook | d->config[0x07] = 0x02; |
153 | 502a5395 | pbrook | d->config[0x08] = 0x00; // revision |
154 | 502a5395 | pbrook | d->config[0x09] = 0x00; // programming i/f |
155 | 173a543b | blueswir1 | pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_CO); |
156 | 502a5395 | pbrook | d->config[0x0D] = 0x10; // latency_timer |
157 | 81a322d4 | Gerd Hoffmann | return 0; |
158 | 0027b06d | Paul Brook | } |
159 | 502a5395 | pbrook | |
160 | 0aab0d3a | Gerd Hoffmann | static PCIDeviceInfo versatile_pci_host_info = {
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161 | 0aab0d3a | Gerd Hoffmann | .qdev.name = "versatile_pci_host",
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162 | 0aab0d3a | Gerd Hoffmann | .qdev.size = sizeof(PCIDevice),
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163 | 0aab0d3a | Gerd Hoffmann | .init = versatile_pci_host_init, |
164 | 0aab0d3a | Gerd Hoffmann | }; |
165 | 0aab0d3a | Gerd Hoffmann | |
166 | 0027b06d | Paul Brook | static void versatile_pci_register_devices(void) |
167 | 0027b06d | Paul Brook | { |
168 | 0027b06d | Paul Brook | sysbus_register_dev("versatile_pci", sizeof(PCIVPBState), pci_vpb_init); |
169 | 0027b06d | Paul Brook | sysbus_register_dev("realview_pci", sizeof(PCIVPBState), |
170 | 0027b06d | Paul Brook | pci_realview_init); |
171 | 0aab0d3a | Gerd Hoffmann | pci_qdev_register(&versatile_pci_host_info); |
172 | 502a5395 | pbrook | } |
173 | 0027b06d | Paul Brook | |
174 | 0027b06d | Paul Brook | device_init(versatile_pci_register_devices) |