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1 | 9dd986cc | Richard W.M. Jones | /*
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2 | 9dd986cc | Richard W.M. Jones | * Virtual hardware watchdog.
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3 | 9dd986cc | Richard W.M. Jones | *
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4 | 9dd986cc | Richard W.M. Jones | * Copyright (C) 2009 Red Hat Inc.
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5 | 9dd986cc | Richard W.M. Jones | *
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6 | 9dd986cc | Richard W.M. Jones | * This program is free software; you can redistribute it and/or
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7 | 9dd986cc | Richard W.M. Jones | * modify it under the terms of the GNU General Public License
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8 | 9dd986cc | Richard W.M. Jones | * as published by the Free Software Foundation; either version 2
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9 | 9dd986cc | Richard W.M. Jones | * of the License, or (at your option) any later version.
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10 | 9dd986cc | Richard W.M. Jones | *
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11 | 9dd986cc | Richard W.M. Jones | * This program is distributed in the hope that it will be useful,
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12 | 9dd986cc | Richard W.M. Jones | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 9dd986cc | Richard W.M. Jones | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | 9dd986cc | Richard W.M. Jones | * GNU General Public License for more details.
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15 | 9dd986cc | Richard W.M. Jones | *
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16 | 9dd986cc | Richard W.M. Jones | * You should have received a copy of the GNU General Public License
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17 | 8167ee88 | Blue Swirl | * along with this program; if not, see <http://www.gnu.org/licenses/>.
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18 | 9dd986cc | Richard W.M. Jones | *
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19 | 9dd986cc | Richard W.M. Jones | * By Richard W.M. Jones (rjones@redhat.com).
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20 | 9dd986cc | Richard W.M. Jones | */
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21 | 9dd986cc | Richard W.M. Jones | |
22 | 9dd986cc | Richard W.M. Jones | #include <inttypes.h> |
23 | 9dd986cc | Richard W.M. Jones | |
24 | 9dd986cc | Richard W.M. Jones | #include "qemu-common.h" |
25 | 9dd986cc | Richard W.M. Jones | #include "qemu-timer.h" |
26 | 9dd986cc | Richard W.M. Jones | #include "watchdog.h" |
27 | 9dd986cc | Richard W.M. Jones | #include "hw.h" |
28 | 9dd986cc | Richard W.M. Jones | #include "pci.h" |
29 | 9dd986cc | Richard W.M. Jones | |
30 | 9dd986cc | Richard W.M. Jones | /*#define I6300ESB_DEBUG 1*/
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31 | 9dd986cc | Richard W.M. Jones | |
32 | 9dd986cc | Richard W.M. Jones | #ifdef I6300ESB_DEBUG
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33 | 9dd986cc | Richard W.M. Jones | #define i6300esb_debug(fs,...) \
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34 | 9dd986cc | Richard W.M. Jones | fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__) |
35 | 9dd986cc | Richard W.M. Jones | #else
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36 | 9dd986cc | Richard W.M. Jones | #define i6300esb_debug(fs,...)
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37 | 9dd986cc | Richard W.M. Jones | #endif
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38 | 9dd986cc | Richard W.M. Jones | |
39 | 9dd986cc | Richard W.M. Jones | #ifndef PCI_DEVICE_ID_INTEL_ESB_9
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40 | 9dd986cc | Richard W.M. Jones | #define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab |
41 | 9dd986cc | Richard W.M. Jones | #endif
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42 | 9dd986cc | Richard W.M. Jones | |
43 | 9dd986cc | Richard W.M. Jones | /* PCI configuration registers */
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44 | 9dd986cc | Richard W.M. Jones | #define ESB_CONFIG_REG 0x60 /* Config register */ |
45 | 9dd986cc | Richard W.M. Jones | #define ESB_LOCK_REG 0x68 /* WDT lock register */ |
46 | 9dd986cc | Richard W.M. Jones | |
47 | 9dd986cc | Richard W.M. Jones | /* Memory mapped registers (offset from base address) */
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48 | 9dd986cc | Richard W.M. Jones | #define ESB_TIMER1_REG 0x00 /* Timer1 value after each reset */ |
49 | 9dd986cc | Richard W.M. Jones | #define ESB_TIMER2_REG 0x04 /* Timer2 value after each reset */ |
50 | 9dd986cc | Richard W.M. Jones | #define ESB_GINTSR_REG 0x08 /* General Interrupt Status Register */ |
51 | 9dd986cc | Richard W.M. Jones | #define ESB_RELOAD_REG 0x0c /* Reload register */ |
52 | 9dd986cc | Richard W.M. Jones | |
53 | 9dd986cc | Richard W.M. Jones | /* Lock register bits */
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54 | 9dd986cc | Richard W.M. Jones | #define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */ |
55 | 9dd986cc | Richard W.M. Jones | #define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */ |
56 | 9dd986cc | Richard W.M. Jones | #define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */ |
57 | 9dd986cc | Richard W.M. Jones | |
58 | 9dd986cc | Richard W.M. Jones | /* Config register bits */
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59 | 9dd986cc | Richard W.M. Jones | #define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */ |
60 | 9dd986cc | Richard W.M. Jones | #define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */ |
61 | 9dd986cc | Richard W.M. Jones | #define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */ |
62 | 9dd986cc | Richard W.M. Jones | |
63 | 9dd986cc | Richard W.M. Jones | /* Reload register bits */
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64 | 9dd986cc | Richard W.M. Jones | #define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */ |
65 | 9dd986cc | Richard W.M. Jones | |
66 | 9dd986cc | Richard W.M. Jones | /* Magic constants */
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67 | 9dd986cc | Richard W.M. Jones | #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */ |
68 | 9dd986cc | Richard W.M. Jones | #define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */ |
69 | 9dd986cc | Richard W.M. Jones | |
70 | 9dd986cc | Richard W.M. Jones | /* Device state. */
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71 | 9dd986cc | Richard W.M. Jones | struct I6300State {
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72 | 9d472d51 | Markus Armbruster | PCIDevice dev; |
73 | 9dd986cc | Richard W.M. Jones | |
74 | 9dd986cc | Richard W.M. Jones | int reboot_enabled; /* "Reboot" on timer expiry. The real action |
75 | 9dd986cc | Richard W.M. Jones | * performed depends on the -watchdog-action
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76 | 9dd986cc | Richard W.M. Jones | * param passed on QEMU command line.
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77 | 9dd986cc | Richard W.M. Jones | */
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78 | 9dd986cc | Richard W.M. Jones | int clock_scale; /* Clock scale. */ |
79 | 9dd986cc | Richard W.M. Jones | #define CLOCK_SCALE_1KHZ 0 |
80 | 9dd986cc | Richard W.M. Jones | #define CLOCK_SCALE_1MHZ 1 |
81 | 9dd986cc | Richard W.M. Jones | |
82 | 9dd986cc | Richard W.M. Jones | int int_type; /* Interrupt type generated. */ |
83 | 9dd986cc | Richard W.M. Jones | #define INT_TYPE_IRQ 0 /* APIC 1, INT 10 */ |
84 | 9dd986cc | Richard W.M. Jones | #define INT_TYPE_SMI 2 |
85 | 9dd986cc | Richard W.M. Jones | #define INT_TYPE_DISABLED 3 |
86 | 9dd986cc | Richard W.M. Jones | |
87 | 9dd986cc | Richard W.M. Jones | int free_run; /* If true, reload timer on expiry. */ |
88 | 9dd986cc | Richard W.M. Jones | int locked; /* If true, enabled field cannot be changed. */ |
89 | 9dd986cc | Richard W.M. Jones | int enabled; /* If true, watchdog is enabled. */ |
90 | 9dd986cc | Richard W.M. Jones | |
91 | 9dd986cc | Richard W.M. Jones | QEMUTimer *timer; /* The actual watchdog timer. */
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92 | 9dd986cc | Richard W.M. Jones | |
93 | 9dd986cc | Richard W.M. Jones | uint32_t timer1_preload; /* Values preloaded into timer1, timer2. */
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94 | 9dd986cc | Richard W.M. Jones | uint32_t timer2_preload; |
95 | 9dd986cc | Richard W.M. Jones | int stage; /* Stage (1 or 2). */ |
96 | 9dd986cc | Richard W.M. Jones | |
97 | 9dd986cc | Richard W.M. Jones | int unlock_state; /* Guest writes 0x80, 0x86 to unlock the |
98 | 9dd986cc | Richard W.M. Jones | * registers, and we transition through
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99 | 9dd986cc | Richard W.M. Jones | * states 0 -> 1 -> 2 when this happens.
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100 | 9dd986cc | Richard W.M. Jones | */
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101 | 9dd986cc | Richard W.M. Jones | |
102 | 9dd986cc | Richard W.M. Jones | int previous_reboot_flag; /* If the watchdog caused the previous |
103 | 9dd986cc | Richard W.M. Jones | * reboot, this flag will be set.
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104 | 9dd986cc | Richard W.M. Jones | */
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105 | 9dd986cc | Richard W.M. Jones | }; |
106 | 9dd986cc | Richard W.M. Jones | |
107 | 9dd986cc | Richard W.M. Jones | typedef struct I6300State I6300State; |
108 | 9dd986cc | Richard W.M. Jones | |
109 | 9dd986cc | Richard W.M. Jones | /* This function is called when the watchdog has either been enabled
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110 | 9dd986cc | Richard W.M. Jones | * (hence it starts counting down) or has been keep-alived.
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111 | 9dd986cc | Richard W.M. Jones | */
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112 | 9dd986cc | Richard W.M. Jones | static void i6300esb_restart_timer(I6300State *d, int stage) |
113 | 9dd986cc | Richard W.M. Jones | { |
114 | 9dd986cc | Richard W.M. Jones | int64_t timeout; |
115 | 9dd986cc | Richard W.M. Jones | |
116 | 9dd986cc | Richard W.M. Jones | if (!d->enabled)
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117 | 9dd986cc | Richard W.M. Jones | return;
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118 | 9dd986cc | Richard W.M. Jones | |
119 | 9dd986cc | Richard W.M. Jones | d->stage = stage; |
120 | 9dd986cc | Richard W.M. Jones | |
121 | 9dd986cc | Richard W.M. Jones | if (d->stage <= 1) |
122 | 9dd986cc | Richard W.M. Jones | timeout = d->timer1_preload; |
123 | 9dd986cc | Richard W.M. Jones | else
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124 | 9dd986cc | Richard W.M. Jones | timeout = d->timer2_preload; |
125 | 9dd986cc | Richard W.M. Jones | |
126 | 9dd986cc | Richard W.M. Jones | if (d->clock_scale == CLOCK_SCALE_1KHZ)
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127 | 9dd986cc | Richard W.M. Jones | timeout <<= 15;
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128 | 9dd986cc | Richard W.M. Jones | else
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129 | 9dd986cc | Richard W.M. Jones | timeout <<= 5;
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130 | 9dd986cc | Richard W.M. Jones | |
131 | 9dd986cc | Richard W.M. Jones | /* Get the timeout in units of ticks_per_sec. */
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132 | 6ee093c9 | Juan Quintela | timeout = get_ticks_per_sec() * timeout / 33000000;
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133 | 9dd986cc | Richard W.M. Jones | |
134 | 9dd986cc | Richard W.M. Jones | i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout); |
135 | 9dd986cc | Richard W.M. Jones | |
136 | 9dd986cc | Richard W.M. Jones | qemu_mod_timer(d->timer, qemu_get_clock(vm_clock) + timeout); |
137 | 9dd986cc | Richard W.M. Jones | } |
138 | 9dd986cc | Richard W.M. Jones | |
139 | 9dd986cc | Richard W.M. Jones | /* This is called when the guest disables the watchdog. */
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140 | 9dd986cc | Richard W.M. Jones | static void i6300esb_disable_timer(I6300State *d) |
141 | 9dd986cc | Richard W.M. Jones | { |
142 | 9dd986cc | Richard W.M. Jones | i6300esb_debug("timer disabled\n");
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143 | 9dd986cc | Richard W.M. Jones | |
144 | 9dd986cc | Richard W.M. Jones | qemu_del_timer(d->timer); |
145 | 9dd986cc | Richard W.M. Jones | } |
146 | 9dd986cc | Richard W.M. Jones | |
147 | 9dd986cc | Richard W.M. Jones | static void i6300esb_reset(I6300State *d) |
148 | 9dd986cc | Richard W.M. Jones | { |
149 | 9dd986cc | Richard W.M. Jones | /* XXX We should probably reset other parts of the state here,
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150 | 9dd986cc | Richard W.M. Jones | * but we should also reset our state on general machine reset
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151 | 9dd986cc | Richard W.M. Jones | * too. For now just disable the timer so it doesn't fire
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152 | 9dd986cc | Richard W.M. Jones | * again after the reboot.
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153 | 9dd986cc | Richard W.M. Jones | */
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154 | 9dd986cc | Richard W.M. Jones | i6300esb_disable_timer(d); |
155 | 9dd986cc | Richard W.M. Jones | } |
156 | 9dd986cc | Richard W.M. Jones | |
157 | 9dd986cc | Richard W.M. Jones | /* This function is called when the watchdog expires. Note that
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158 | 9dd986cc | Richard W.M. Jones | * the hardware has two timers, and so expiry happens in two stages.
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159 | 9dd986cc | Richard W.M. Jones | * If d->stage == 1 then we perform the first stage action (usually,
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160 | 9dd986cc | Richard W.M. Jones | * sending an interrupt) and then restart the timer again for the
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161 | 9dd986cc | Richard W.M. Jones | * second stage. If the second stage expires then the watchdog
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162 | 9dd986cc | Richard W.M. Jones | * really has run out.
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163 | 9dd986cc | Richard W.M. Jones | */
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164 | 9dd986cc | Richard W.M. Jones | static void i6300esb_timer_expired(void *vp) |
165 | 9dd986cc | Richard W.M. Jones | { |
166 | 9dd986cc | Richard W.M. Jones | I6300State *d = (I6300State *) vp; |
167 | 9dd986cc | Richard W.M. Jones | |
168 | 9dd986cc | Richard W.M. Jones | i6300esb_debug("stage %d\n", d->stage);
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169 | 9dd986cc | Richard W.M. Jones | |
170 | 9dd986cc | Richard W.M. Jones | if (d->stage == 1) { |
171 | 9dd986cc | Richard W.M. Jones | /* What to do at the end of stage 1? */
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172 | 9dd986cc | Richard W.M. Jones | switch (d->int_type) {
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173 | 9dd986cc | Richard W.M. Jones | case INT_TYPE_IRQ:
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174 | 9dd986cc | Richard W.M. Jones | fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
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175 | 9dd986cc | Richard W.M. Jones | break;
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176 | 9dd986cc | Richard W.M. Jones | case INT_TYPE_SMI:
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177 | 9dd986cc | Richard W.M. Jones | fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
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178 | 9dd986cc | Richard W.M. Jones | break;
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179 | 9dd986cc | Richard W.M. Jones | } |
180 | 9dd986cc | Richard W.M. Jones | |
181 | 9dd986cc | Richard W.M. Jones | /* Start the second stage. */
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182 | 9dd986cc | Richard W.M. Jones | i6300esb_restart_timer(d, 2);
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183 | 9dd986cc | Richard W.M. Jones | } else {
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184 | 9dd986cc | Richard W.M. Jones | /* Second stage expired, reboot for real. */
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185 | 9dd986cc | Richard W.M. Jones | if (d->reboot_enabled) {
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186 | 9dd986cc | Richard W.M. Jones | d->previous_reboot_flag = 1;
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187 | 9dd986cc | Richard W.M. Jones | watchdog_perform_action(); /* This reboots, exits, etc */
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188 | 9dd986cc | Richard W.M. Jones | i6300esb_reset(d); |
189 | 9dd986cc | Richard W.M. Jones | } |
190 | 9dd986cc | Richard W.M. Jones | |
191 | 9dd986cc | Richard W.M. Jones | /* In "free running mode" we start stage 1 again. */
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192 | 9dd986cc | Richard W.M. Jones | if (d->free_run)
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193 | 9dd986cc | Richard W.M. Jones | i6300esb_restart_timer(d, 1);
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194 | 9dd986cc | Richard W.M. Jones | } |
195 | 9dd986cc | Richard W.M. Jones | } |
196 | 9dd986cc | Richard W.M. Jones | |
197 | 9dd986cc | Richard W.M. Jones | static void i6300esb_config_write(PCIDevice *dev, uint32_t addr, |
198 | 9dd986cc | Richard W.M. Jones | uint32_t data, int len)
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199 | 9dd986cc | Richard W.M. Jones | { |
200 | d03f09cc | Markus Armbruster | I6300State *d = DO_UPCAST(I6300State, dev, dev); |
201 | 9dd986cc | Richard W.M. Jones | int old;
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202 | 9dd986cc | Richard W.M. Jones | |
203 | 9dd986cc | Richard W.M. Jones | i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);
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204 | 9dd986cc | Richard W.M. Jones | |
205 | 9dd986cc | Richard W.M. Jones | if (addr == ESB_CONFIG_REG && len == 2) { |
206 | 9dd986cc | Richard W.M. Jones | d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
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207 | 9dd986cc | Richard W.M. Jones | d->clock_scale = |
208 | 9dd986cc | Richard W.M. Jones | (data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
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209 | 9dd986cc | Richard W.M. Jones | d->int_type = (data & ESB_WDT_INTTYPE); |
210 | 9dd986cc | Richard W.M. Jones | } else if (addr == ESB_LOCK_REG && len == 1) { |
211 | 9dd986cc | Richard W.M. Jones | if (!d->locked) {
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212 | 9dd986cc | Richard W.M. Jones | d->locked = (data & ESB_WDT_LOCK) != 0;
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213 | 9dd986cc | Richard W.M. Jones | d->free_run = (data & ESB_WDT_FUNC) != 0;
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214 | 9dd986cc | Richard W.M. Jones | old = d->enabled; |
215 | 9dd986cc | Richard W.M. Jones | d->enabled = (data & ESB_WDT_ENABLE) != 0;
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216 | 9dd986cc | Richard W.M. Jones | if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */ |
217 | 9dd986cc | Richard W.M. Jones | i6300esb_restart_timer(d, 1);
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218 | 9dd986cc | Richard W.M. Jones | else if (!d->enabled) |
219 | 9dd986cc | Richard W.M. Jones | i6300esb_disable_timer(d); |
220 | 9dd986cc | Richard W.M. Jones | } |
221 | 9dd986cc | Richard W.M. Jones | } else {
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222 | 9dd986cc | Richard W.M. Jones | pci_default_write_config(dev, addr, data, len); |
223 | 9dd986cc | Richard W.M. Jones | } |
224 | 9dd986cc | Richard W.M. Jones | } |
225 | 9dd986cc | Richard W.M. Jones | |
226 | 9dd986cc | Richard W.M. Jones | static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len) |
227 | 9dd986cc | Richard W.M. Jones | { |
228 | d03f09cc | Markus Armbruster | I6300State *d = DO_UPCAST(I6300State, dev, dev); |
229 | 9dd986cc | Richard W.M. Jones | uint32_t data; |
230 | 9dd986cc | Richard W.M. Jones | |
231 | 9dd986cc | Richard W.M. Jones | i6300esb_debug ("addr = %x, len = %d\n", addr, len);
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232 | 9dd986cc | Richard W.M. Jones | |
233 | 9dd986cc | Richard W.M. Jones | if (addr == ESB_CONFIG_REG && len == 2) { |
234 | 9dd986cc | Richard W.M. Jones | data = |
235 | 9dd986cc | Richard W.M. Jones | (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) |
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236 | 9dd986cc | Richard W.M. Jones | (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) |
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237 | 9dd986cc | Richard W.M. Jones | d->int_type; |
238 | 9dd986cc | Richard W.M. Jones | return data;
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239 | 9dd986cc | Richard W.M. Jones | } else if (addr == ESB_LOCK_REG && len == 1) { |
240 | 9dd986cc | Richard W.M. Jones | data = |
241 | 9dd986cc | Richard W.M. Jones | (d->free_run ? ESB_WDT_FUNC : 0) |
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242 | 9dd986cc | Richard W.M. Jones | (d->locked ? ESB_WDT_LOCK : 0) |
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243 | 9dd986cc | Richard W.M. Jones | (d->enabled ? ESB_WDT_ENABLE : 0);
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244 | 9dd986cc | Richard W.M. Jones | return data;
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245 | 9dd986cc | Richard W.M. Jones | } else {
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246 | 9dd986cc | Richard W.M. Jones | return pci_default_read_config(dev, addr, len);
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247 | 9dd986cc | Richard W.M. Jones | } |
248 | 9dd986cc | Richard W.M. Jones | } |
249 | 9dd986cc | Richard W.M. Jones | |
250 | c227f099 | Anthony Liguori | static uint32_t i6300esb_mem_readb(void *vp, target_phys_addr_t addr) |
251 | 9dd986cc | Richard W.M. Jones | { |
252 | 9dd986cc | Richard W.M. Jones | i6300esb_debug ("addr = %x\n", (int) addr); |
253 | 9dd986cc | Richard W.M. Jones | |
254 | 9dd986cc | Richard W.M. Jones | return 0; |
255 | 9dd986cc | Richard W.M. Jones | } |
256 | 9dd986cc | Richard W.M. Jones | |
257 | c227f099 | Anthony Liguori | static uint32_t i6300esb_mem_readw(void *vp, target_phys_addr_t addr) |
258 | 9dd986cc | Richard W.M. Jones | { |
259 | 9dd986cc | Richard W.M. Jones | uint32_t data = 0;
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260 | 9dd986cc | Richard W.M. Jones | I6300State *d = (I6300State *) vp; |
261 | 9dd986cc | Richard W.M. Jones | |
262 | 9dd986cc | Richard W.M. Jones | i6300esb_debug("addr = %x\n", (int) addr); |
263 | 9dd986cc | Richard W.M. Jones | |
264 | 9dd986cc | Richard W.M. Jones | if (addr == 0xc) { |
265 | 9dd986cc | Richard W.M. Jones | /* The previous reboot flag is really bit 9, but there is
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266 | 9dd986cc | Richard W.M. Jones | * a bug in the Linux driver where it thinks it's bit 12.
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267 | 9dd986cc | Richard W.M. Jones | * Set both.
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268 | 9dd986cc | Richard W.M. Jones | */
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269 | 9dd986cc | Richard W.M. Jones | data = d->previous_reboot_flag ? 0x1200 : 0; |
270 | 9dd986cc | Richard W.M. Jones | } |
271 | 9dd986cc | Richard W.M. Jones | |
272 | 9dd986cc | Richard W.M. Jones | return data;
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273 | 9dd986cc | Richard W.M. Jones | } |
274 | 9dd986cc | Richard W.M. Jones | |
275 | c227f099 | Anthony Liguori | static uint32_t i6300esb_mem_readl(void *vp, target_phys_addr_t addr) |
276 | 9dd986cc | Richard W.M. Jones | { |
277 | 9dd986cc | Richard W.M. Jones | i6300esb_debug("addr = %x\n", (int) addr); |
278 | 9dd986cc | Richard W.M. Jones | |
279 | 9dd986cc | Richard W.M. Jones | return 0; |
280 | 9dd986cc | Richard W.M. Jones | } |
281 | 9dd986cc | Richard W.M. Jones | |
282 | c227f099 | Anthony Liguori | static void i6300esb_mem_writeb(void *vp, target_phys_addr_t addr, uint32_t val) |
283 | 9dd986cc | Richard W.M. Jones | { |
284 | 9dd986cc | Richard W.M. Jones | I6300State *d = (I6300State *) vp; |
285 | 9dd986cc | Richard W.M. Jones | |
286 | 9dd986cc | Richard W.M. Jones | i6300esb_debug("addr = %x, val = %x\n", (int) addr, val); |
287 | 9dd986cc | Richard W.M. Jones | |
288 | 9dd986cc | Richard W.M. Jones | if (addr == 0xc && val == 0x80) |
289 | 9dd986cc | Richard W.M. Jones | d->unlock_state = 1;
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290 | 9dd986cc | Richard W.M. Jones | else if (addr == 0xc && val == 0x86 && d->unlock_state == 1) |
291 | 9dd986cc | Richard W.M. Jones | d->unlock_state = 2;
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292 | 9dd986cc | Richard W.M. Jones | } |
293 | 9dd986cc | Richard W.M. Jones | |
294 | c227f099 | Anthony Liguori | static void i6300esb_mem_writew(void *vp, target_phys_addr_t addr, uint32_t val) |
295 | 9dd986cc | Richard W.M. Jones | { |
296 | 9dd986cc | Richard W.M. Jones | I6300State *d = (I6300State *) vp; |
297 | 9dd986cc | Richard W.M. Jones | |
298 | 9dd986cc | Richard W.M. Jones | i6300esb_debug("addr = %x, val = %x\n", (int) addr, val); |
299 | 9dd986cc | Richard W.M. Jones | |
300 | 9dd986cc | Richard W.M. Jones | if (addr == 0xc && val == 0x80) |
301 | 9dd986cc | Richard W.M. Jones | d->unlock_state = 1;
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302 | 9dd986cc | Richard W.M. Jones | else if (addr == 0xc && val == 0x86 && d->unlock_state == 1) |
303 | 9dd986cc | Richard W.M. Jones | d->unlock_state = 2;
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304 | 9dd986cc | Richard W.M. Jones | else {
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305 | 9dd986cc | Richard W.M. Jones | if (d->unlock_state == 2) { |
306 | 9dd986cc | Richard W.M. Jones | if (addr == 0xc) { |
307 | 9dd986cc | Richard W.M. Jones | if ((val & 0x100) != 0) |
308 | 9dd986cc | Richard W.M. Jones | /* This is the "ping" from the userspace watchdog in
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309 | 9dd986cc | Richard W.M. Jones | * the guest ...
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310 | 9dd986cc | Richard W.M. Jones | */
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311 | 9dd986cc | Richard W.M. Jones | i6300esb_restart_timer(d, 1);
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312 | 9dd986cc | Richard W.M. Jones | |
313 | 9dd986cc | Richard W.M. Jones | /* Setting bit 9 resets the previous reboot flag.
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314 | 9dd986cc | Richard W.M. Jones | * There's a bug in the Linux driver where it sets
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315 | 9dd986cc | Richard W.M. Jones | * bit 12 instead.
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316 | 9dd986cc | Richard W.M. Jones | */
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317 | 9dd986cc | Richard W.M. Jones | if ((val & 0x200) != 0 || (val & 0x1000) != 0) { |
318 | 9dd986cc | Richard W.M. Jones | d->previous_reboot_flag = 0;
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319 | 9dd986cc | Richard W.M. Jones | } |
320 | 9dd986cc | Richard W.M. Jones | } |
321 | 9dd986cc | Richard W.M. Jones | |
322 | 9dd986cc | Richard W.M. Jones | d->unlock_state = 0;
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323 | 9dd986cc | Richard W.M. Jones | } |
324 | 9dd986cc | Richard W.M. Jones | } |
325 | 9dd986cc | Richard W.M. Jones | } |
326 | 9dd986cc | Richard W.M. Jones | |
327 | c227f099 | Anthony Liguori | static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val) |
328 | 9dd986cc | Richard W.M. Jones | { |
329 | 9dd986cc | Richard W.M. Jones | I6300State *d = (I6300State *) vp; |
330 | 9dd986cc | Richard W.M. Jones | |
331 | 9dd986cc | Richard W.M. Jones | i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val); |
332 | 9dd986cc | Richard W.M. Jones | |
333 | 9dd986cc | Richard W.M. Jones | if (addr == 0xc && val == 0x80) |
334 | 9dd986cc | Richard W.M. Jones | d->unlock_state = 1;
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335 | 9dd986cc | Richard W.M. Jones | else if (addr == 0xc && val == 0x86 && d->unlock_state == 1) |
336 | 9dd986cc | Richard W.M. Jones | d->unlock_state = 2;
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337 | 9dd986cc | Richard W.M. Jones | else {
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338 | 9dd986cc | Richard W.M. Jones | if (d->unlock_state == 2) { |
339 | 9dd986cc | Richard W.M. Jones | if (addr == 0) |
340 | 9dd986cc | Richard W.M. Jones | d->timer1_preload = val & 0xfffff;
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341 | 9dd986cc | Richard W.M. Jones | else if (addr == 4) |
342 | 9dd986cc | Richard W.M. Jones | d->timer2_preload = val & 0xfffff;
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343 | 9dd986cc | Richard W.M. Jones | |
344 | 9dd986cc | Richard W.M. Jones | d->unlock_state = 0;
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345 | 9dd986cc | Richard W.M. Jones | } |
346 | 9dd986cc | Richard W.M. Jones | } |
347 | 9dd986cc | Richard W.M. Jones | } |
348 | 9dd986cc | Richard W.M. Jones | |
349 | 9dd986cc | Richard W.M. Jones | static void i6300esb_map(PCIDevice *dev, int region_num, |
350 | 9dd986cc | Richard W.M. Jones | uint32_t addr, uint32_t size, int type)
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351 | 9dd986cc | Richard W.M. Jones | { |
352 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mem_read[3] = { |
353 | 9dd986cc | Richard W.M. Jones | i6300esb_mem_readb, |
354 | 9dd986cc | Richard W.M. Jones | i6300esb_mem_readw, |
355 | 9dd986cc | Richard W.M. Jones | i6300esb_mem_readl, |
356 | 9dd986cc | Richard W.M. Jones | }; |
357 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mem_write[3] = { |
358 | 9dd986cc | Richard W.M. Jones | i6300esb_mem_writeb, |
359 | 9dd986cc | Richard W.M. Jones | i6300esb_mem_writew, |
360 | 9dd986cc | Richard W.M. Jones | i6300esb_mem_writel, |
361 | 9dd986cc | Richard W.M. Jones | }; |
362 | d03f09cc | Markus Armbruster | I6300State *d = DO_UPCAST(I6300State, dev, dev); |
363 | 9dd986cc | Richard W.M. Jones | int io_mem;
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364 | 9dd986cc | Richard W.M. Jones | |
365 | 9dd986cc | Richard W.M. Jones | i6300esb_debug("addr = %x, size = %x, type = %d\n", addr, size, type);
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366 | 9dd986cc | Richard W.M. Jones | |
367 | 1eed09cb | Avi Kivity | io_mem = cpu_register_io_memory(mem_read, mem_write, d); |
368 | 9dd986cc | Richard W.M. Jones | cpu_register_physical_memory (addr, 0x10, io_mem);
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369 | 9dd986cc | Richard W.M. Jones | /* qemu_register_coalesced_mmio (addr, 0x10); ? */
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370 | 9dd986cc | Richard W.M. Jones | } |
371 | 9dd986cc | Richard W.M. Jones | |
372 | 9dd986cc | Richard W.M. Jones | static void i6300esb_save(QEMUFile *f, void *vp) |
373 | 9dd986cc | Richard W.M. Jones | { |
374 | 9dd986cc | Richard W.M. Jones | I6300State *d = (I6300State *) vp; |
375 | 9dd986cc | Richard W.M. Jones | |
376 | 9dd986cc | Richard W.M. Jones | pci_device_save(&d->dev, f); |
377 | 9dd986cc | Richard W.M. Jones | qemu_put_be32(f, d->reboot_enabled); |
378 | 9dd986cc | Richard W.M. Jones | qemu_put_be32(f, d->clock_scale); |
379 | 9dd986cc | Richard W.M. Jones | qemu_put_be32(f, d->int_type); |
380 | 9dd986cc | Richard W.M. Jones | qemu_put_be32(f, d->free_run); |
381 | 9dd986cc | Richard W.M. Jones | qemu_put_be32(f, d->locked); |
382 | 9dd986cc | Richard W.M. Jones | qemu_put_be32(f, d->enabled); |
383 | 9dd986cc | Richard W.M. Jones | qemu_put_timer(f, d->timer); |
384 | 9dd986cc | Richard W.M. Jones | qemu_put_be32(f, d->timer1_preload); |
385 | 9dd986cc | Richard W.M. Jones | qemu_put_be32(f, d->timer2_preload); |
386 | 9dd986cc | Richard W.M. Jones | qemu_put_be32(f, d->stage); |
387 | 9dd986cc | Richard W.M. Jones | qemu_put_be32(f, d->unlock_state); |
388 | 9dd986cc | Richard W.M. Jones | qemu_put_be32(f, d->previous_reboot_flag); |
389 | 9dd986cc | Richard W.M. Jones | } |
390 | 9dd986cc | Richard W.M. Jones | |
391 | 9dd986cc | Richard W.M. Jones | static int i6300esb_load(QEMUFile *f, void *vp, int version) |
392 | 9dd986cc | Richard W.M. Jones | { |
393 | 9dd986cc | Richard W.M. Jones | I6300State *d = (I6300State *) vp; |
394 | 9dd986cc | Richard W.M. Jones | |
395 | 9dd986cc | Richard W.M. Jones | if (version != sizeof (I6300State)) |
396 | 9dd986cc | Richard W.M. Jones | return -EINVAL;
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397 | 9dd986cc | Richard W.M. Jones | |
398 | 9dd986cc | Richard W.M. Jones | pci_device_load(&d->dev, f); |
399 | 9dd986cc | Richard W.M. Jones | d->reboot_enabled = qemu_get_be32(f); |
400 | 9dd986cc | Richard W.M. Jones | d->clock_scale = qemu_get_be32(f); |
401 | 9dd986cc | Richard W.M. Jones | d->int_type = qemu_get_be32(f); |
402 | 9dd986cc | Richard W.M. Jones | d->free_run = qemu_get_be32(f); |
403 | 9dd986cc | Richard W.M. Jones | d->locked = qemu_get_be32(f); |
404 | 9dd986cc | Richard W.M. Jones | d->enabled = qemu_get_be32(f); |
405 | 9dd986cc | Richard W.M. Jones | qemu_get_timer(f, d->timer); |
406 | 9dd986cc | Richard W.M. Jones | d->timer1_preload = qemu_get_be32(f); |
407 | 9dd986cc | Richard W.M. Jones | d->timer2_preload = qemu_get_be32(f); |
408 | 9dd986cc | Richard W.M. Jones | d->stage = qemu_get_be32(f); |
409 | 9dd986cc | Richard W.M. Jones | d->unlock_state = qemu_get_be32(f); |
410 | 9dd986cc | Richard W.M. Jones | d->previous_reboot_flag = qemu_get_be32(f); |
411 | 9dd986cc | Richard W.M. Jones | |
412 | 9dd986cc | Richard W.M. Jones | return 0; |
413 | 9dd986cc | Richard W.M. Jones | } |
414 | 9dd986cc | Richard W.M. Jones | |
415 | 81a322d4 | Gerd Hoffmann | static int i6300esb_init(PCIDevice *dev) |
416 | 9dd986cc | Richard W.M. Jones | { |
417 | d03f09cc | Markus Armbruster | I6300State *d = DO_UPCAST(I6300State, dev, dev); |
418 | 9dd986cc | Richard W.M. Jones | uint8_t *pci_conf; |
419 | 9dd986cc | Richard W.M. Jones | |
420 | 9dd986cc | Richard W.M. Jones | d->reboot_enabled = 1;
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421 | 9dd986cc | Richard W.M. Jones | d->clock_scale = CLOCK_SCALE_1KHZ; |
422 | 9dd986cc | Richard W.M. Jones | d->int_type = INT_TYPE_IRQ; |
423 | 9dd986cc | Richard W.M. Jones | d->free_run = 0;
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424 | 9dd986cc | Richard W.M. Jones | d->locked = 0;
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425 | 9dd986cc | Richard W.M. Jones | d->enabled = 0;
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426 | 9dd986cc | Richard W.M. Jones | d->timer = qemu_new_timer(vm_clock, i6300esb_timer_expired, d); |
427 | 9dd986cc | Richard W.M. Jones | d->timer1_preload = 0xfffff;
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428 | 9dd986cc | Richard W.M. Jones | d->timer2_preload = 0xfffff;
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429 | 9dd986cc | Richard W.M. Jones | d->stage = 1;
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430 | 9dd986cc | Richard W.M. Jones | d->unlock_state = 0;
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431 | 9dd986cc | Richard W.M. Jones | d->previous_reboot_flag = 0;
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432 | 9dd986cc | Richard W.M. Jones | |
433 | 9dd986cc | Richard W.M. Jones | pci_conf = d->dev.config; |
434 | 9dd986cc | Richard W.M. Jones | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
435 | 9dd986cc | Richard W.M. Jones | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_ESB_9); |
436 | 9dd986cc | Richard W.M. Jones | pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER); |
437 | 9dd986cc | Richard W.M. Jones | pci_conf[0x0e] = 0x00; |
438 | 9dd986cc | Richard W.M. Jones | |
439 | 28c2c264 | Avi Kivity | pci_register_bar(&d->dev, 0, 0x10, |
440 | 9dd986cc | Richard W.M. Jones | PCI_ADDRESS_SPACE_MEM, i6300esb_map); |
441 | 9dd986cc | Richard W.M. Jones | |
442 | 9dd986cc | Richard W.M. Jones | register_savevm("i6300esb_wdt", -1, sizeof(I6300State), |
443 | 9dd986cc | Richard W.M. Jones | i6300esb_save, i6300esb_load, d); |
444 | 81a322d4 | Gerd Hoffmann | |
445 | 81a322d4 | Gerd Hoffmann | return 0; |
446 | 9dd986cc | Richard W.M. Jones | } |
447 | 9dd986cc | Richard W.M. Jones | |
448 | 9dd986cc | Richard W.M. Jones | static WatchdogTimerModel model = {
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449 | 9dd986cc | Richard W.M. Jones | .wdt_name = "i6300esb",
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450 | 9dd986cc | Richard W.M. Jones | .wdt_description = "Intel 6300ESB",
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451 | 9dd986cc | Richard W.M. Jones | }; |
452 | 9dd986cc | Richard W.M. Jones | |
453 | 09aaa160 | Markus Armbruster | static PCIDeviceInfo i6300esb_info = {
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454 | 09aaa160 | Markus Armbruster | .qdev.name = "i6300esb",
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455 | 09aaa160 | Markus Armbruster | .qdev.size = sizeof(I6300State),
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456 | 09aaa160 | Markus Armbruster | .config_read = i6300esb_config_read, |
457 | 09aaa160 | Markus Armbruster | .config_write = i6300esb_config_write, |
458 | 09aaa160 | Markus Armbruster | .init = i6300esb_init, |
459 | 09aaa160 | Markus Armbruster | }; |
460 | 09aaa160 | Markus Armbruster | |
461 | 09aaa160 | Markus Armbruster | static void i6300esb_register_devices(void) |
462 | 9dd986cc | Richard W.M. Jones | { |
463 | 9dd986cc | Richard W.M. Jones | watchdog_add_model(&model); |
464 | 09aaa160 | Markus Armbruster | pci_qdev_register(&i6300esb_info); |
465 | 9dd986cc | Richard W.M. Jones | } |
466 | 09aaa160 | Markus Armbruster | |
467 | 09aaa160 | Markus Armbruster | device_init(i6300esb_register_devices); |