target-arm: Move call to disas_vfp_insn out of disas_coproc_insn.
Floating point is an extension to the instruction set rather thana coprocessor, so call it directly from the ARM and Thumb decodefunctions.
Signed-off-by: Will Newton <will.newton@linaro.org>...
target-arm: Implement ARMv8 VSEL instruction.
This adds support for the VSEL floating point selection instructionwhich was added in ARMv8.
Signed-off-by: Will Newton <will.newton@linaro.org>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Message-id: 1386158099-9239-3-git-send-email-will.newton@linaro.org...
target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.
This adds support for the ARMv8 floating point VMAXNM and VMINNMinstructions.
Signed-off-by: Will Newton <will.newton@linaro.org>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Message-id: 1386158099-9239-6-git-send-email-will.newton@linaro.org...
target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions.
This adds support for the ARMv8 Advanced SIMD VMAXNM and VMINNMinstructions.
Signed-off-by: Will Newton <will.newton@linaro.org>Message-id: 1386158099-9239-7-git-send-email-will.newton@linaro.org...
target-arm: Don't hardcode KVM target CPU to be A15
Instead of assuming that a KVM target CPU must always be aCortex-A15 and hardcoding this in kvm_arch_init_vcpu(),store the KVM_ARM_TARGET_* value in the ARMCPU class,and use that.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Provide '-cpu host' when running KVM
Implement '-cpu host' for ARM when we're using KVM, broadlyin line with other KVM-supporting architectures.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>...
target-arm: Provide PSCI constants to generic QEMU code
Provide versions of the KVM PSCI constants to non-KVM code;this will allow us to avoid an ifdef in boards which set upa PSCI node in the device tree.
target-arm: Add ARMCPU field for Linux device-tree 'compatible' string
Linux requires device tree CPU nodes to include a 'compatible'string describing the CPU. Add a field in the ARMCPU struct forthis so that boards which construct a device tree can insert...
target-arm: Allow secondary KVM CPUs to be booted via PSCI
New ARM boards are generally expected to boot their secondary CPUsvia the PSCI interface, rather than ad-hoc "loop around in holdingpen code" as hw/arm/boot.c implements. In particular this isnecessary for mach-virt kernels. For KVM we achieve this by creating...
target-arm: Provide mechanism for getting KVM constants even if not CONFIG_KVM
There are a number of places where it would be convenient for ARMcode to have working definitions of KVM constants even in codewhich is compiled with CONFIG_KVM not set. In this situation we...
target-arm: Add CP15 VBAR support
Added Vector Base Address remapping on ARM v7.
Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>[PMM: removed spurious mask of value with 1<<31]Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: sort TCG cpreg list by KVM-style 64 bit ID number
Both KVM and TCG populate the cpreg_list with 64 bit register IDs,but in the TCG side the cpreg_list is sorted using the 32 bit IDversion while in the kvm side the 64 bit ID version is used. This...
target-arm: fix sorting issue of KVM cpreg list
The compare_u64 function was not sorting the KVM cpreg_list in theright way due to the wrong returned value. Since we are comparingtwo 64bit values we can't simply return their difference if thereturned type is int....
Merge remote-tracking branch 'bonzini/configure' into staging
Makefile.target: CONFIG_NO_* variables removed
CONFIG_NO_* variables replaced with the lnot logical function
Signed-off-by: Ákos Kovács <akoskovacs@gmx.com>[PMM: fixed a few CONFIG_NO_* uses that were missed]Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
Merge remote-tracking branch 'rth/tcg-pull' into staging
Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into staging
QOM CPUState refactorings / X86CPU
tcg: Move helper registration into tcg_context_init
No longer needs to be done on a per-target basis.
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg: Remove stray semi-colons from target-*/helper.h
During GEN_HELPER=1, these are actually stray top-level semi-colonswhich are technically invalid ISO C, but GCC accepts as an extension.If we added enough extension markers that we could dare use...
cpu: Drop cpu_model_str from CPU_COMMON
Since this is only read in cpu_copy() and linux-user has a globalcpu_model, drop the field from generic code.
Signed-off-by: Andreas Färber <afaerber@suse.de>
misc: Use new rotate functions
Signed-off-by: Stefan Weil <sw@weilnetz.de>
target-arm: Export cpu_env
The cpu_env tcg variable will be used by both the AArch32 and AArch64handling code. Unstaticify it, so that both sides can make use of it.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: John Rigby <john.rigby@linaro.org>...
target-arm: Fix target_ulong/uint32_t confusions
Correct a few places that were using uint32_t or a 32 bitonly format string to handle something that should be a target_ulong.
target-arm: Pass DisasContext* to gen_set_pc_im()
We want gen_set_pc_im() to work for both AArch64 and AArch32, butto do this we'll need the DisasContext* so we can tell which modewe're in, so pass it in as a parameter.
target-arm: Add new AArch64CPUInfo base class and subclasses
Create a new AArch64CPU class; all 64-bit capable ARMCPUs are subclasses of this. (Currently we only supportone, the "any" CPU used by linux-user.)
target-arm: Disable 32 bit CPUs in 64 bit linux-user builds
If we're building aarch64-linux-user then the 32 bit CPUs areall unwanted, because they can't possibly execute the 64 bitbinaries we will be running; disable them.
target-arm: Prepare translation for AArch64 code
This patch adds all the prerequisites for AArch64 support that didn'tfit into split up patches. It extends important bits in the core cpuheaders to also take AArch64 mode into account.
Add new ARM_TBFLAG_AARCH64_STATE translation buffer flag...
target-arm: Add AArch64 translation stub
We should translate AArch64 mode separately from AArch32 mode. In AArch64 mode,registers look vastly different, instruction encoding is completely different,basically the system turns into a different machine.
So let's do a simple if() in translate.c to decide whether we can handle the...
target-arm: Add AArch64 gdbstub support
We want to be able to debug AArch64 guests. So let's add the respective gdbstub functions and xml descriptions that allow us to do so.
target-arm: Abstract out load/store from a vaddr in AArch32
AArch32 code (ie traditional 32 bit world) expects to beable to pass a vaddr in a TCGv_i32. However when QEMU iscompiled with TARGET_LONG_BITS=32 the TCG load/storefunctions take a TCGv_i64. Abstract out load/store with...
target-arm: Extract the disas struct to a header file
We will need to share the disassembly status struct between AArch32 andAArch64 modes. So put it into a header file that both sides can use.
target-arm: Implement qmp query-cpu-definitions
Libvirt uses this to introspect available CPU models.
Signed-off-by: Cole Robinson <crobinso@redhat.com>Reviewed-by: Andreas Färber <afaerber@suse.de>Message-id: c0bdcd6c7ea6a085a6902ccaa73180fd771c8267.1378303555.git.crobinso@redhat.com...
target-arm: Make '-cpu any' available in linux-user mode only
Make the 'any' CPU for target-arm available only in linux-user mode.The ARM target provides a CPU named "any", which turns on support forall user-level instruction set extensions we know about. This is...
target-arm: Use sextract32() in branch decode
In the decode of ARM B and BL insns, swap the order of the"append 2 implicit zeros to imm24" and the sign extend, anduse the new sextract32() utility function to do the latter.This avoids a direct dependency on the undefined C behaviour...
target-arm: Avoid "1 << 31" undefined behaviour
Avoid the undefined behaviour of "1 << 31" by using 1U to makethe shift be of an unsigned value rather than shifting into thesign bit of a signed integer. For consistency, we make all theCPSR_* constants unsigned, though the only one which triggers...
target-arm: fix ARMv7M stack alignment on reset
When the initial SP is loaded from the vector table on ARMv7M systems the twoleast significant bits are ignored as the stack is always aligned at a four byteboundary (see ARM DDI 0403C, B1.4.1 and B1.5.5). So far QEMU did not ignore...
Merge remote-tracking branch 'mjt/trivial-patches' into staging
tcg: Change tcg_gen_exit_tb argument to uintptr_t
And update all users.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>
target-arm: Report unimplemented opcodes (LOG_UNIMP)
These unimplemented opcodes are handled like illegal opcodes, butthey are used in existing code. We should at least report when theyare executed.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
aio / timers: Switch entire codebase to the new timer API
This is an autogenerated patch using scripts/switch-timer-api.
Switch the entire code base to using the new timer API.
Note this patch may introduce some line length issues.
Signed-off-by: Alex Bligh <alex@alex.org.uk>...
target-arm: Allow raw_read() and raw_write() to handle 64 bit regs
Extend the raw_read() and raw_write() helper accessors so thatthey can be used for 64 bit registers as well as 32 bit registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>...
target-arm: Support coprocessor registers which do I/O
Add an ARM_CP_IO flag which an ARMCPRegInfo definition can use toindicate that the register's implementation does I/O and thusits accesses need to be surrounded by gen_io_start()/gen_io_end()in order for icount to work. Most notably, cp registers which...
target-arm: Implement the generic timer
The ARMv7 architecture specifies a 'generic timer' which is implementedvia cp15 registers. Newer kernels will prefer to use this rather thana devboard-level timer. Implement the generic timer for TCG; for KVMwe will already use the hardware's virtualized timer for this....
target-arm: Implement 'int' loglevel
The 'int' loglevel for recording interrupts and exceptionsrequires support in the target-specific code. Implementit for ARM. This improves debug logging in some situationsthat were otherwise pretty opaque, such as when we fault...
target-arm: Make IRQ and FIQ gpio lines on the CPU object
Now that ARMCPU is a subclass of DeviceState, we can make theCPU's inbound IRQ and FIQ lines be simply gpio lines, whichmeans we can remove the odd arm_pic shim.
We retain the arm_pic_init_cpu() function as a backwards...
cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"
Commit c643bed99 moved qemu_init_vcpu() calls to common CPUState code.This causes x86 cpu-add to fail with "KVM: setting VAPIC address failed".
The reason for the failure is that CPUClass::kvm_fd is not yet...
misc: Use g_assert_not_reached for code which is expected to be unreachable
The macro g_assert_not_reached is a better self documenting replacementfor assert(0) or assert(false).
Signed-off-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions
This avoids polluting the global namespace with a non-prefixed macro andmakes it obvious in the call sites that we return.
Semi-automatic conversion using, e.g., sed i 's/GET_REGL(/return gdb_get_regl(mem_buf, /g' target*/gdbstub.c...
cpu: Introduce CPUClass::gdb_{read,write}_register()
Completes migration of target-specific code to new target-*/gdbstub.c.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Introduce CPUClass::gdb_core_xml_file for GDB_CORE_XML
Replace the GDB_CORE_XML define in gdbstub.c with a CPUClass field.Use first_cpu for qSupported and qXfer:features:read: for now.Add a stub for xml_builtin.
target-arm: Move cpu_gdb_{read,write}_register()
cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
CPUState::gdb_num_regs replaces num_g_regs.CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS.
Allows building gdb_register_coprocessor() for xtensa, too.
As a side effect this should fix coprocessor register numbering for SMP....
cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook
Change breakpoint_invalidate() argument to CPUState alongside.
Since all targets now assign a softmmu-only field, we can drop helperscpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd()....
exec: Change cpu_memory_rw_debug() argument to CPUState
Propagate X86CPU in kvmvapic for simplicity.
gdbstub: Change gdb_register_coprocessor() argument to CPUState
cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()
Where no extra implementation is needed, fall back to CPUClass::set_pc().
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Prepares for changing cpu_single_step() argument to CPUState.
gdbstub: Change syscall callback argument to CPUState
Callback implementations were specific to arm and m68k, so can easilycast to ARMCPU and M68kCPU respectively.
Prepares for changing GDBState::c_cpu to CPUState.
cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()
This moves setting the Program Counter from gdbstub into target code.Use vaddr type as upper-bound replacement for target_ulong.
target-arm: implement LDA/STL instructions
This adds support for the ARMv8 load acquire/store release instructions.Since qemu does nothing special for memory barriers, these can beemulated like their non-acquire/release counterparts.
Signed-off-by: Mans Rullgard <mans@mansr.com>...
target-arm: explicitly decode SEVL instruction
The ARMv8 SEVL instruction is in the architectural hint space alreadyemulated as nop. This makes the decoding of SEVL explicit for clarity.
Signed-off-by: Mans Rullgard <mans@mansr.com>Message-id: 1370606786-5650-3-git-send-email-mans@mansr.com...
target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup
The if block detecting OMAP/StrongARM modifies the id_cp_reginfo.access fields in place. So there is no need to replicate the callto define_arm_cp_reg(). Dropped, and let the OMAP case fall through...
target-arm/helper.c: Implement MIDR aliases
Unimplemented registers in the cp15, CRn=0, opc1=0, CRm=0 space defaultto aliasing the MIDR register. Set all registers in the space to accessMIDR by default.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>...
target-arm/helper.c: Allow const opaques in arm CP
Allow for defining const opaque data in ARM CP register definitions bysetting .opaque = foo. If non null opaque is passed intodefine_one_arm_cp_reg_with_opaque then that opaque will takeprecedence, otherwise if null opaque is passed, the original opaque...
target-arm: avoid undefined behaviour when writing TTBCR
LPAE CPUs have more potentially valid bits in the TTBCR, and so thesimple masking out of invalid bits is no longer sufficient to obtainthe base address width field of the register, which is what we use to...
target-arm: Avoid g_hash_table_get_keys()
g_hash_table_get_keys() was only introduced in glib 2.14, and we'restill targeting a minimum version of 2.12. Rewrite the offendingcode (introduced in commit 721fae1) to use g_hash_table_foreach()to build the list of keys....
target-arm: add feature flag for ARMv8
Signed-off-by: Mans Rullgard <mans@mansr.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
log: Change log_cpu_state[_mask]() argument to CPUState
Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turncpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is nolonger needed.
Add documentation and make the functions available through qemu/log.h...
cpu: Move reset logging to CPUState
x86 was using additional CPU_DUMP_* flags, so make that configurable inCPUClass::reset_dump_flags.
This adds reset logging for alpha, unicore32 and xtensa.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-arm: Change gen_intermediate_code_internal() argument to ARMCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-user
The functions cpu_clone_regs() and cpu_set_tls() are not purely CPUrelated -- they are specific to the TLS ABI for a a particular OS.Move them into the linux-user/ tree where they belong....
cpu: Drop unnecessary dynamic casts in *_env_get_cpu()
A transition from CPUFooState to FooCPU can be considered safe,just like FooCPU::env access in the opposite direction.The only benefit of the FOO_CPU() casts would be protection againstbogus CPUFooState pointers, but then surrounding code would likely...
memory: add ref/unref calls
Add ref/unref calls at the following places:
- places where memory regions are stashed by a listener and used outside the BQL (including in Xen or KVM).
- memory_region_find callsites
- creation of aliases and containers (only the aliased/contained...
cpu: Change qemu_init_vcpu() argument to CPUState
This allows to move the call into CPUState's realizefn.Therefore move the stub into libqemustub.a.
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()arguments to CPUState.
target-arm: Convert TCG to using (index,value) list for cp migration
Convert the TCG ARM target to using an (index,value) list for migratingcoprocessors. The primary benefit of the (index,value) list is forpassing state between KVM and QEMU, but it works for TCG-to-TCG...
target-arm: Initialize cpreg list from KVM when using KVM
When using KVM, use the kernel's initial state to set up thecpreg list, and sync to and from the kernel when doingmigration.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Reinitialize all KVM VCPU registers on reset
Since the ARM KVM API doesn't include a "reset this VCPU" ioctl, we have to capture the initial values of everyregister it knows about so that we can reset the VCPUby feeding those values back again....
target-arm: Use tuple list to sync cp regs with KVM
Use the tuple list of cp registers for syncing KVM state to QEMU,rather than only syncing a very minimal set by hand.
target-arm: Make LPAE feature imply V7MP
The v7 ARM ARM specifies that the Large Physical AddressExtension requires implementation of the MultiprocessingExtensions, so make our LPAE feature imply V7MP ratherthan specifying both in the A15 CPU initfn....
target-arm: Allow special cpregs to have flags set
Relax the "is this a valid ARMCPRegInfo type value?" check to permit"special" cpregs to have flags other than ARM_CP_SPECIAL set. Atthe moment none of the other flags are relevant for special regs,but the migration related flag we're about to introduce can apply...
target-arm: Add raw_readfn and raw_writefn to ARMCPRegInfo
For reading and writing register values from the kernel for KVM,we need to provide accessor functions which are guaranteed to succeedand don't impose access checks, mask out unwritable bits, etc....
target-arm: mark up cpregs for no-migrate or raw access
Mark up coprocessor register definitions to add raw accessfunctions or mark the register as non-migratable where necessary.
Merge remote-tracking branch 'mjt/trivial-patches-next' into staging
Merge remote-tracking branch 'pmaydell/target-arm.next' into staging
Message-id: 1370268884-25945-1-git-send-email-peter.maydell@linaro.orgSigned-off-by: Anthony Liguori <aliguori@us.ibm.com>
KVM: ARM: Add dummy kvm_arch_init_irq_routing()
The common KVM code insists on calling kvm_arch_init_irq_routing()as soon as it sees kernel header support for it (regardless of whetherQEMU supports it). Provide a dummy function to satisfy this.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>...
Fix rfe instruction
The rfe instruction has been broken since patch5a839c0d54fac9db0516904db873a4fe01f50f4b because of a typo.
Signed-off-by: Peter Chubb <peter.chubb@nicta.com.au>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Remove unnecessary break statements
Fix these warnings from cppcheck:
hw/display/cirrus_vga.c:2603:hw/sd/sd.c:348:hw/timer/exynos4210_mct.c:1033:target-arm/translate.c:9886:target-s390x/mem_helper.c:518:target-unicore32/translate.c:1936: style: Consecutive return, break, continue, goto or throw statements are unnecessary....
target-arm: Remove gen_{ld,st}* definitions
All the uses of the gen_{ld,st}* functions are gone now, so removethe functions themselves.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Remove uses of gen_{ld,st}* from Neon code
target-arm: Remove use of gen_{ld,st}* from ldrex/strex
target-arm: Remove gen_{ld,st}* from basic ARM insns
target-arm: Remove gen_{ld,st}* from Thumb insns
target-arm: Remove gen_{ld,st}* from thumb2 decoder
target-arm: Remove uses of gen_{ld,st}* from iWMMXt code
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Remove gen_ld64() and gen_st64()
gen_ld64() and gen_st64() are used only in one place, so justexpand them out.
target-arm: Don't use TCGv when we mean TCGv_i32
TCGv changes size depending on the compile time value ofTARGET_LONG_BITS. This is useful for generating code for MIPS style"instructions are the same but the register width changes" CPUs, andalso for the generic bits of QEMU which operate on "width of a...
target-arm: Fix incorrect check of kvm_vcpu_ioctl return value
kvm_vcpu_ioctl() returns ETHING on error, not ETHING - correctan incorrect check in kvm_arch_init_vcpu(). This would not havehad any significant ill-effects -- we would just have propagated...
target-arm: Add some missing CPU state fields to VMState
A number of CPU state fields were accidentally omitted fromour migration state: some OMAP specific cp15 registers, andsome related to state for load/store exclusive insns. Add them.
target-arm: Correctly restore FPSCR
Use the helper functions to save and restore the FPSCR, so thatwe correctly propagate rounding mode and flushing behaviour intothe float_status fields. This also allows us to stop saving thevector length/stride fields separately....