Revision 50cfa95c target-cris/translate.c
| b/target-cris/translate.c | ||
|---|---|---|
| 449 | 449 |
tb = dc->tb; |
| 450 | 450 |
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
|
| 451 | 451 |
tcg_gen_goto_tb(n); |
| 452 |
tcg_gen_movi_tl(cpu_T[0], dest); |
|
| 453 |
t_gen_mov_env_TN(pc, cpu_T[0]); |
|
| 452 |
tcg_gen_movi_tl(env_pc, dest); |
|
| 454 | 453 |
tcg_gen_exit_tb((long)tb + n); |
| 455 | 454 |
} else {
|
| 456 |
t_gen_mov_env_TN(pc, cpu_T[0]);
|
|
| 455 |
tcg_gen_mov_tl(env_pc, cpu_T[0]);
|
|
| 457 | 456 |
tcg_gen_exit_tb(0); |
| 458 | 457 |
} |
| 459 | 458 |
} |
| ... | ... | |
| 916 | 915 |
tcg_gen_ext8s_i32(d, s); |
| 917 | 916 |
else if (size == 2) |
| 918 | 917 |
tcg_gen_ext16s_i32(d, s); |
| 918 |
else |
|
| 919 |
tcg_gen_mov_tl(d, s); |
|
| 919 | 920 |
} |
| 920 | 921 |
|
| 921 | 922 |
static inline void t_gen_zext(TCGv d, TCGv s, int size) |
| ... | ... | |
| 925 | 926 |
tcg_gen_andi_i32(d, s, 0xff); |
| 926 | 927 |
else if (size == 2) |
| 927 | 928 |
tcg_gen_andi_i32(d, s, 0xffff); |
| 929 |
else |
|
| 930 |
tcg_gen_mov_tl(d, s); |
|
| 928 | 931 |
} |
| 929 | 932 |
|
| 930 | 933 |
#if DISAS_CRIS |
| ... | ... | |
| 968 | 971 |
static void dec_prep_move_r(DisasContext *dc, int rs, int rd, |
| 969 | 972 |
int size, int s_ext) |
| 970 | 973 |
{
|
| 971 |
t_gen_mov_TN_reg(cpu_T[1], rs); |
|
| 972 | 974 |
if (s_ext) |
| 973 |
t_gen_sext(cpu_T[1], cpu_T[1], size);
|
|
| 975 |
t_gen_sext(cpu_T[1], cpu_R[rs], size);
|
|
| 974 | 976 |
else |
| 975 |
t_gen_zext(cpu_T[1], cpu_T[1], size);
|
|
| 977 |
t_gen_zext(cpu_T[1], cpu_R[rs], size);
|
|
| 976 | 978 |
} |
| 977 | 979 |
|
| 978 | 980 |
/* Prepare T0 and T1 for a register alu operation. |
| ... | ... | |
| 983 | 985 |
{
|
| 984 | 986 |
dec_prep_move_r(dc, rs, rd, size, s_ext); |
| 985 | 987 |
|
| 986 |
t_gen_mov_TN_reg(cpu_T[0], rd); |
|
| 987 | 988 |
if (s_ext) |
| 988 |
t_gen_sext(cpu_T[0], cpu_T[0], size);
|
|
| 989 |
t_gen_sext(cpu_T[0], cpu_R[rd], size);
|
|
| 989 | 990 |
else |
| 990 |
t_gen_zext(cpu_T[0], cpu_T[0], size);
|
|
| 991 |
t_gen_zext(cpu_T[0], cpu_R[rd], size);
|
|
| 991 | 992 |
} |
| 992 | 993 |
|
| 993 | 994 |
/* Prepare T0 and T1 for a memory + alu operation. |
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