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1 | fde7d5bd | ths | /*
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2 | fde7d5bd | ths | * QEMU GT64120 PCI host
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3 | fde7d5bd | ths | *
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4 | 4de9b249 | ths | * Copyright (c) 2006,2007 Aurelien Jarno
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5 | fde7d5bd | ths | *
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6 | fde7d5bd | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | fde7d5bd | ths | * of this software and associated documentation files (the "Software"), to deal
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8 | fde7d5bd | ths | * in the Software without restriction, including without limitation the rights
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9 | fde7d5bd | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | fde7d5bd | ths | * copies of the Software, and to permit persons to whom the Software is
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11 | fde7d5bd | ths | * furnished to do so, subject to the following conditions:
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12 | fde7d5bd | ths | *
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13 | fde7d5bd | ths | * The above copyright notice and this permission notice shall be included in
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14 | fde7d5bd | ths | * all copies or substantial portions of the Software.
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15 | fde7d5bd | ths | *
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16 | fde7d5bd | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | fde7d5bd | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | fde7d5bd | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | fde7d5bd | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | fde7d5bd | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | fde7d5bd | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | fde7d5bd | ths | * THE SOFTWARE.
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23 | fde7d5bd | ths | */
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24 | fde7d5bd | ths | |
25 | fde7d5bd | ths | #include "vl.h" |
26 | fde7d5bd | ths | typedef target_phys_addr_t pci_addr_t;
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27 | fde7d5bd | ths | #include "pci_host.h" |
28 | fde7d5bd | ths | |
29 | fde7d5bd | ths | #define GT_REGS (0x1000 >> 2) |
30 | fde7d5bd | ths | |
31 | fde7d5bd | ths | /* CPU Configuration */
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32 | fde7d5bd | ths | #define GT_CPU (0x000 >> 2) |
33 | fde7d5bd | ths | #define GT_MULTI (0x120 >> 2) |
34 | fde7d5bd | ths | |
35 | fde7d5bd | ths | /* CPU Address Decode */
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36 | fde7d5bd | ths | #define GT_SCS10LD (0x008 >> 2) |
37 | fde7d5bd | ths | #define GT_SCS10HD (0x010 >> 2) |
38 | fde7d5bd | ths | #define GT_SCS32LD (0x018 >> 2) |
39 | fde7d5bd | ths | #define GT_SCS32HD (0x020 >> 2) |
40 | fde7d5bd | ths | #define GT_CS20LD (0x028 >> 2) |
41 | fde7d5bd | ths | #define GT_CS20HD (0x030 >> 2) |
42 | fde7d5bd | ths | #define GT_CS3BOOTLD (0x038 >> 2) |
43 | fde7d5bd | ths | #define GT_CS3BOOTHD (0x040 >> 2) |
44 | fde7d5bd | ths | #define GT_PCI0IOLD (0x048 >> 2) |
45 | fde7d5bd | ths | #define GT_PCI0IOHD (0x050 >> 2) |
46 | fde7d5bd | ths | #define GT_PCI0M0LD (0x058 >> 2) |
47 | fde7d5bd | ths | #define GT_PCI0M0HD (0x060 >> 2) |
48 | fde7d5bd | ths | #define GT_ISD (0x068 >> 2) |
49 | fde7d5bd | ths | |
50 | fde7d5bd | ths | #define GT_PCI0M1LD (0x080 >> 2) |
51 | fde7d5bd | ths | #define GT_PCI0M1HD (0x088 >> 2) |
52 | fde7d5bd | ths | #define GT_PCI1IOLD (0x090 >> 2) |
53 | fde7d5bd | ths | #define GT_PCI1IOHD (0x098 >> 2) |
54 | fde7d5bd | ths | #define GT_PCI1M0LD (0x0a0 >> 2) |
55 | fde7d5bd | ths | #define GT_PCI1M0HD (0x0a8 >> 2) |
56 | fde7d5bd | ths | #define GT_PCI1M1LD (0x0b0 >> 2) |
57 | fde7d5bd | ths | #define GT_PCI1M1HD (0x0b8 >> 2) |
58 | fde7d5bd | ths | #define GT_PCI1M1LD (0x0b0 >> 2) |
59 | fde7d5bd | ths | #define GT_PCI1M1HD (0x0b8 >> 2) |
60 | fde7d5bd | ths | |
61 | fde7d5bd | ths | #define GT_SCS10AR (0x0d0 >> 2) |
62 | fde7d5bd | ths | #define GT_SCS32AR (0x0d8 >> 2) |
63 | fde7d5bd | ths | #define GT_CS20R (0x0e0 >> 2) |
64 | fde7d5bd | ths | #define GT_CS3BOOTR (0x0e8 >> 2) |
65 | fde7d5bd | ths | |
66 | fde7d5bd | ths | #define GT_PCI0IOREMAP (0x0f0 >> 2) |
67 | fde7d5bd | ths | #define GT_PCI0M0REMAP (0x0f8 >> 2) |
68 | fde7d5bd | ths | #define GT_PCI0M1REMAP (0x100 >> 2) |
69 | fde7d5bd | ths | #define GT_PCI1IOREMAP (0x108 >> 2) |
70 | fde7d5bd | ths | #define GT_PCI1M0REMAP (0x110 >> 2) |
71 | fde7d5bd | ths | #define GT_PCI1M1REMAP (0x118 >> 2) |
72 | fde7d5bd | ths | |
73 | fde7d5bd | ths | /* CPU Error Report */
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74 | fde7d5bd | ths | #define GT_CPUERR_ADDRLO (0x070 >> 2) |
75 | fde7d5bd | ths | #define GT_CPUERR_ADDRHI (0x078 >> 2) |
76 | fde7d5bd | ths | #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ |
77 | fde7d5bd | ths | #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ |
78 | fde7d5bd | ths | #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ |
79 | fde7d5bd | ths | |
80 | fde7d5bd | ths | /* CPU Sync Barrier */
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81 | fde7d5bd | ths | #define GT_PCI0SYNC (0x0c0 >> 2) |
82 | fde7d5bd | ths | #define GT_PCI1SYNC (0x0c8 >> 2) |
83 | fde7d5bd | ths | |
84 | fde7d5bd | ths | /* SDRAM and Device Address Decode */
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85 | fde7d5bd | ths | #define GT_SCS0LD (0x400 >> 2) |
86 | fde7d5bd | ths | #define GT_SCS0HD (0x404 >> 2) |
87 | fde7d5bd | ths | #define GT_SCS1LD (0x408 >> 2) |
88 | fde7d5bd | ths | #define GT_SCS1HD (0x40c >> 2) |
89 | fde7d5bd | ths | #define GT_SCS2LD (0x410 >> 2) |
90 | fde7d5bd | ths | #define GT_SCS2HD (0x414 >> 2) |
91 | fde7d5bd | ths | #define GT_SCS3LD (0x418 >> 2) |
92 | fde7d5bd | ths | #define GT_SCS3HD (0x41c >> 2) |
93 | fde7d5bd | ths | #define GT_CS0LD (0x420 >> 2) |
94 | fde7d5bd | ths | #define GT_CS0HD (0x424 >> 2) |
95 | fde7d5bd | ths | #define GT_CS1LD (0x428 >> 2) |
96 | fde7d5bd | ths | #define GT_CS1HD (0x42c >> 2) |
97 | fde7d5bd | ths | #define GT_CS2LD (0x430 >> 2) |
98 | fde7d5bd | ths | #define GT_CS2HD (0x434 >> 2) |
99 | fde7d5bd | ths | #define GT_CS3LD (0x438 >> 2) |
100 | fde7d5bd | ths | #define GT_CS3HD (0x43c >> 2) |
101 | fde7d5bd | ths | #define GT_BOOTLD (0x440 >> 2) |
102 | fde7d5bd | ths | #define GT_BOOTHD (0x444 >> 2) |
103 | fde7d5bd | ths | #define GT_ADERR (0x470 >> 2) |
104 | fde7d5bd | ths | |
105 | fde7d5bd | ths | /* SDRAM Configuration */
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106 | fde7d5bd | ths | #define GT_SDRAM_CFG (0x448 >> 2) |
107 | fde7d5bd | ths | #define GT_SDRAM_OPMODE (0x474 >> 2) |
108 | fde7d5bd | ths | #define GT_SDRAM_BM (0x478 >> 2) |
109 | fde7d5bd | ths | #define GT_SDRAM_ADDRDECODE (0x47c >> 2) |
110 | fde7d5bd | ths | |
111 | fde7d5bd | ths | /* SDRAM Parameters */
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112 | fde7d5bd | ths | #define GT_SDRAM_B0 (0x44c >> 2) |
113 | fde7d5bd | ths | #define GT_SDRAM_B1 (0x450 >> 2) |
114 | fde7d5bd | ths | #define GT_SDRAM_B2 (0x454 >> 2) |
115 | fde7d5bd | ths | #define GT_SDRAM_B3 (0x458 >> 2) |
116 | fde7d5bd | ths | |
117 | fde7d5bd | ths | /* Device Parameters */
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118 | fde7d5bd | ths | #define GT_DEV_B0 (0x45c >> 2) |
119 | fde7d5bd | ths | #define GT_DEV_B1 (0x460 >> 2) |
120 | fde7d5bd | ths | #define GT_DEV_B2 (0x464 >> 2) |
121 | fde7d5bd | ths | #define GT_DEV_B3 (0x468 >> 2) |
122 | fde7d5bd | ths | #define GT_DEV_BOOT (0x46c >> 2) |
123 | fde7d5bd | ths | |
124 | fde7d5bd | ths | /* ECC */
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125 | fde7d5bd | ths | #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ |
126 | fde7d5bd | ths | #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ |
127 | fde7d5bd | ths | #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ |
128 | fde7d5bd | ths | #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ |
129 | fde7d5bd | ths | #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ |
130 | fde7d5bd | ths | |
131 | fde7d5bd | ths | /* DMA Record */
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132 | fde7d5bd | ths | #define GT_DMA0_CNT (0x800 >> 2) |
133 | fde7d5bd | ths | #define GT_DMA1_CNT (0x804 >> 2) |
134 | fde7d5bd | ths | #define GT_DMA2_CNT (0x808 >> 2) |
135 | fde7d5bd | ths | #define GT_DMA3_CNT (0x80c >> 2) |
136 | fde7d5bd | ths | #define GT_DMA0_SA (0x810 >> 2) |
137 | fde7d5bd | ths | #define GT_DMA1_SA (0x814 >> 2) |
138 | fde7d5bd | ths | #define GT_DMA2_SA (0x818 >> 2) |
139 | fde7d5bd | ths | #define GT_DMA3_SA (0x81c >> 2) |
140 | fde7d5bd | ths | #define GT_DMA0_DA (0x820 >> 2) |
141 | fde7d5bd | ths | #define GT_DMA1_DA (0x824 >> 2) |
142 | fde7d5bd | ths | #define GT_DMA2_DA (0x828 >> 2) |
143 | fde7d5bd | ths | #define GT_DMA3_DA (0x82c >> 2) |
144 | fde7d5bd | ths | #define GT_DMA0_NEXT (0x830 >> 2) |
145 | fde7d5bd | ths | #define GT_DMA1_NEXT (0x834 >> 2) |
146 | fde7d5bd | ths | #define GT_DMA2_NEXT (0x838 >> 2) |
147 | fde7d5bd | ths | #define GT_DMA3_NEXT (0x83c >> 2) |
148 | fde7d5bd | ths | #define GT_DMA0_CUR (0x870 >> 2) |
149 | fde7d5bd | ths | #define GT_DMA1_CUR (0x874 >> 2) |
150 | fde7d5bd | ths | #define GT_DMA2_CUR (0x878 >> 2) |
151 | fde7d5bd | ths | #define GT_DMA3_CUR (0x87c >> 2) |
152 | fde7d5bd | ths | |
153 | fde7d5bd | ths | /* DMA Channel Control */
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154 | fde7d5bd | ths | #define GT_DMA0_CTRL (0x840 >> 2) |
155 | fde7d5bd | ths | #define GT_DMA1_CTRL (0x844 >> 2) |
156 | fde7d5bd | ths | #define GT_DMA2_CTRL (0x848 >> 2) |
157 | fde7d5bd | ths | #define GT_DMA3_CTRL (0x84c >> 2) |
158 | fde7d5bd | ths | |
159 | fde7d5bd | ths | /* DMA Arbiter */
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160 | fde7d5bd | ths | #define GT_DMA_ARB (0x860 >> 2) |
161 | fde7d5bd | ths | |
162 | fde7d5bd | ths | /* Timer/Counter */
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163 | fde7d5bd | ths | #define GT_TC0 (0x850 >> 2) |
164 | fde7d5bd | ths | #define GT_TC1 (0x854 >> 2) |
165 | fde7d5bd | ths | #define GT_TC2 (0x858 >> 2) |
166 | fde7d5bd | ths | #define GT_TC3 (0x85c >> 2) |
167 | fde7d5bd | ths | #define GT_TC_CONTROL (0x864 >> 2) |
168 | fde7d5bd | ths | |
169 | fde7d5bd | ths | /* PCI Internal */
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170 | fde7d5bd | ths | #define GT_PCI0_CMD (0xc00 >> 2) |
171 | fde7d5bd | ths | #define GT_PCI0_TOR (0xc04 >> 2) |
172 | fde7d5bd | ths | #define GT_PCI0_BS_SCS10 (0xc08 >> 2) |
173 | fde7d5bd | ths | #define GT_PCI0_BS_SCS32 (0xc0c >> 2) |
174 | fde7d5bd | ths | #define GT_PCI0_BS_CS20 (0xc10 >> 2) |
175 | fde7d5bd | ths | #define GT_PCI0_BS_CS3BT (0xc14 >> 2) |
176 | fde7d5bd | ths | #define GT_PCI1_IACK (0xc30 >> 2) |
177 | fde7d5bd | ths | #define GT_PCI0_IACK (0xc34 >> 2) |
178 | fde7d5bd | ths | #define GT_PCI0_BARE (0xc3c >> 2) |
179 | fde7d5bd | ths | #define GT_PCI0_PREFMBR (0xc40 >> 2) |
180 | fde7d5bd | ths | #define GT_PCI0_SCS10_BAR (0xc48 >> 2) |
181 | fde7d5bd | ths | #define GT_PCI0_SCS32_BAR (0xc4c >> 2) |
182 | fde7d5bd | ths | #define GT_PCI0_CS20_BAR (0xc50 >> 2) |
183 | fde7d5bd | ths | #define GT_PCI0_CS3BT_BAR (0xc54 >> 2) |
184 | fde7d5bd | ths | #define GT_PCI0_SSCS10_BAR (0xc58 >> 2) |
185 | fde7d5bd | ths | #define GT_PCI0_SSCS32_BAR (0xc5c >> 2) |
186 | fde7d5bd | ths | #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) |
187 | fde7d5bd | ths | #define GT_PCI1_CMD (0xc80 >> 2) |
188 | fde7d5bd | ths | #define GT_PCI1_TOR (0xc84 >> 2) |
189 | fde7d5bd | ths | #define GT_PCI1_BS_SCS10 (0xc88 >> 2) |
190 | fde7d5bd | ths | #define GT_PCI1_BS_SCS32 (0xc8c >> 2) |
191 | fde7d5bd | ths | #define GT_PCI1_BS_CS20 (0xc90 >> 2) |
192 | fde7d5bd | ths | #define GT_PCI1_BS_CS3BT (0xc94 >> 2) |
193 | fde7d5bd | ths | #define GT_PCI1_BARE (0xcbc >> 2) |
194 | fde7d5bd | ths | #define GT_PCI1_PREFMBR (0xcc0 >> 2) |
195 | fde7d5bd | ths | #define GT_PCI1_SCS10_BAR (0xcc8 >> 2) |
196 | fde7d5bd | ths | #define GT_PCI1_SCS32_BAR (0xccc >> 2) |
197 | fde7d5bd | ths | #define GT_PCI1_CS20_BAR (0xcd0 >> 2) |
198 | fde7d5bd | ths | #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) |
199 | fde7d5bd | ths | #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) |
200 | fde7d5bd | ths | #define GT_PCI1_SSCS32_BAR (0xcdc >> 2) |
201 | fde7d5bd | ths | #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) |
202 | fde7d5bd | ths | #define GT_PCI1_CFGADDR (0xcf0 >> 2) |
203 | fde7d5bd | ths | #define GT_PCI1_CFGDATA (0xcf4 >> 2) |
204 | fde7d5bd | ths | #define GT_PCI0_CFGADDR (0xcf8 >> 2) |
205 | fde7d5bd | ths | #define GT_PCI0_CFGDATA (0xcfc >> 2) |
206 | fde7d5bd | ths | |
207 | fde7d5bd | ths | /* Interrupts */
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208 | fde7d5bd | ths | #define GT_INTRCAUSE (0xc18 >> 2) |
209 | fde7d5bd | ths | #define GT_INTRMASK (0xc1c >> 2) |
210 | fde7d5bd | ths | #define GT_PCI0_ICMASK (0xc24 >> 2) |
211 | fde7d5bd | ths | #define GT_PCI0_SERR0MASK (0xc28 >> 2) |
212 | fde7d5bd | ths | #define GT_CPU_INTSEL (0xc70 >> 2) |
213 | fde7d5bd | ths | #define GT_PCI0_INTSEL (0xc74 >> 2) |
214 | fde7d5bd | ths | #define GT_HINTRCAUSE (0xc98 >> 2) |
215 | fde7d5bd | ths | #define GT_HINTRMASK (0xc9c >> 2) |
216 | fde7d5bd | ths | #define GT_PCI0_HICMASK (0xca4 >> 2) |
217 | fde7d5bd | ths | #define GT_PCI1_SERR1MASK (0xca8 >> 2) |
218 | fde7d5bd | ths | |
219 | fde7d5bd | ths | |
220 | fde7d5bd | ths | typedef PCIHostState GT64120PCIState;
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221 | fde7d5bd | ths | |
222 | fde7d5bd | ths | typedef struct GT64120State { |
223 | fde7d5bd | ths | GT64120PCIState *pci; |
224 | fde7d5bd | ths | uint32_t regs[GT_REGS]; |
225 | 35f1de31 | ths | target_phys_addr_t PCI0IO_start; |
226 | 35f1de31 | ths | target_phys_addr_t PCI0IO_length; |
227 | fde7d5bd | ths | } GT64120State; |
228 | fde7d5bd | ths | |
229 | fde7d5bd | ths | static void gt64120_pci_mapping(GT64120State *s) |
230 | fde7d5bd | ths | { |
231 | fde7d5bd | ths | /* Update IO mapping */
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232 | 90e950d1 | ths | if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) |
233 | 90e950d1 | ths | { |
234 | 35f1de31 | ths | /* Unmap old IO address */
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235 | 35f1de31 | ths | if (s->PCI0IO_length)
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236 | 35f1de31 | ths | { |
237 | 35f1de31 | ths | cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED); |
238 | 35f1de31 | ths | } |
239 | 35f1de31 | ths | /* Map new IO address */
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240 | 35f1de31 | ths | s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
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241 | 35f1de31 | ths | s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; |
242 | 11f29511 | ths | isa_mem_base = s->PCI0IO_start; |
243 | 35f1de31 | ths | isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length); |
244 | 90e950d1 | ths | } |
245 | fde7d5bd | ths | } |
246 | fde7d5bd | ths | |
247 | fde7d5bd | ths | static void gt64120_writel (void *opaque, target_phys_addr_t addr, |
248 | fde7d5bd | ths | uint32_t val) |
249 | fde7d5bd | ths | { |
250 | fde7d5bd | ths | GT64120State *s = opaque; |
251 | fde7d5bd | ths | uint32_t saddr; |
252 | fde7d5bd | ths | |
253 | 0da75eb1 | ths | #ifdef TARGET_WORDS_BIGENDIAN
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254 | 0da75eb1 | ths | val = bswap32(val); |
255 | 0da75eb1 | ths | #endif
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256 | 0da75eb1 | ths | |
257 | fde7d5bd | ths | saddr = (addr & 0xfff) >> 2; |
258 | fde7d5bd | ths | switch (saddr) {
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259 | 0da75eb1 | ths | |
260 | 0da75eb1 | ths | /* CPU Configuration */
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261 | fde7d5bd | ths | case GT_CPU:
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262 | fde7d5bd | ths | s->regs[GT_CPU] = val; |
263 | fde7d5bd | ths | break;
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264 | fde7d5bd | ths | case GT_MULTI:
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265 | 0da75eb1 | ths | /* Read-only register as only one GT64xxx is present on the CPU bus */
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266 | fde7d5bd | ths | break;
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267 | fde7d5bd | ths | |
268 | fde7d5bd | ths | /* CPU Address Decode */
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269 | fde7d5bd | ths | case GT_PCI0IOLD:
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270 | fde7d5bd | ths | s->regs[GT_PCI0IOLD] = val & 0x00007fff;
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271 | fde7d5bd | ths | s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
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272 | fde7d5bd | ths | gt64120_pci_mapping(s); |
273 | fde7d5bd | ths | break;
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274 | fde7d5bd | ths | case GT_PCI0M0LD:
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275 | fde7d5bd | ths | s->regs[GT_PCI0M0LD] = val & 0x00007fff;
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276 | fde7d5bd | ths | s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
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277 | fde7d5bd | ths | gt64120_pci_mapping(s); |
278 | fde7d5bd | ths | break;
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279 | fde7d5bd | ths | case GT_PCI0M1LD:
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280 | fde7d5bd | ths | s->regs[GT_PCI0M1LD] = val & 0x00007fff;
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281 | fde7d5bd | ths | s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
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282 | fde7d5bd | ths | gt64120_pci_mapping(s); |
283 | fde7d5bd | ths | break;
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284 | fde7d5bd | ths | case GT_PCI1IOLD:
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285 | fde7d5bd | ths | s->regs[GT_PCI1IOLD] = val & 0x00007fff;
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286 | fde7d5bd | ths | s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
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287 | fde7d5bd | ths | gt64120_pci_mapping(s); |
288 | fde7d5bd | ths | break;
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289 | fde7d5bd | ths | case GT_PCI1M0LD:
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290 | fde7d5bd | ths | s->regs[GT_PCI1M0LD] = val & 0x00007fff;
|
291 | fde7d5bd | ths | s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
|
292 | fde7d5bd | ths | gt64120_pci_mapping(s); |
293 | fde7d5bd | ths | break;
|
294 | fde7d5bd | ths | case GT_PCI1M1LD:
|
295 | fde7d5bd | ths | s->regs[GT_PCI1M1LD] = val & 0x00007fff;
|
296 | fde7d5bd | ths | s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
|
297 | fde7d5bd | ths | gt64120_pci_mapping(s); |
298 | fde7d5bd | ths | break;
|
299 | fde7d5bd | ths | case GT_PCI0IOHD:
|
300 | fde7d5bd | ths | case GT_PCI0M0HD:
|
301 | fde7d5bd | ths | case GT_PCI0M1HD:
|
302 | fde7d5bd | ths | case GT_PCI1IOHD:
|
303 | fde7d5bd | ths | case GT_PCI1M0HD:
|
304 | fde7d5bd | ths | case GT_PCI1M1HD:
|
305 | fde7d5bd | ths | s->regs[saddr] = val & 0x0000007f;
|
306 | fde7d5bd | ths | gt64120_pci_mapping(s); |
307 | fde7d5bd | ths | break;
|
308 | fde7d5bd | ths | case GT_PCI0IOREMAP:
|
309 | fde7d5bd | ths | case GT_PCI0M0REMAP:
|
310 | fde7d5bd | ths | case GT_PCI0M1REMAP:
|
311 | fde7d5bd | ths | case GT_PCI1IOREMAP:
|
312 | fde7d5bd | ths | case GT_PCI1M0REMAP:
|
313 | fde7d5bd | ths | case GT_PCI1M1REMAP:
|
314 | fde7d5bd | ths | s->regs[saddr] = val & 0x000007ff;
|
315 | fde7d5bd | ths | gt64120_pci_mapping(s); |
316 | fde7d5bd | ths | break;
|
317 | fde7d5bd | ths | |
318 | fde7d5bd | ths | /* CPU Error Report */
|
319 | fde7d5bd | ths | case GT_CPUERR_ADDRLO:
|
320 | fde7d5bd | ths | case GT_CPUERR_ADDRHI:
|
321 | fde7d5bd | ths | case GT_CPUERR_DATALO:
|
322 | fde7d5bd | ths | case GT_CPUERR_DATAHI:
|
323 | fde7d5bd | ths | case GT_CPUERR_PARITY:
|
324 | 0da75eb1 | ths | /* Read-only registers, do nothing */
|
325 | 0da75eb1 | ths | break;
|
326 | 0da75eb1 | ths | |
327 | 0da75eb1 | ths | /* CPU Sync Barrier */
|
328 | 0da75eb1 | ths | case GT_PCI0SYNC:
|
329 | 0da75eb1 | ths | case GT_PCI1SYNC:
|
330 | 0da75eb1 | ths | /* Read-only registers, do nothing */
|
331 | fde7d5bd | ths | break;
|
332 | fde7d5bd | ths | |
333 | fde7d5bd | ths | /* ECC */
|
334 | fde7d5bd | ths | case GT_ECC_ERRDATALO:
|
335 | fde7d5bd | ths | case GT_ECC_ERRDATAHI:
|
336 | fde7d5bd | ths | case GT_ECC_MEM:
|
337 | fde7d5bd | ths | case GT_ECC_CALC:
|
338 | fde7d5bd | ths | case GT_ECC_ERRADDR:
|
339 | 0da75eb1 | ths | /* Read-only registers, do nothing */
|
340 | fde7d5bd | ths | break;
|
341 | fde7d5bd | ths | |
342 | fde7d5bd | ths | /* PCI Internal */
|
343 | fde7d5bd | ths | case GT_PCI0_CMD:
|
344 | fde7d5bd | ths | case GT_PCI1_CMD:
|
345 | fde7d5bd | ths | s->regs[saddr] = val & 0x0401fc0f;
|
346 | fde7d5bd | ths | break;
|
347 | fde7d5bd | ths | case GT_PCI0_CFGADDR:
|
348 | fde7d5bd | ths | s->pci->config_reg = val & 0x80fffffc;
|
349 | fde7d5bd | ths | break;
|
350 | fde7d5bd | ths | case GT_PCI0_CFGDATA:
|
351 | fde7d5bd | ths | pci_host_data_writel(s->pci, 0, val);
|
352 | fde7d5bd | ths | break;
|
353 | fde7d5bd | ths | |
354 | 0da75eb1 | ths | /* SDRAM Parameters */
|
355 | 0da75eb1 | ths | case GT_SDRAM_B0:
|
356 | 0da75eb1 | ths | case GT_SDRAM_B1:
|
357 | 0da75eb1 | ths | case GT_SDRAM_B2:
|
358 | 0da75eb1 | ths | case GT_SDRAM_B3:
|
359 | 0da75eb1 | ths | /* We don't simulate electrical parameters of the SDRAM.
|
360 | 0da75eb1 | ths | Accept, but ignore the values. */
|
361 | 0da75eb1 | ths | s->regs[saddr] = val; |
362 | 0da75eb1 | ths | break;
|
363 | 0da75eb1 | ths | |
364 | fde7d5bd | ths | default:
|
365 | fde7d5bd | ths | #if 0
|
366 | fde7d5bd | ths | printf ("gt64120_writel: Bad register offset 0x%x\n", (int)addr);
|
367 | fde7d5bd | ths | #endif
|
368 | fde7d5bd | ths | break;
|
369 | fde7d5bd | ths | } |
370 | fde7d5bd | ths | } |
371 | fde7d5bd | ths | |
372 | fde7d5bd | ths | static uint32_t gt64120_readl (void *opaque, |
373 | fde7d5bd | ths | target_phys_addr_t addr) |
374 | fde7d5bd | ths | { |
375 | fde7d5bd | ths | GT64120State *s = opaque; |
376 | fde7d5bd | ths | uint32_t val; |
377 | fde7d5bd | ths | uint32_t saddr; |
378 | fde7d5bd | ths | |
379 | fde7d5bd | ths | val = 0;
|
380 | fde7d5bd | ths | saddr = (addr & 0xfff) >> 2; |
381 | fde7d5bd | ths | |
382 | fde7d5bd | ths | switch (saddr) {
|
383 | fde7d5bd | ths | |
384 | 0da75eb1 | ths | /* CPU Configuration */
|
385 | 0da75eb1 | ths | case GT_MULTI:
|
386 | 0da75eb1 | ths | /* Only one GT64xxx is present on the CPU bus, return
|
387 | 0da75eb1 | ths | the initial value */
|
388 | 0da75eb1 | ths | val = s->regs[saddr]; |
389 | 0da75eb1 | ths | break;
|
390 | 0da75eb1 | ths | |
391 | fde7d5bd | ths | /* CPU Error Report */
|
392 | fde7d5bd | ths | case GT_CPUERR_ADDRLO:
|
393 | fde7d5bd | ths | case GT_CPUERR_ADDRHI:
|
394 | fde7d5bd | ths | case GT_CPUERR_DATALO:
|
395 | fde7d5bd | ths | case GT_CPUERR_DATAHI:
|
396 | fde7d5bd | ths | case GT_CPUERR_PARITY:
|
397 | 0da75eb1 | ths | /* Emulated memory has no error, always return the initial
|
398 | 0da75eb1 | ths | values */
|
399 | 0da75eb1 | ths | val = s->regs[saddr]; |
400 | 0da75eb1 | ths | break;
|
401 | 0da75eb1 | ths | |
402 | 0da75eb1 | ths | /* CPU Sync Barrier */
|
403 | 0da75eb1 | ths | case GT_PCI0SYNC:
|
404 | 0da75eb1 | ths | case GT_PCI1SYNC:
|
405 | 0da75eb1 | ths | /* Reading those register should empty all FIFO on the PCI
|
406 | 0da75eb1 | ths | bus, which are not emulated. The return value should be
|
407 | 0da75eb1 | ths | a random value that should be ignored. */
|
408 | 0da75eb1 | ths | val = 0xc000ffee;
|
409 | fde7d5bd | ths | break;
|
410 | fde7d5bd | ths | |
411 | fde7d5bd | ths | /* ECC */
|
412 | fde7d5bd | ths | case GT_ECC_ERRDATALO:
|
413 | fde7d5bd | ths | case GT_ECC_ERRDATAHI:
|
414 | fde7d5bd | ths | case GT_ECC_MEM:
|
415 | fde7d5bd | ths | case GT_ECC_CALC:
|
416 | fde7d5bd | ths | case GT_ECC_ERRADDR:
|
417 | 0da75eb1 | ths | /* Emulated memory has no error, always return the initial
|
418 | 0da75eb1 | ths | values */
|
419 | 0da75eb1 | ths | val = s->regs[saddr]; |
420 | fde7d5bd | ths | break;
|
421 | fde7d5bd | ths | |
422 | fde7d5bd | ths | case GT_CPU:
|
423 | fde7d5bd | ths | case GT_PCI0IOLD:
|
424 | fde7d5bd | ths | case GT_PCI0M0LD:
|
425 | fde7d5bd | ths | case GT_PCI0M1LD:
|
426 | fde7d5bd | ths | case GT_PCI1IOLD:
|
427 | fde7d5bd | ths | case GT_PCI1M0LD:
|
428 | fde7d5bd | ths | case GT_PCI1M1LD:
|
429 | fde7d5bd | ths | case GT_PCI0IOHD:
|
430 | fde7d5bd | ths | case GT_PCI0M0HD:
|
431 | fde7d5bd | ths | case GT_PCI0M1HD:
|
432 | fde7d5bd | ths | case GT_PCI1IOHD:
|
433 | fde7d5bd | ths | case GT_PCI1M0HD:
|
434 | fde7d5bd | ths | case GT_PCI1M1HD:
|
435 | fde7d5bd | ths | case GT_PCI0_CMD:
|
436 | fde7d5bd | ths | case GT_PCI1_CMD:
|
437 | fde7d5bd | ths | case GT_PCI0IOREMAP:
|
438 | fde7d5bd | ths | case GT_PCI0M0REMAP:
|
439 | fde7d5bd | ths | case GT_PCI0M1REMAP:
|
440 | fde7d5bd | ths | case GT_PCI1IOREMAP:
|
441 | fde7d5bd | ths | case GT_PCI1M0REMAP:
|
442 | fde7d5bd | ths | case GT_PCI1M1REMAP:
|
443 | fde7d5bd | ths | val = s->regs[saddr]; |
444 | fde7d5bd | ths | break;
|
445 | fde7d5bd | ths | case GT_PCI0_IACK:
|
446 | 4de9b249 | ths | /* Read the IRQ number */
|
447 | 4de9b249 | ths | val = pic_read_irq(isa_pic); |
448 | fde7d5bd | ths | break;
|
449 | fde7d5bd | ths | |
450 | 0da75eb1 | ths | /* SDRAM Parameters */
|
451 | 0da75eb1 | ths | case GT_SDRAM_B0:
|
452 | 0da75eb1 | ths | case GT_SDRAM_B1:
|
453 | 0da75eb1 | ths | case GT_SDRAM_B2:
|
454 | 0da75eb1 | ths | case GT_SDRAM_B3:
|
455 | 0da75eb1 | ths | /* We don't simulate electrical parameters of the SDRAM.
|
456 | 0da75eb1 | ths | Just return the last written value. */
|
457 | 0da75eb1 | ths | val = s->regs[saddr]; |
458 | 0da75eb1 | ths | break;
|
459 | 0da75eb1 | ths | |
460 | fde7d5bd | ths | /* PCI Internal */
|
461 | fde7d5bd | ths | case GT_PCI0_CFGADDR:
|
462 | fde7d5bd | ths | val = s->pci->config_reg; |
463 | fde7d5bd | ths | break;
|
464 | fde7d5bd | ths | case GT_PCI0_CFGDATA:
|
465 | fde7d5bd | ths | val = pci_host_data_readl(s->pci, 0);
|
466 | fde7d5bd | ths | break;
|
467 | fde7d5bd | ths | |
468 | fde7d5bd | ths | default:
|
469 | fde7d5bd | ths | val = s->regs[saddr]; |
470 | fde7d5bd | ths | #if 0
|
471 | fde7d5bd | ths | printf ("gt64120_readl: Bad register offset 0x%x\n", (int)addr);
|
472 | fde7d5bd | ths | #endif
|
473 | fde7d5bd | ths | break;
|
474 | fde7d5bd | ths | } |
475 | fde7d5bd | ths | |
476 | 0da75eb1 | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
477 | 0da75eb1 | ths | return bswap32(val);
|
478 | 0da75eb1 | ths | #else
|
479 | fde7d5bd | ths | return val;
|
480 | 0da75eb1 | ths | #endif
|
481 | fde7d5bd | ths | } |
482 | fde7d5bd | ths | |
483 | fde7d5bd | ths | static CPUWriteMemoryFunc *gt64120_write[] = {
|
484 | fde7d5bd | ths | >64120_writel, |
485 | fde7d5bd | ths | >64120_writel, |
486 | fde7d5bd | ths | >64120_writel, |
487 | fde7d5bd | ths | }; |
488 | fde7d5bd | ths | |
489 | fde7d5bd | ths | static CPUReadMemoryFunc *gt64120_read[] = {
|
490 | fde7d5bd | ths | >64120_readl, |
491 | fde7d5bd | ths | >64120_readl, |
492 | fde7d5bd | ths | >64120_readl, |
493 | fde7d5bd | ths | }; |
494 | fde7d5bd | ths | |
495 | fde7d5bd | ths | static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num) |
496 | fde7d5bd | ths | { |
497 | fde7d5bd | ths | int slot;
|
498 | fde7d5bd | ths | |
499 | fde7d5bd | ths | slot = (pci_dev->devfn >> 3);
|
500 | fde7d5bd | ths | |
501 | fde7d5bd | ths | switch (slot) {
|
502 | fde7d5bd | ths | /* PIIX4 USB */
|
503 | fde7d5bd | ths | case 10: |
504 | fde7d5bd | ths | return 3; |
505 | fde7d5bd | ths | /* AMD 79C973 Ethernet */
|
506 | fde7d5bd | ths | case 11: |
507 | fde7d5bd | ths | return 0; |
508 | fde7d5bd | ths | /* Crystal 4281 Sound */
|
509 | fde7d5bd | ths | case 12: |
510 | fde7d5bd | ths | return 0; |
511 | fde7d5bd | ths | /* PCI slot 1 to 4 */
|
512 | fde7d5bd | ths | case 18 ... 21: |
513 | fde7d5bd | ths | return ((slot - 18) + irq_num) & 0x03; |
514 | fde7d5bd | ths | /* Unknown device, don't do any translation */
|
515 | fde7d5bd | ths | default:
|
516 | fde7d5bd | ths | return irq_num;
|
517 | fde7d5bd | ths | } |
518 | fde7d5bd | ths | } |
519 | fde7d5bd | ths | |
520 | fde7d5bd | ths | extern PCIDevice *piix4_dev;
|
521 | fde7d5bd | ths | static int pci_irq_levels[4]; |
522 | fde7d5bd | ths | |
523 | fde7d5bd | ths | static void pci_gt64120_set_irq(void *pic, int irq_num, int level) |
524 | fde7d5bd | ths | { |
525 | fde7d5bd | ths | int i, pic_irq, pic_level;
|
526 | fde7d5bd | ths | |
527 | fde7d5bd | ths | pci_irq_levels[irq_num] = level; |
528 | fde7d5bd | ths | |
529 | fde7d5bd | ths | /* now we change the pic irq level according to the piix irq mappings */
|
530 | fde7d5bd | ths | /* XXX: optimize */
|
531 | fde7d5bd | ths | pic_irq = piix4_dev->config[0x60 + irq_num];
|
532 | fde7d5bd | ths | if (pic_irq < 16) { |
533 | fde7d5bd | ths | /* The pic level is the logical OR of all the PCI irqs mapped
|
534 | fde7d5bd | ths | to it */
|
535 | fde7d5bd | ths | pic_level = 0;
|
536 | fde7d5bd | ths | for (i = 0; i < 4; i++) { |
537 | fde7d5bd | ths | if (pic_irq == piix4_dev->config[0x60 + i]) |
538 | fde7d5bd | ths | pic_level |= pci_irq_levels[i]; |
539 | fde7d5bd | ths | } |
540 | fde7d5bd | ths | pic_set_irq(pic_irq, pic_level); |
541 | fde7d5bd | ths | } |
542 | fde7d5bd | ths | } |
543 | fde7d5bd | ths | |
544 | fde7d5bd | ths | |
545 | fde7d5bd | ths | void gt64120_reset(void *opaque) |
546 | fde7d5bd | ths | { |
547 | fde7d5bd | ths | GT64120State *s = opaque; |
548 | fde7d5bd | ths | |
549 | fde7d5bd | ths | /* CPU Configuration */
|
550 | fde7d5bd | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
551 | fde7d5bd | ths | s->regs[GT_CPU] = 0x00000000;
|
552 | fde7d5bd | ths | #else
|
553 | fde7d5bd | ths | s->regs[GT_CPU] = 0x00000800;
|
554 | fde7d5bd | ths | #endif
|
555 | fde7d5bd | ths | s->regs[GT_MULTI] = 0x00000000;
|
556 | fde7d5bd | ths | |
557 | fde7d5bd | ths | /* CPU Address decode FIXME: not complete*/
|
558 | fde7d5bd | ths | s->regs[GT_PCI0IOLD] = 0x00000080;
|
559 | fde7d5bd | ths | s->regs[GT_PCI0IOHD] = 0x0000000f;
|
560 | fde7d5bd | ths | s->regs[GT_PCI0M0LD] = 0x00000090;
|
561 | fde7d5bd | ths | s->regs[GT_PCI0M0HD] = 0x0000001f;
|
562 | fde7d5bd | ths | s->regs[GT_PCI0M1LD] = 0x00000790;
|
563 | fde7d5bd | ths | s->regs[GT_PCI0M1HD] = 0x0000001f;
|
564 | fde7d5bd | ths | s->regs[GT_PCI1IOLD] = 0x00000100;
|
565 | fde7d5bd | ths | s->regs[GT_PCI1IOHD] = 0x0000000f;
|
566 | fde7d5bd | ths | s->regs[GT_PCI1M0LD] = 0x00000110;
|
567 | fde7d5bd | ths | s->regs[GT_PCI1M0HD] = 0x0000001f;
|
568 | fde7d5bd | ths | s->regs[GT_PCI1M1LD] = 0x00000120;
|
569 | fde7d5bd | ths | s->regs[GT_PCI1M1HD] = 0x0000002f;
|
570 | fde7d5bd | ths | s->regs[GT_PCI0IOREMAP] = 0x00000080;
|
571 | fde7d5bd | ths | s->regs[GT_PCI0M0REMAP] = 0x00000090;
|
572 | fde7d5bd | ths | s->regs[GT_PCI0M1REMAP] = 0x00000790;
|
573 | fde7d5bd | ths | s->regs[GT_PCI1IOREMAP] = 0x00000100;
|
574 | fde7d5bd | ths | s->regs[GT_PCI1M0REMAP] = 0x00000110;
|
575 | fde7d5bd | ths | s->regs[GT_PCI1M1REMAP] = 0x00000120;
|
576 | fde7d5bd | ths | |
577 | fde7d5bd | ths | /* CPU Error Report */
|
578 | fde7d5bd | ths | s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
|
579 | fde7d5bd | ths | s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
|
580 | fde7d5bd | ths | s->regs[GT_CPUERR_DATALO] = 0xffffffff;
|
581 | fde7d5bd | ths | s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
|
582 | fde7d5bd | ths | s->regs[GT_CPUERR_PARITY] = 0x000000ff;
|
583 | fde7d5bd | ths | |
584 | fde7d5bd | ths | /* ECC */
|
585 | fde7d5bd | ths | s->regs[GT_ECC_ERRDATALO] = 0x00000000;
|
586 | fde7d5bd | ths | s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
|
587 | fde7d5bd | ths | s->regs[GT_ECC_MEM] = 0x00000000;
|
588 | fde7d5bd | ths | s->regs[GT_ECC_CALC] = 0x00000000;
|
589 | fde7d5bd | ths | s->regs[GT_ECC_ERRADDR] = 0x00000000;
|
590 | fde7d5bd | ths | |
591 | 0da75eb1 | ths | /* SDRAM Parameters */
|
592 | 0da75eb1 | ths | s->regs[GT_SDRAM_B0] = 0x00000005;
|
593 | 0da75eb1 | ths | s->regs[GT_SDRAM_B1] = 0x00000005;
|
594 | 0da75eb1 | ths | s->regs[GT_SDRAM_B2] = 0x00000005;
|
595 | 0da75eb1 | ths | s->regs[GT_SDRAM_B3] = 0x00000005;
|
596 | 0da75eb1 | ths | |
597 | fde7d5bd | ths | /* PCI Internal FIXME: not complete*/
|
598 | fde7d5bd | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
599 | fde7d5bd | ths | s->regs[GT_PCI0_CMD] = 0x00000000;
|
600 | fde7d5bd | ths | s->regs[GT_PCI1_CMD] = 0x00000000;
|
601 | fde7d5bd | ths | #else
|
602 | fde7d5bd | ths | s->regs[GT_PCI0_CMD] = 0x00010001;
|
603 | fde7d5bd | ths | s->regs[GT_PCI1_CMD] = 0x00010001;
|
604 | fde7d5bd | ths | #endif
|
605 | fde7d5bd | ths | s->regs[GT_PCI0_IACK] = 0x00000000;
|
606 | fde7d5bd | ths | s->regs[GT_PCI1_IACK] = 0x00000000;
|
607 | fde7d5bd | ths | |
608 | fde7d5bd | ths | gt64120_pci_mapping(s); |
609 | fde7d5bd | ths | } |
610 | fde7d5bd | ths | |
611 | fde7d5bd | ths | PCIBus *pci_gt64120_init(void *pic)
|
612 | fde7d5bd | ths | { |
613 | fde7d5bd | ths | GT64120State *s; |
614 | fde7d5bd | ths | PCIDevice *d; |
615 | fde7d5bd | ths | int gt64120;
|
616 | fde7d5bd | ths | |
617 | fde7d5bd | ths | s = qemu_mallocz(sizeof(GT64120State));
|
618 | fde7d5bd | ths | s->pci = qemu_mallocz(sizeof(GT64120PCIState));
|
619 | fde7d5bd | ths | gt64120_reset(s); |
620 | fde7d5bd | ths | |
621 | fde7d5bd | ths | s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq, |
622 | fde7d5bd | ths | pic, 144, 4); |
623 | fde7d5bd | ths | |
624 | fde7d5bd | ths | gt64120 = cpu_register_io_memory(0, gt64120_read,
|
625 | fde7d5bd | ths | gt64120_write, s); |
626 | fde7d5bd | ths | cpu_register_physical_memory(0x1be00000LL, 0x1000, gt64120); |
627 | fde7d5bd | ths | |
628 | fde7d5bd | ths | d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice), |
629 | fde7d5bd | ths | 0, NULL, NULL); |
630 | fde7d5bd | ths | |
631 | fde7d5bd | ths | d->config[0x00] = 0xab; // vendor_id |
632 | fde7d5bd | ths | d->config[0x01] = 0x11; |
633 | fde7d5bd | ths | d->config[0x02] = 0x46; // device_id |
634 | fde7d5bd | ths | d->config[0x03] = 0x20; |
635 | fde7d5bd | ths | d->config[0x04] = 0x06; |
636 | fde7d5bd | ths | d->config[0x05] = 0x00; |
637 | fde7d5bd | ths | d->config[0x06] = 0x80; |
638 | fde7d5bd | ths | d->config[0x07] = 0xa2; |
639 | fde7d5bd | ths | d->config[0x08] = 0x10; |
640 | fde7d5bd | ths | d->config[0x09] = 0x00; |
641 | fde7d5bd | ths | d->config[0x0A] = 0x80; |
642 | fde7d5bd | ths | d->config[0x0B] = 0x05; |
643 | fde7d5bd | ths | d->config[0x0C] = 0x08; |
644 | fde7d5bd | ths | d->config[0x0D] = 0x40; |
645 | fde7d5bd | ths | d->config[0x0E] = 0x00; |
646 | fde7d5bd | ths | d->config[0x0F] = 0x00; |
647 | fde7d5bd | ths | d->config[0x17] = 0x08; |
648 | fde7d5bd | ths | d->config[0x1B] = 0x1c; |
649 | fde7d5bd | ths | d->config[0x1F] = 0x1f; |
650 | fde7d5bd | ths | d->config[0x23] = 0x14; |
651 | fde7d5bd | ths | d->config[0x27] = 0x14; |
652 | fde7d5bd | ths | d->config[0x3D] = 0x01; |
653 | fde7d5bd | ths | |
654 | fde7d5bd | ths | return s->pci->bus;
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655 | fde7d5bd | ths | } |