root / target-mips / mips-defs.h @ 50d3eeae
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1 | 6af0bf9c | bellard | #if !defined (__QEMU_MIPS_DEFS_H__)
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2 | 6af0bf9c | bellard | #define __QEMU_MIPS_DEFS_H__
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3 | 6af0bf9c | bellard | |
4 | 6af0bf9c | bellard | /* If we want to use 64 bits host regs... */
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5 | 6af0bf9c | bellard | //#define USE_64BITS_REGS
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6 | 6af0bf9c | bellard | /* If we want to use host float regs... */
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7 | 6af0bf9c | bellard | //#define USE_HOST_FLOAT_REGS
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8 | 6af0bf9c | bellard | |
9 | 6af0bf9c | bellard | /* 32 bits target */
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10 | c570fd16 | ths | #undef MIPS_HAS_MIPS64
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11 | c570fd16 | ths | //#define MIPS_HAS_MIPS64 1
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12 | 6af0bf9c | bellard | /* real pages are variable size... */
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13 | 6af0bf9c | bellard | #define TARGET_PAGE_BITS 12 |
14 | 6af0bf9c | bellard | /* Uses MIPS R4Kc TLB model */
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15 | 6af0bf9c | bellard | #define MIPS_USES_R4K_TLB
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16 | 6af0bf9c | bellard | #define MIPS_TLB_NB 16 |
17 | 814b9a47 | ths | #define MIPS_TLB_MAX 128 |
18 | 6ea83fed | bellard | /* Define a implementation number of 1.
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19 | 6ea83fed | bellard | * Define a major version 1, minor version 0.
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20 | 6ea83fed | bellard | */
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21 | 6ea83fed | bellard | #define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0) |
22 | 7a387fff | ths | /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
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23 | 7a387fff | ths | uncached coherency */
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24 | 7a387fff | ths | #define MIPS_CONFIG0_1 \
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25 | 7a387fff | ths | ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \ |
26 | 7a387fff | ths | (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \ |
27 | 7a387fff | ths | (0x2 << CP0C0_K0))
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28 | c5d6edc3 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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29 | c5d6edc3 | bellard | #define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE)) |
30 | c5d6edc3 | bellard | #else
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31 | c5d6edc3 | bellard | #define MIPS_CONFIG0 MIPS_CONFIG0_1
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32 | c5d6edc3 | bellard | #endif
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33 | 7a387fff | ths | /* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line,
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34 | 7a387fff | ths | 2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
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35 | 7a387fff | ths | no coprocessor2 attached, no MDMX support attached,
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36 | 7a387fff | ths | no performance counters, watch registers present,
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37 | 36d23958 | ths | no code compression, EJTAG present, no FPU */
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38 | 36d23958 | ths | #define MIPS_CONFIG1 \
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39 | 7a387fff | ths | ((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) | \ |
40 | 7a387fff | ths | (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \ |
41 | 7a387fff | ths | (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \ |
42 | 7a387fff | ths | (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ |
43 | 36d23958 | ths | (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ |
44 | 36d23958 | ths | (0 << CP0C1_FP))
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45 | 7a387fff | ths | /* Have config3, no tertiary/secondary caches implemented */
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46 | 7a387fff | ths | #define MIPS_CONFIG2 \
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47 | 7a387fff | ths | ((1 << CP0C2_M))
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48 | 7a387fff | ths | /* No config4, no DSP ASE, no large physaddr,
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49 | 7a387fff | ths | no external interrupt controller, no vectored interupts,
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50 | 7a387fff | ths | no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
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51 | 7a387fff | ths | #define MIPS_CONFIG3 \
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52 | 7a387fff | ths | ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ |
53 | 7a387fff | ths | (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ |
54 | 7a387fff | ths | (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL)) |
55 | 6af0bf9c | bellard | |
56 | c570fd16 | ths | #ifdef MIPS_HAS_MIPS64
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57 | c570fd16 | ths | #define TARGET_LONG_BITS 64 |
58 | c570fd16 | ths | #else
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59 | c570fd16 | ths | #define TARGET_LONG_BITS 32 |
60 | c570fd16 | ths | #endif
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61 | c570fd16 | ths | |
62 | 6af0bf9c | bellard | #endif /* !defined (__QEMU_MIPS_DEFS_H__) */ |