root / target-sh4 / op.c @ 50d3eeae
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1 | fdf9b3e8 | bellard | /*
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2 | fdf9b3e8 | bellard | * SH4 emulation
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3 | fdf9b3e8 | bellard | *
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4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
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5 | fdf9b3e8 | bellard | *
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6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
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7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
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9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | fdf9b3e8 | bellard | *
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11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
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12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
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15 | fdf9b3e8 | bellard | *
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16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | fdf9b3e8 | bellard | * License along with this library; if not, write to the Free Software
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18 | fdf9b3e8 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | fdf9b3e8 | bellard | */
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20 | fdf9b3e8 | bellard | #include "exec.h" |
21 | fdf9b3e8 | bellard | |
22 | fdf9b3e8 | bellard | static inline void set_flag(uint32_t flag) |
23 | fdf9b3e8 | bellard | { |
24 | fdf9b3e8 | bellard | env->flags |= flag; |
25 | fdf9b3e8 | bellard | } |
26 | fdf9b3e8 | bellard | |
27 | fdf9b3e8 | bellard | static inline void clr_flag(uint32_t flag) |
28 | fdf9b3e8 | bellard | { |
29 | fdf9b3e8 | bellard | env->flags &= ~flag; |
30 | fdf9b3e8 | bellard | } |
31 | fdf9b3e8 | bellard | |
32 | fdf9b3e8 | bellard | static inline void set_t(void) |
33 | fdf9b3e8 | bellard | { |
34 | fdf9b3e8 | bellard | env->sr |= SR_T; |
35 | fdf9b3e8 | bellard | } |
36 | fdf9b3e8 | bellard | |
37 | fdf9b3e8 | bellard | static inline void clr_t(void) |
38 | fdf9b3e8 | bellard | { |
39 | fdf9b3e8 | bellard | env->sr &= ~SR_T; |
40 | fdf9b3e8 | bellard | } |
41 | fdf9b3e8 | bellard | |
42 | fdf9b3e8 | bellard | static inline void cond_t(int cond) |
43 | fdf9b3e8 | bellard | { |
44 | fdf9b3e8 | bellard | if (cond)
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45 | fdf9b3e8 | bellard | set_t(); |
46 | fdf9b3e8 | bellard | else
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47 | fdf9b3e8 | bellard | clr_t(); |
48 | fdf9b3e8 | bellard | } |
49 | fdf9b3e8 | bellard | |
50 | fdf9b3e8 | bellard | void OPPROTO op_movl_imm_T0(void) |
51 | fdf9b3e8 | bellard | { |
52 | fdf9b3e8 | bellard | T0 = (uint32_t) PARAM1; |
53 | fdf9b3e8 | bellard | RETURN(); |
54 | fdf9b3e8 | bellard | } |
55 | fdf9b3e8 | bellard | |
56 | fdf9b3e8 | bellard | void OPPROTO op_movl_imm_T1(void) |
57 | fdf9b3e8 | bellard | { |
58 | fdf9b3e8 | bellard | T0 = (uint32_t) PARAM1; |
59 | fdf9b3e8 | bellard | RETURN(); |
60 | fdf9b3e8 | bellard | } |
61 | fdf9b3e8 | bellard | |
62 | fdf9b3e8 | bellard | void OPPROTO op_movl_imm_T2(void) |
63 | fdf9b3e8 | bellard | { |
64 | fdf9b3e8 | bellard | T0 = (uint32_t) PARAM1; |
65 | fdf9b3e8 | bellard | RETURN(); |
66 | fdf9b3e8 | bellard | } |
67 | fdf9b3e8 | bellard | |
68 | fdf9b3e8 | bellard | void OPPROTO op_cmp_eq_imm_T0(void) |
69 | fdf9b3e8 | bellard | { |
70 | fdf9b3e8 | bellard | cond_t((int32_t) T0 == (int32_t) PARAM1); |
71 | fdf9b3e8 | bellard | RETURN(); |
72 | fdf9b3e8 | bellard | } |
73 | fdf9b3e8 | bellard | |
74 | fdf9b3e8 | bellard | void OPPROTO op_cmd_eq_T0_T1(void) |
75 | fdf9b3e8 | bellard | { |
76 | fdf9b3e8 | bellard | cond_t(T0 == T1); |
77 | fdf9b3e8 | bellard | RETURN(); |
78 | fdf9b3e8 | bellard | } |
79 | fdf9b3e8 | bellard | |
80 | fdf9b3e8 | bellard | void OPPROTO op_cmd_hs_T0_T1(void) |
81 | fdf9b3e8 | bellard | { |
82 | fdf9b3e8 | bellard | cond_t((uint32_t) T0 <= (uint32_t) T1); |
83 | fdf9b3e8 | bellard | RETURN(); |
84 | fdf9b3e8 | bellard | } |
85 | fdf9b3e8 | bellard | |
86 | fdf9b3e8 | bellard | void OPPROTO op_cmd_ge_T0_T1(void) |
87 | fdf9b3e8 | bellard | { |
88 | fdf9b3e8 | bellard | cond_t((int32_t) T0 <= (int32_t) T1); |
89 | fdf9b3e8 | bellard | RETURN(); |
90 | fdf9b3e8 | bellard | } |
91 | fdf9b3e8 | bellard | |
92 | fdf9b3e8 | bellard | void OPPROTO op_cmd_hi_T0_T1(void) |
93 | fdf9b3e8 | bellard | { |
94 | fdf9b3e8 | bellard | cond_t((uint32_t) T0 < (uint32_t) T1); |
95 | fdf9b3e8 | bellard | RETURN(); |
96 | fdf9b3e8 | bellard | } |
97 | fdf9b3e8 | bellard | |
98 | fdf9b3e8 | bellard | void OPPROTO op_cmd_gt_T0_T1(void) |
99 | fdf9b3e8 | bellard | { |
100 | fdf9b3e8 | bellard | cond_t((int32_t) T0 < (int32_t) T1); |
101 | fdf9b3e8 | bellard | RETURN(); |
102 | fdf9b3e8 | bellard | } |
103 | fdf9b3e8 | bellard | |
104 | fdf9b3e8 | bellard | void OPPROTO op_not_T0(void) |
105 | fdf9b3e8 | bellard | { |
106 | fdf9b3e8 | bellard | T0 = ~T0; |
107 | fdf9b3e8 | bellard | RETURN(); |
108 | fdf9b3e8 | bellard | } |
109 | fdf9b3e8 | bellard | |
110 | fdf9b3e8 | bellard | void OPPROTO op_bf_s(void) |
111 | fdf9b3e8 | bellard | { |
112 | fdf9b3e8 | bellard | env->delayed_pc = PARAM1; |
113 | 9c2a9ea1 | pbrook | set_flag(DELAY_SLOT_CONDITIONAL | ((~env->sr) & SR_T)); |
114 | fdf9b3e8 | bellard | RETURN(); |
115 | fdf9b3e8 | bellard | } |
116 | fdf9b3e8 | bellard | |
117 | fdf9b3e8 | bellard | void OPPROTO op_bt_s(void) |
118 | fdf9b3e8 | bellard | { |
119 | fdf9b3e8 | bellard | env->delayed_pc = PARAM1; |
120 | 9c2a9ea1 | pbrook | set_flag(DELAY_SLOT_CONDITIONAL | (env->sr & SR_T)); |
121 | fdf9b3e8 | bellard | RETURN(); |
122 | fdf9b3e8 | bellard | } |
123 | fdf9b3e8 | bellard | |
124 | fdf9b3e8 | bellard | void OPPROTO op_bra(void) |
125 | fdf9b3e8 | bellard | { |
126 | fdf9b3e8 | bellard | env->delayed_pc = PARAM1; |
127 | fdf9b3e8 | bellard | set_flag(DELAY_SLOT); |
128 | fdf9b3e8 | bellard | RETURN(); |
129 | fdf9b3e8 | bellard | } |
130 | fdf9b3e8 | bellard | |
131 | fdf9b3e8 | bellard | void OPPROTO op_braf_T0(void) |
132 | fdf9b3e8 | bellard | { |
133 | fdf9b3e8 | bellard | env->delayed_pc = PARAM1 + T0; |
134 | fdf9b3e8 | bellard | set_flag(DELAY_SLOT); |
135 | fdf9b3e8 | bellard | RETURN(); |
136 | fdf9b3e8 | bellard | } |
137 | fdf9b3e8 | bellard | |
138 | fdf9b3e8 | bellard | void OPPROTO op_bsr(void) |
139 | fdf9b3e8 | bellard | { |
140 | fdf9b3e8 | bellard | env->pr = PARAM1; |
141 | fdf9b3e8 | bellard | env->delayed_pc = PARAM2; |
142 | fdf9b3e8 | bellard | set_flag(DELAY_SLOT); |
143 | fdf9b3e8 | bellard | RETURN(); |
144 | fdf9b3e8 | bellard | } |
145 | fdf9b3e8 | bellard | |
146 | fdf9b3e8 | bellard | void OPPROTO op_bsrf_T0(void) |
147 | fdf9b3e8 | bellard | { |
148 | fdf9b3e8 | bellard | env->pr = PARAM1; |
149 | fdf9b3e8 | bellard | env->delayed_pc = PARAM1 + T0; |
150 | fdf9b3e8 | bellard | set_flag(DELAY_SLOT); |
151 | fdf9b3e8 | bellard | RETURN(); |
152 | fdf9b3e8 | bellard | } |
153 | fdf9b3e8 | bellard | |
154 | fdf9b3e8 | bellard | void OPPROTO op_jsr_T0(void) |
155 | fdf9b3e8 | bellard | { |
156 | fdf9b3e8 | bellard | env->pr = PARAM1; |
157 | fdf9b3e8 | bellard | env->delayed_pc = T0; |
158 | fdf9b3e8 | bellard | set_flag(DELAY_SLOT); |
159 | fdf9b3e8 | bellard | RETURN(); |
160 | fdf9b3e8 | bellard | } |
161 | fdf9b3e8 | bellard | |
162 | fdf9b3e8 | bellard | void OPPROTO op_rts(void) |
163 | fdf9b3e8 | bellard | { |
164 | fdf9b3e8 | bellard | env->delayed_pc = env->pr; |
165 | fdf9b3e8 | bellard | set_flag(DELAY_SLOT); |
166 | fdf9b3e8 | bellard | RETURN(); |
167 | fdf9b3e8 | bellard | } |
168 | fdf9b3e8 | bellard | |
169 | fdf9b3e8 | bellard | void OPPROTO op_clr_delay_slot(void) |
170 | fdf9b3e8 | bellard | { |
171 | fdf9b3e8 | bellard | clr_flag(DELAY_SLOT); |
172 | fdf9b3e8 | bellard | RETURN(); |
173 | fdf9b3e8 | bellard | } |
174 | fdf9b3e8 | bellard | |
175 | fdf9b3e8 | bellard | void OPPROTO op_clr_delay_slot_conditional(void) |
176 | fdf9b3e8 | bellard | { |
177 | fdf9b3e8 | bellard | clr_flag(DELAY_SLOT_CONDITIONAL); |
178 | fdf9b3e8 | bellard | RETURN(); |
179 | fdf9b3e8 | bellard | } |
180 | fdf9b3e8 | bellard | |
181 | fdf9b3e8 | bellard | void OPPROTO op_exit_tb(void) |
182 | fdf9b3e8 | bellard | { |
183 | fdf9b3e8 | bellard | EXIT_TB(); |
184 | fdf9b3e8 | bellard | RETURN(); |
185 | fdf9b3e8 | bellard | } |
186 | fdf9b3e8 | bellard | |
187 | fdf9b3e8 | bellard | void OPPROTO op_addl_imm_T0(void) |
188 | fdf9b3e8 | bellard | { |
189 | fdf9b3e8 | bellard | T0 += PARAM1; |
190 | fdf9b3e8 | bellard | RETURN(); |
191 | fdf9b3e8 | bellard | } |
192 | fdf9b3e8 | bellard | |
193 | fdf9b3e8 | bellard | void OPPROTO op_addl_imm_T1(void) |
194 | fdf9b3e8 | bellard | { |
195 | fdf9b3e8 | bellard | T1 += PARAM1; |
196 | fdf9b3e8 | bellard | RETURN(); |
197 | fdf9b3e8 | bellard | } |
198 | fdf9b3e8 | bellard | |
199 | fdf9b3e8 | bellard | void OPPROTO op_clrmac(void) |
200 | fdf9b3e8 | bellard | { |
201 | fdf9b3e8 | bellard | env->mach = env->macl = 0;
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202 | fdf9b3e8 | bellard | RETURN(); |
203 | fdf9b3e8 | bellard | } |
204 | fdf9b3e8 | bellard | |
205 | fdf9b3e8 | bellard | void OPPROTO op_clrs(void) |
206 | fdf9b3e8 | bellard | { |
207 | fdf9b3e8 | bellard | env->sr &= ~SR_S; |
208 | fdf9b3e8 | bellard | RETURN(); |
209 | fdf9b3e8 | bellard | } |
210 | fdf9b3e8 | bellard | |
211 | fdf9b3e8 | bellard | void OPPROTO op_clrt(void) |
212 | fdf9b3e8 | bellard | { |
213 | fdf9b3e8 | bellard | env->sr &= ~SR_T; |
214 | fdf9b3e8 | bellard | RETURN(); |
215 | fdf9b3e8 | bellard | } |
216 | fdf9b3e8 | bellard | |
217 | fdf9b3e8 | bellard | void OPPROTO op_sets(void) |
218 | fdf9b3e8 | bellard | { |
219 | fdf9b3e8 | bellard | env->sr |= SR_S; |
220 | fdf9b3e8 | bellard | RETURN(); |
221 | fdf9b3e8 | bellard | } |
222 | fdf9b3e8 | bellard | |
223 | fdf9b3e8 | bellard | void OPPROTO op_sett(void) |
224 | fdf9b3e8 | bellard | { |
225 | fdf9b3e8 | bellard | env->sr |= SR_T; |
226 | fdf9b3e8 | bellard | RETURN(); |
227 | fdf9b3e8 | bellard | } |
228 | fdf9b3e8 | bellard | |
229 | eda9b09b | bellard | void OPPROTO op_frchg(void) |
230 | eda9b09b | bellard | { |
231 | eda9b09b | bellard | env->fpscr ^= FPSCR_FR; |
232 | eda9b09b | bellard | RETURN(); |
233 | eda9b09b | bellard | } |
234 | eda9b09b | bellard | |
235 | eda9b09b | bellard | void OPPROTO op_fschg(void) |
236 | eda9b09b | bellard | { |
237 | eda9b09b | bellard | env->fpscr ^= FPSCR_SZ; |
238 | eda9b09b | bellard | RETURN(); |
239 | eda9b09b | bellard | } |
240 | eda9b09b | bellard | |
241 | fdf9b3e8 | bellard | void OPPROTO op_rte(void) |
242 | fdf9b3e8 | bellard | { |
243 | fdf9b3e8 | bellard | env->sr = env->ssr; |
244 | fdf9b3e8 | bellard | env->delayed_pc = env->spc; |
245 | fdf9b3e8 | bellard | set_flag(DELAY_SLOT); |
246 | fdf9b3e8 | bellard | RETURN(); |
247 | fdf9b3e8 | bellard | } |
248 | fdf9b3e8 | bellard | |
249 | fdf9b3e8 | bellard | void OPPROTO op_swapb_T0(void) |
250 | fdf9b3e8 | bellard | { |
251 | fdf9b3e8 | bellard | T0 = (T0 & 0xffff0000) | ((T0 & 0xff) << 8) | ((T0 >> 8) & 0xff); |
252 | fdf9b3e8 | bellard | RETURN(); |
253 | fdf9b3e8 | bellard | } |
254 | fdf9b3e8 | bellard | |
255 | fdf9b3e8 | bellard | void OPPROTO op_swapw_T0(void) |
256 | fdf9b3e8 | bellard | { |
257 | fdf9b3e8 | bellard | T0 = ((T0 & 0xffff) << 16) | ((T0 >> 16) & 0xffff); |
258 | fdf9b3e8 | bellard | RETURN(); |
259 | fdf9b3e8 | bellard | } |
260 | fdf9b3e8 | bellard | |
261 | fdf9b3e8 | bellard | void OPPROTO op_xtrct_T0_T1(void) |
262 | fdf9b3e8 | bellard | { |
263 | fdf9b3e8 | bellard | T1 = ((T0 & 0xffff) << 16) | ((T1 >> 16) & 0xffff); |
264 | fdf9b3e8 | bellard | RETURN(); |
265 | fdf9b3e8 | bellard | } |
266 | fdf9b3e8 | bellard | |
267 | fdf9b3e8 | bellard | void OPPROTO op_addc_T0_T1(void) |
268 | fdf9b3e8 | bellard | { |
269 | fdf9b3e8 | bellard | helper_addc_T0_T1(); |
270 | fdf9b3e8 | bellard | RETURN(); |
271 | fdf9b3e8 | bellard | } |
272 | fdf9b3e8 | bellard | |
273 | fdf9b3e8 | bellard | void OPPROTO op_addv_T0_T1(void) |
274 | fdf9b3e8 | bellard | { |
275 | fdf9b3e8 | bellard | helper_addv_T0_T1(); |
276 | fdf9b3e8 | bellard | RETURN(); |
277 | fdf9b3e8 | bellard | } |
278 | fdf9b3e8 | bellard | |
279 | fdf9b3e8 | bellard | void OPPROTO op_cmp_eq_T0_T1(void) |
280 | fdf9b3e8 | bellard | { |
281 | fdf9b3e8 | bellard | cond_t(T1 == T0); |
282 | fdf9b3e8 | bellard | RETURN(); |
283 | fdf9b3e8 | bellard | } |
284 | fdf9b3e8 | bellard | |
285 | fdf9b3e8 | bellard | void OPPROTO op_cmp_ge_T0_T1(void) |
286 | fdf9b3e8 | bellard | { |
287 | fdf9b3e8 | bellard | cond_t((int32_t) T1 >= (int32_t) T0); |
288 | fdf9b3e8 | bellard | RETURN(); |
289 | fdf9b3e8 | bellard | } |
290 | fdf9b3e8 | bellard | |
291 | fdf9b3e8 | bellard | void OPPROTO op_cmp_gt_T0_T1(void) |
292 | fdf9b3e8 | bellard | { |
293 | fdf9b3e8 | bellard | cond_t((int32_t) T1 > (int32_t) T0); |
294 | fdf9b3e8 | bellard | RETURN(); |
295 | fdf9b3e8 | bellard | } |
296 | fdf9b3e8 | bellard | |
297 | fdf9b3e8 | bellard | void OPPROTO op_cmp_hi_T0_T1(void) |
298 | fdf9b3e8 | bellard | { |
299 | fdf9b3e8 | bellard | cond_t((uint32_t) T1 > (uint32_t) T0); |
300 | fdf9b3e8 | bellard | RETURN(); |
301 | fdf9b3e8 | bellard | } |
302 | fdf9b3e8 | bellard | |
303 | fdf9b3e8 | bellard | void OPPROTO op_cmp_hs_T0_T1(void) |
304 | fdf9b3e8 | bellard | { |
305 | fdf9b3e8 | bellard | cond_t((uint32_t) T1 >= (uint32_t) T0); |
306 | fdf9b3e8 | bellard | RETURN(); |
307 | fdf9b3e8 | bellard | } |
308 | fdf9b3e8 | bellard | |
309 | fdf9b3e8 | bellard | void OPPROTO op_cmp_str_T0_T1(void) |
310 | fdf9b3e8 | bellard | { |
311 | fdf9b3e8 | bellard | cond_t((T0 & 0x000000ff) == (T1 & 0x000000ff) || |
312 | fdf9b3e8 | bellard | (T0 & 0x0000ff00) == (T1 & 0x0000ff00) || |
313 | fdf9b3e8 | bellard | (T0 & 0x00ff0000) == (T1 & 0x00ff0000) || |
314 | fdf9b3e8 | bellard | (T0 & 0xff000000) == (T1 & 0xff000000)); |
315 | fdf9b3e8 | bellard | RETURN(); |
316 | fdf9b3e8 | bellard | } |
317 | fdf9b3e8 | bellard | |
318 | fdf9b3e8 | bellard | void OPPROTO op_tst_T0_T1(void) |
319 | fdf9b3e8 | bellard | { |
320 | fdf9b3e8 | bellard | cond_t((T1 & T0) == 0);
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321 | fdf9b3e8 | bellard | RETURN(); |
322 | fdf9b3e8 | bellard | } |
323 | fdf9b3e8 | bellard | |
324 | fdf9b3e8 | bellard | void OPPROTO op_div0s_T0_T1(void) |
325 | fdf9b3e8 | bellard | { |
326 | fdf9b3e8 | bellard | if (T1 & 0x80000000) |
327 | fdf9b3e8 | bellard | env->sr |= SR_Q; |
328 | fdf9b3e8 | bellard | else
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329 | fdf9b3e8 | bellard | env->sr &= ~SR_Q; |
330 | fdf9b3e8 | bellard | if (T0 & 0x80000000) |
331 | fdf9b3e8 | bellard | env->sr |= SR_M; |
332 | fdf9b3e8 | bellard | else
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333 | fdf9b3e8 | bellard | env->sr &= ~SR_M; |
334 | fdf9b3e8 | bellard | cond_t((T1 ^ T0) & 0x80000000);
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335 | fdf9b3e8 | bellard | RETURN(); |
336 | fdf9b3e8 | bellard | } |
337 | fdf9b3e8 | bellard | |
338 | fdf9b3e8 | bellard | void OPPROTO op_div0u(void) |
339 | fdf9b3e8 | bellard | { |
340 | fdf9b3e8 | bellard | env->sr &= ~(SR_M | SR_Q | SR_T); |
341 | fdf9b3e8 | bellard | RETURN(); |
342 | fdf9b3e8 | bellard | } |
343 | fdf9b3e8 | bellard | |
344 | fdf9b3e8 | bellard | void OPPROTO op_div1_T0_T1(void) |
345 | fdf9b3e8 | bellard | { |
346 | fdf9b3e8 | bellard | helper_div1_T0_T1(); |
347 | fdf9b3e8 | bellard | RETURN(); |
348 | fdf9b3e8 | bellard | } |
349 | fdf9b3e8 | bellard | |
350 | fdf9b3e8 | bellard | void OPPROTO op_dmulsl_T0_T1(void) |
351 | fdf9b3e8 | bellard | { |
352 | fdf9b3e8 | bellard | helper_dmulsl_T0_T1(); |
353 | fdf9b3e8 | bellard | RETURN(); |
354 | fdf9b3e8 | bellard | } |
355 | fdf9b3e8 | bellard | |
356 | fdf9b3e8 | bellard | void OPPROTO op_dmulul_T0_T1(void) |
357 | fdf9b3e8 | bellard | { |
358 | fdf9b3e8 | bellard | helper_dmulul_T0_T1(); |
359 | fdf9b3e8 | bellard | RETURN(); |
360 | fdf9b3e8 | bellard | } |
361 | fdf9b3e8 | bellard | |
362 | fdf9b3e8 | bellard | void OPPROTO op_macl_T0_T1(void) |
363 | fdf9b3e8 | bellard | { |
364 | fdf9b3e8 | bellard | helper_macl_T0_T1(); |
365 | fdf9b3e8 | bellard | RETURN(); |
366 | fdf9b3e8 | bellard | } |
367 | fdf9b3e8 | bellard | |
368 | fdf9b3e8 | bellard | void OPPROTO op_macw_T0_T1(void) |
369 | fdf9b3e8 | bellard | { |
370 | fdf9b3e8 | bellard | helper_macw_T0_T1(); |
371 | fdf9b3e8 | bellard | RETURN(); |
372 | fdf9b3e8 | bellard | } |
373 | fdf9b3e8 | bellard | |
374 | fdf9b3e8 | bellard | void OPPROTO op_mull_T0_T1(void) |
375 | fdf9b3e8 | bellard | { |
376 | fdf9b3e8 | bellard | env->macl = (T0 * T1) & 0xffffffff;
|
377 | fdf9b3e8 | bellard | RETURN(); |
378 | fdf9b3e8 | bellard | } |
379 | fdf9b3e8 | bellard | |
380 | fdf9b3e8 | bellard | void OPPROTO op_mulsw_T0_T1(void) |
381 | fdf9b3e8 | bellard | { |
382 | fdf9b3e8 | bellard | env->macl = (int32_t) T0 *(int32_t) T1; |
383 | fdf9b3e8 | bellard | RETURN(); |
384 | fdf9b3e8 | bellard | } |
385 | fdf9b3e8 | bellard | |
386 | fdf9b3e8 | bellard | void OPPROTO op_muluw_T0_T1(void) |
387 | fdf9b3e8 | bellard | { |
388 | fdf9b3e8 | bellard | env->macl = (uint32_t) T0 *(uint32_t) T1; |
389 | fdf9b3e8 | bellard | RETURN(); |
390 | fdf9b3e8 | bellard | } |
391 | fdf9b3e8 | bellard | |
392 | fdf9b3e8 | bellard | void OPPROTO op_neg_T0(void) |
393 | fdf9b3e8 | bellard | { |
394 | fdf9b3e8 | bellard | T0 = -T0; |
395 | fdf9b3e8 | bellard | RETURN(); |
396 | fdf9b3e8 | bellard | } |
397 | fdf9b3e8 | bellard | |
398 | fdf9b3e8 | bellard | void OPPROTO op_negc_T0(void) |
399 | fdf9b3e8 | bellard | { |
400 | fdf9b3e8 | bellard | helper_negc_T0(); |
401 | fdf9b3e8 | bellard | RETURN(); |
402 | fdf9b3e8 | bellard | } |
403 | fdf9b3e8 | bellard | |
404 | fdf9b3e8 | bellard | void OPPROTO op_shad_T0_T1(void) |
405 | fdf9b3e8 | bellard | { |
406 | fdf9b3e8 | bellard | if ((T0 & 0x80000000) == 0) |
407 | fdf9b3e8 | bellard | T1 <<= (T0 & 0x1f);
|
408 | fdf9b3e8 | bellard | else if ((T0 & 0x1f) == 0) |
409 | fdf9b3e8 | bellard | T1 = 0;
|
410 | fdf9b3e8 | bellard | else
|
411 | fdf9b3e8 | bellard | T1 = ((int32_t) T1) >> ((~T0 & 0x1f) + 1); |
412 | fdf9b3e8 | bellard | RETURN(); |
413 | fdf9b3e8 | bellard | } |
414 | fdf9b3e8 | bellard | |
415 | fdf9b3e8 | bellard | void OPPROTO op_shld_T0_T1(void) |
416 | fdf9b3e8 | bellard | { |
417 | fdf9b3e8 | bellard | if ((T0 & 0x80000000) == 0) |
418 | fdf9b3e8 | bellard | T1 <<= (T0 & 0x1f);
|
419 | fdf9b3e8 | bellard | else if ((T0 & 0x1f) == 0) |
420 | fdf9b3e8 | bellard | T1 = 0;
|
421 | fdf9b3e8 | bellard | else
|
422 | fdf9b3e8 | bellard | T1 = ((uint32_t) T1) >> ((~T0 & 0x1f) + 1); |
423 | fdf9b3e8 | bellard | RETURN(); |
424 | fdf9b3e8 | bellard | } |
425 | fdf9b3e8 | bellard | |
426 | fdf9b3e8 | bellard | void OPPROTO op_subc_T0_T1(void) |
427 | fdf9b3e8 | bellard | { |
428 | fdf9b3e8 | bellard | helper_subc_T0_T1(); |
429 | fdf9b3e8 | bellard | RETURN(); |
430 | fdf9b3e8 | bellard | } |
431 | fdf9b3e8 | bellard | |
432 | fdf9b3e8 | bellard | void OPPROTO op_subv_T0_T1(void) |
433 | fdf9b3e8 | bellard | { |
434 | fdf9b3e8 | bellard | helper_subv_T0_T1(); |
435 | fdf9b3e8 | bellard | RETURN(); |
436 | fdf9b3e8 | bellard | } |
437 | fdf9b3e8 | bellard | |
438 | fdf9b3e8 | bellard | void OPPROTO op_trapa(void) |
439 | fdf9b3e8 | bellard | { |
440 | fdf9b3e8 | bellard | env->tra = PARAM1 * 2;
|
441 | fdf9b3e8 | bellard | env->exception_index = 0x160;
|
442 | fdf9b3e8 | bellard | do_raise_exception(); |
443 | fdf9b3e8 | bellard | RETURN(); |
444 | fdf9b3e8 | bellard | } |
445 | fdf9b3e8 | bellard | |
446 | fdf9b3e8 | bellard | void OPPROTO op_cmp_pl_T0(void) |
447 | fdf9b3e8 | bellard | { |
448 | fdf9b3e8 | bellard | cond_t((int32_t) T0 > 0);
|
449 | fdf9b3e8 | bellard | RETURN(); |
450 | fdf9b3e8 | bellard | } |
451 | fdf9b3e8 | bellard | |
452 | fdf9b3e8 | bellard | void OPPROTO op_cmp_pz_T0(void) |
453 | fdf9b3e8 | bellard | { |
454 | fdf9b3e8 | bellard | cond_t((int32_t) T0 >= 0);
|
455 | fdf9b3e8 | bellard | RETURN(); |
456 | fdf9b3e8 | bellard | } |
457 | fdf9b3e8 | bellard | |
458 | fdf9b3e8 | bellard | void OPPROTO op_jmp_T0(void) |
459 | fdf9b3e8 | bellard | { |
460 | fdf9b3e8 | bellard | env->delayed_pc = T0; |
461 | fdf9b3e8 | bellard | set_flag(DELAY_SLOT); |
462 | fdf9b3e8 | bellard | RETURN(); |
463 | fdf9b3e8 | bellard | } |
464 | fdf9b3e8 | bellard | |
465 | fdf9b3e8 | bellard | void OPPROTO op_movl_rN_rN(void) |
466 | fdf9b3e8 | bellard | { |
467 | fdf9b3e8 | bellard | env->gregs[PARAM2] = env->gregs[PARAM1]; |
468 | fdf9b3e8 | bellard | RETURN(); |
469 | fdf9b3e8 | bellard | } |
470 | fdf9b3e8 | bellard | |
471 | fdf9b3e8 | bellard | void OPPROTO op_ldcl_rMplus_rN_bank(void) |
472 | fdf9b3e8 | bellard | { |
473 | fdf9b3e8 | bellard | env->gregs[PARAM2] = env->gregs[PARAM1]; |
474 | fdf9b3e8 | bellard | env->gregs[PARAM1] += 4;
|
475 | fdf9b3e8 | bellard | RETURN(); |
476 | fdf9b3e8 | bellard | } |
477 | fdf9b3e8 | bellard | |
478 | eda9b09b | bellard | void OPPROTO op_ldc_T0_sr(void) |
479 | eda9b09b | bellard | { |
480 | eda9b09b | bellard | env->sr = T0 & 0x700083f3;
|
481 | eda9b09b | bellard | RETURN(); |
482 | eda9b09b | bellard | } |
483 | eda9b09b | bellard | |
484 | eda9b09b | bellard | void OPPROTO op_stc_sr_T0(void) |
485 | eda9b09b | bellard | { |
486 | eda9b09b | bellard | T0 = env->sr; |
487 | eda9b09b | bellard | RETURN(); |
488 | eda9b09b | bellard | } |
489 | eda9b09b | bellard | |
490 | fdf9b3e8 | bellard | #define LDSTOPS(target,load,store) \
|
491 | fdf9b3e8 | bellard | void OPPROTO op_##load##_T0_##target (void) \ |
492 | fdf9b3e8 | bellard | { env ->target = T0; RETURN(); \ |
493 | fdf9b3e8 | bellard | } \ |
494 | fdf9b3e8 | bellard | void OPPROTO op_##store##_##target##_T0 (void) \ |
495 | fdf9b3e8 | bellard | { T0 = env->target; RETURN(); \ |
496 | fdf9b3e8 | bellard | } \ |
497 | fdf9b3e8 | bellard | |
498 | fdf9b3e8 | bellard | LDSTOPS(gbr, ldc, stc) |
499 | fdf9b3e8 | bellard | LDSTOPS(vbr, ldc, stc) |
500 | fdf9b3e8 | bellard | LDSTOPS(ssr, ldc, stc) |
501 | fdf9b3e8 | bellard | LDSTOPS(spc, ldc, stc) |
502 | fdf9b3e8 | bellard | LDSTOPS(sgr, ldc, stc) |
503 | fdf9b3e8 | bellard | LDSTOPS(dbr, ldc, stc) |
504 | fdf9b3e8 | bellard | LDSTOPS(mach, lds, sts) |
505 | fdf9b3e8 | bellard | LDSTOPS(macl, lds, sts) |
506 | fdf9b3e8 | bellard | LDSTOPS(pr, lds, sts) |
507 | eda9b09b | bellard | LDSTOPS(fpul, lds, sts) |
508 | eda9b09b | bellard | |
509 | eda9b09b | bellard | void OPPROTO op_lds_T0_fpscr(void) |
510 | eda9b09b | bellard | { |
511 | eda9b09b | bellard | env->fpscr = T0 & 0x003fffff;
|
512 | eda9b09b | bellard | RETURN(); |
513 | eda9b09b | bellard | } |
514 | eda9b09b | bellard | |
515 | eda9b09b | bellard | void OPPROTO op_sts_fpscr_T0(void) |
516 | eda9b09b | bellard | { |
517 | eda9b09b | bellard | T0 = env->fpscr & 0x003fffff;
|
518 | eda9b09b | bellard | RETURN(); |
519 | eda9b09b | bellard | } |
520 | fdf9b3e8 | bellard | |
521 | fdf9b3e8 | bellard | void OPPROTO op_movt_rN(void) |
522 | fdf9b3e8 | bellard | { |
523 | fdf9b3e8 | bellard | env->gregs[PARAM1] = env->sr & SR_T; |
524 | fdf9b3e8 | bellard | RETURN(); |
525 | fdf9b3e8 | bellard | } |
526 | fdf9b3e8 | bellard | |
527 | fdf9b3e8 | bellard | void OPPROTO op_rotcl_Rn(void) |
528 | fdf9b3e8 | bellard | { |
529 | fdf9b3e8 | bellard | helper_rotcl(&env->gregs[PARAM1]); |
530 | fdf9b3e8 | bellard | RETURN(); |
531 | fdf9b3e8 | bellard | } |
532 | fdf9b3e8 | bellard | |
533 | fdf9b3e8 | bellard | void OPPROTO op_rotcr_Rn(void) |
534 | fdf9b3e8 | bellard | { |
535 | fdf9b3e8 | bellard | helper_rotcr(&env->gregs[PARAM1]); |
536 | fdf9b3e8 | bellard | RETURN(); |
537 | fdf9b3e8 | bellard | } |
538 | fdf9b3e8 | bellard | |
539 | fdf9b3e8 | bellard | void OPPROTO op_rotl_Rn(void) |
540 | fdf9b3e8 | bellard | { |
541 | fdf9b3e8 | bellard | cond_t(env->gregs[PARAM1] & 0x80000000);
|
542 | fdf9b3e8 | bellard | env->gregs[PARAM1] = (env->gregs[PARAM1] << 1) | (env->sr & SR_T);
|
543 | fdf9b3e8 | bellard | RETURN(); |
544 | fdf9b3e8 | bellard | } |
545 | fdf9b3e8 | bellard | |
546 | fdf9b3e8 | bellard | void OPPROTO op_rotr_Rn(void) |
547 | fdf9b3e8 | bellard | { |
548 | fdf9b3e8 | bellard | cond_t(env->gregs[PARAM1] & 1);
|
549 | fdf9b3e8 | bellard | env->gregs[PARAM1] = (env->gregs[PARAM1] >> 1) |
|
550 | fdf9b3e8 | bellard | ((env->sr & SR_T) ? 0x80000000 : 0); |
551 | fdf9b3e8 | bellard | RETURN(); |
552 | fdf9b3e8 | bellard | } |
553 | fdf9b3e8 | bellard | |
554 | fdf9b3e8 | bellard | void OPPROTO op_shal_Rn(void) |
555 | fdf9b3e8 | bellard | { |
556 | fdf9b3e8 | bellard | cond_t(env->gregs[PARAM1] & 0x80000000);
|
557 | fdf9b3e8 | bellard | env->gregs[PARAM1] <<= 1;
|
558 | fdf9b3e8 | bellard | RETURN(); |
559 | fdf9b3e8 | bellard | } |
560 | fdf9b3e8 | bellard | |
561 | fdf9b3e8 | bellard | void OPPROTO op_shar_Rn(void) |
562 | fdf9b3e8 | bellard | { |
563 | fdf9b3e8 | bellard | cond_t(env->gregs[PARAM1] & 1);
|
564 | fdf9b3e8 | bellard | *(int32_t *) & env->gregs[PARAM1] >>= 1;
|
565 | fdf9b3e8 | bellard | RETURN(); |
566 | fdf9b3e8 | bellard | } |
567 | fdf9b3e8 | bellard | |
568 | fdf9b3e8 | bellard | void OPPROTO op_shlr_Rn(void) |
569 | fdf9b3e8 | bellard | { |
570 | fdf9b3e8 | bellard | cond_t(env->gregs[PARAM1] & 1);
|
571 | fdf9b3e8 | bellard | *(uint32_t *) & env->gregs[PARAM1] >>= 1;
|
572 | fdf9b3e8 | bellard | RETURN(); |
573 | fdf9b3e8 | bellard | } |
574 | fdf9b3e8 | bellard | |
575 | fdf9b3e8 | bellard | void OPPROTO op_shll2_Rn(void) |
576 | fdf9b3e8 | bellard | { |
577 | fdf9b3e8 | bellard | env->gregs[PARAM1] <<= 2;
|
578 | fdf9b3e8 | bellard | RETURN(); |
579 | fdf9b3e8 | bellard | } |
580 | fdf9b3e8 | bellard | |
581 | fdf9b3e8 | bellard | void OPPROTO op_shll8_Rn(void) |
582 | fdf9b3e8 | bellard | { |
583 | fdf9b3e8 | bellard | env->gregs[PARAM1] <<= 8;
|
584 | fdf9b3e8 | bellard | RETURN(); |
585 | fdf9b3e8 | bellard | } |
586 | fdf9b3e8 | bellard | |
587 | fdf9b3e8 | bellard | void OPPROTO op_shll16_Rn(void) |
588 | fdf9b3e8 | bellard | { |
589 | fdf9b3e8 | bellard | env->gregs[PARAM1] <<= 16;
|
590 | fdf9b3e8 | bellard | RETURN(); |
591 | fdf9b3e8 | bellard | } |
592 | fdf9b3e8 | bellard | |
593 | fdf9b3e8 | bellard | void OPPROTO op_shlr2_Rn(void) |
594 | fdf9b3e8 | bellard | { |
595 | fdf9b3e8 | bellard | *(uint32_t *) & env->gregs[PARAM1] >>= 2;
|
596 | fdf9b3e8 | bellard | RETURN(); |
597 | fdf9b3e8 | bellard | } |
598 | fdf9b3e8 | bellard | |
599 | fdf9b3e8 | bellard | void OPPROTO op_shlr8_Rn(void) |
600 | fdf9b3e8 | bellard | { |
601 | fdf9b3e8 | bellard | *(uint32_t *) & env->gregs[PARAM1] >>= 8;
|
602 | fdf9b3e8 | bellard | RETURN(); |
603 | fdf9b3e8 | bellard | } |
604 | fdf9b3e8 | bellard | |
605 | fdf9b3e8 | bellard | void OPPROTO op_shlr16_Rn(void) |
606 | fdf9b3e8 | bellard | { |
607 | fdf9b3e8 | bellard | *(uint32_t *) & env->gregs[PARAM1] >>= 16;
|
608 | fdf9b3e8 | bellard | RETURN(); |
609 | fdf9b3e8 | bellard | } |
610 | fdf9b3e8 | bellard | |
611 | fdf9b3e8 | bellard | void OPPROTO op_tasb_rN(void) |
612 | fdf9b3e8 | bellard | { |
613 | fdf9b3e8 | bellard | cond_t(*(int8_t *) env->gregs[PARAM1] == 0);
|
614 | fdf9b3e8 | bellard | *(int8_t *) env->gregs[PARAM1] |= 0x80;
|
615 | fdf9b3e8 | bellard | RETURN(); |
616 | fdf9b3e8 | bellard | } |
617 | fdf9b3e8 | bellard | |
618 | fdf9b3e8 | bellard | void OPPROTO op_movl_T0_rN(void) |
619 | fdf9b3e8 | bellard | { |
620 | fdf9b3e8 | bellard | env->gregs[PARAM1] = T0; |
621 | fdf9b3e8 | bellard | RETURN(); |
622 | fdf9b3e8 | bellard | } |
623 | fdf9b3e8 | bellard | |
624 | fdf9b3e8 | bellard | void OPPROTO op_movl_T1_rN(void) |
625 | fdf9b3e8 | bellard | { |
626 | fdf9b3e8 | bellard | env->gregs[PARAM1] = T1; |
627 | fdf9b3e8 | bellard | RETURN(); |
628 | fdf9b3e8 | bellard | } |
629 | fdf9b3e8 | bellard | |
630 | fdf9b3e8 | bellard | void OPPROTO op_movb_rN_T0(void) |
631 | fdf9b3e8 | bellard | { |
632 | fdf9b3e8 | bellard | T0 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
|
633 | fdf9b3e8 | bellard | RETURN(); |
634 | fdf9b3e8 | bellard | } |
635 | fdf9b3e8 | bellard | |
636 | fdf9b3e8 | bellard | void OPPROTO op_movub_rN_T0(void) |
637 | fdf9b3e8 | bellard | { |
638 | fdf9b3e8 | bellard | T0 = env->gregs[PARAM1] & 0xff;
|
639 | fdf9b3e8 | bellard | RETURN(); |
640 | fdf9b3e8 | bellard | } |
641 | fdf9b3e8 | bellard | |
642 | fdf9b3e8 | bellard | void OPPROTO op_movw_rN_T0(void) |
643 | fdf9b3e8 | bellard | { |
644 | fdf9b3e8 | bellard | T0 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
|
645 | fdf9b3e8 | bellard | RETURN(); |
646 | fdf9b3e8 | bellard | } |
647 | fdf9b3e8 | bellard | |
648 | fdf9b3e8 | bellard | void OPPROTO op_movuw_rN_T0(void) |
649 | fdf9b3e8 | bellard | { |
650 | fdf9b3e8 | bellard | T0 = env->gregs[PARAM1] & 0xffff;
|
651 | fdf9b3e8 | bellard | RETURN(); |
652 | fdf9b3e8 | bellard | } |
653 | fdf9b3e8 | bellard | |
654 | fdf9b3e8 | bellard | void OPPROTO op_movl_rN_T0(void) |
655 | fdf9b3e8 | bellard | { |
656 | fdf9b3e8 | bellard | T0 = env->gregs[PARAM1]; |
657 | fdf9b3e8 | bellard | RETURN(); |
658 | fdf9b3e8 | bellard | } |
659 | fdf9b3e8 | bellard | |
660 | fdf9b3e8 | bellard | void OPPROTO op_movb_rN_T1(void) |
661 | fdf9b3e8 | bellard | { |
662 | fdf9b3e8 | bellard | T1 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
|
663 | fdf9b3e8 | bellard | RETURN(); |
664 | fdf9b3e8 | bellard | } |
665 | fdf9b3e8 | bellard | |
666 | fdf9b3e8 | bellard | void OPPROTO op_movub_rN_T1(void) |
667 | fdf9b3e8 | bellard | { |
668 | fdf9b3e8 | bellard | T1 = env->gregs[PARAM1] & 0xff;
|
669 | fdf9b3e8 | bellard | RETURN(); |
670 | fdf9b3e8 | bellard | } |
671 | fdf9b3e8 | bellard | |
672 | fdf9b3e8 | bellard | void OPPROTO op_movw_rN_T1(void) |
673 | fdf9b3e8 | bellard | { |
674 | fdf9b3e8 | bellard | T1 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
|
675 | fdf9b3e8 | bellard | RETURN(); |
676 | fdf9b3e8 | bellard | } |
677 | fdf9b3e8 | bellard | |
678 | fdf9b3e8 | bellard | void OPPROTO op_movuw_rN_T1(void) |
679 | fdf9b3e8 | bellard | { |
680 | fdf9b3e8 | bellard | T1 = env->gregs[PARAM1] & 0xffff;
|
681 | fdf9b3e8 | bellard | RETURN(); |
682 | fdf9b3e8 | bellard | } |
683 | fdf9b3e8 | bellard | |
684 | fdf9b3e8 | bellard | void OPPROTO op_movl_rN_T1(void) |
685 | fdf9b3e8 | bellard | { |
686 | fdf9b3e8 | bellard | T1 = env->gregs[PARAM1]; |
687 | fdf9b3e8 | bellard | RETURN(); |
688 | fdf9b3e8 | bellard | } |
689 | fdf9b3e8 | bellard | |
690 | fdf9b3e8 | bellard | void OPPROTO op_movl_imm_rN(void) |
691 | fdf9b3e8 | bellard | { |
692 | fdf9b3e8 | bellard | env->gregs[PARAM2] = PARAM1; |
693 | fdf9b3e8 | bellard | RETURN(); |
694 | fdf9b3e8 | bellard | } |
695 | fdf9b3e8 | bellard | |
696 | eda9b09b | bellard | void OPPROTO op_fmov_frN_FT0(void) |
697 | eda9b09b | bellard | { |
698 | eda9b09b | bellard | FT0 = *(float32 *)&env->fregs[PARAM1]; |
699 | eda9b09b | bellard | RETURN(); |
700 | eda9b09b | bellard | } |
701 | eda9b09b | bellard | |
702 | eda9b09b | bellard | void OPPROTO op_fmov_drN_DT0(void) |
703 | eda9b09b | bellard | { |
704 | eda9b09b | bellard | DT0 = *(float64 *)&env->fregs[PARAM1]; |
705 | eda9b09b | bellard | RETURN(); |
706 | eda9b09b | bellard | } |
707 | eda9b09b | bellard | |
708 | eda9b09b | bellard | void OPPROTO op_fmov_FT0_frN(void) |
709 | eda9b09b | bellard | { |
710 | eda9b09b | bellard | *(float32 *)&env->fregs[PARAM1] = FT0; |
711 | eda9b09b | bellard | RETURN(); |
712 | eda9b09b | bellard | } |
713 | eda9b09b | bellard | |
714 | eda9b09b | bellard | void OPPROTO op_fmov_DT0_drN(void) |
715 | eda9b09b | bellard | { |
716 | eda9b09b | bellard | *(float64 *)&env->fregs[PARAM1] = DT0; |
717 | eda9b09b | bellard | RETURN(); |
718 | eda9b09b | bellard | } |
719 | eda9b09b | bellard | |
720 | fdf9b3e8 | bellard | void OPPROTO op_dec1_rN(void) |
721 | fdf9b3e8 | bellard | { |
722 | fdf9b3e8 | bellard | env->gregs[PARAM1] -= 1;
|
723 | fdf9b3e8 | bellard | RETURN(); |
724 | fdf9b3e8 | bellard | } |
725 | fdf9b3e8 | bellard | |
726 | fdf9b3e8 | bellard | void OPPROTO op_dec2_rN(void) |
727 | fdf9b3e8 | bellard | { |
728 | fdf9b3e8 | bellard | env->gregs[PARAM1] -= 2;
|
729 | fdf9b3e8 | bellard | RETURN(); |
730 | fdf9b3e8 | bellard | } |
731 | fdf9b3e8 | bellard | |
732 | fdf9b3e8 | bellard | void OPPROTO op_dec4_rN(void) |
733 | fdf9b3e8 | bellard | { |
734 | fdf9b3e8 | bellard | env->gregs[PARAM1] -= 4;
|
735 | fdf9b3e8 | bellard | RETURN(); |
736 | fdf9b3e8 | bellard | } |
737 | fdf9b3e8 | bellard | |
738 | eda9b09b | bellard | void OPPROTO op_dec8_rN(void) |
739 | eda9b09b | bellard | { |
740 | eda9b09b | bellard | env->gregs[PARAM1] -= 4;
|
741 | eda9b09b | bellard | RETURN(); |
742 | eda9b09b | bellard | } |
743 | eda9b09b | bellard | |
744 | fdf9b3e8 | bellard | void OPPROTO op_inc1_rN(void) |
745 | fdf9b3e8 | bellard | { |
746 | fdf9b3e8 | bellard | env->gregs[PARAM1] += 1;
|
747 | fdf9b3e8 | bellard | RETURN(); |
748 | fdf9b3e8 | bellard | } |
749 | fdf9b3e8 | bellard | |
750 | fdf9b3e8 | bellard | void OPPROTO op_inc2_rN(void) |
751 | fdf9b3e8 | bellard | { |
752 | fdf9b3e8 | bellard | env->gregs[PARAM1] += 2;
|
753 | fdf9b3e8 | bellard | RETURN(); |
754 | fdf9b3e8 | bellard | } |
755 | fdf9b3e8 | bellard | |
756 | fdf9b3e8 | bellard | void OPPROTO op_inc4_rN(void) |
757 | fdf9b3e8 | bellard | { |
758 | fdf9b3e8 | bellard | env->gregs[PARAM1] += 4;
|
759 | fdf9b3e8 | bellard | RETURN(); |
760 | fdf9b3e8 | bellard | } |
761 | fdf9b3e8 | bellard | |
762 | eda9b09b | bellard | void OPPROTO op_inc8_rN(void) |
763 | eda9b09b | bellard | { |
764 | eda9b09b | bellard | env->gregs[PARAM1] += 4;
|
765 | eda9b09b | bellard | RETURN(); |
766 | eda9b09b | bellard | } |
767 | eda9b09b | bellard | |
768 | fdf9b3e8 | bellard | void OPPROTO op_add_T0_rN(void) |
769 | fdf9b3e8 | bellard | { |
770 | fdf9b3e8 | bellard | env->gregs[PARAM1] += T0; |
771 | fdf9b3e8 | bellard | RETURN(); |
772 | fdf9b3e8 | bellard | } |
773 | fdf9b3e8 | bellard | |
774 | fdf9b3e8 | bellard | void OPPROTO op_sub_T0_rN(void) |
775 | fdf9b3e8 | bellard | { |
776 | fdf9b3e8 | bellard | env->gregs[PARAM1] -= T0; |
777 | fdf9b3e8 | bellard | RETURN(); |
778 | fdf9b3e8 | bellard | } |
779 | fdf9b3e8 | bellard | |
780 | fdf9b3e8 | bellard | void OPPROTO op_and_T0_rN(void) |
781 | fdf9b3e8 | bellard | { |
782 | fdf9b3e8 | bellard | env->gregs[PARAM1] &= T0; |
783 | fdf9b3e8 | bellard | RETURN(); |
784 | fdf9b3e8 | bellard | } |
785 | fdf9b3e8 | bellard | |
786 | fdf9b3e8 | bellard | void OPPROTO op_or_T0_rN(void) |
787 | fdf9b3e8 | bellard | { |
788 | fdf9b3e8 | bellard | env->gregs[PARAM1] |= T0; |
789 | fdf9b3e8 | bellard | RETURN(); |
790 | fdf9b3e8 | bellard | } |
791 | fdf9b3e8 | bellard | |
792 | fdf9b3e8 | bellard | void OPPROTO op_xor_T0_rN(void) |
793 | fdf9b3e8 | bellard | { |
794 | fdf9b3e8 | bellard | env->gregs[PARAM1] ^= T0; |
795 | fdf9b3e8 | bellard | RETURN(); |
796 | fdf9b3e8 | bellard | } |
797 | fdf9b3e8 | bellard | |
798 | fdf9b3e8 | bellard | void OPPROTO op_add_rN_T0(void) |
799 | fdf9b3e8 | bellard | { |
800 | fdf9b3e8 | bellard | T0 += env->gregs[PARAM1]; |
801 | fdf9b3e8 | bellard | RETURN(); |
802 | fdf9b3e8 | bellard | } |
803 | fdf9b3e8 | bellard | |
804 | fdf9b3e8 | bellard | void OPPROTO op_add_rN_T1(void) |
805 | fdf9b3e8 | bellard | { |
806 | fdf9b3e8 | bellard | T1 += env->gregs[PARAM1]; |
807 | fdf9b3e8 | bellard | RETURN(); |
808 | fdf9b3e8 | bellard | } |
809 | fdf9b3e8 | bellard | |
810 | fdf9b3e8 | bellard | void OPPROTO op_add_imm_rN(void) |
811 | fdf9b3e8 | bellard | { |
812 | fdf9b3e8 | bellard | env->gregs[PARAM2] += PARAM1; |
813 | fdf9b3e8 | bellard | RETURN(); |
814 | fdf9b3e8 | bellard | } |
815 | fdf9b3e8 | bellard | |
816 | fdf9b3e8 | bellard | void OPPROTO op_and_imm_rN(void) |
817 | fdf9b3e8 | bellard | { |
818 | fdf9b3e8 | bellard | env->gregs[PARAM2] &= PARAM1; |
819 | fdf9b3e8 | bellard | RETURN(); |
820 | fdf9b3e8 | bellard | } |
821 | fdf9b3e8 | bellard | |
822 | fdf9b3e8 | bellard | void OPPROTO op_or_imm_rN(void) |
823 | fdf9b3e8 | bellard | { |
824 | fdf9b3e8 | bellard | env->gregs[PARAM2] |= PARAM1; |
825 | fdf9b3e8 | bellard | RETURN(); |
826 | fdf9b3e8 | bellard | } |
827 | fdf9b3e8 | bellard | |
828 | fdf9b3e8 | bellard | void OPPROTO op_xor_imm_rN(void) |
829 | fdf9b3e8 | bellard | { |
830 | fdf9b3e8 | bellard | env->gregs[PARAM2] ^= PARAM1; |
831 | fdf9b3e8 | bellard | RETURN(); |
832 | fdf9b3e8 | bellard | } |
833 | fdf9b3e8 | bellard | |
834 | fdf9b3e8 | bellard | void OPPROTO op_dt_rN(void) |
835 | fdf9b3e8 | bellard | { |
836 | fdf9b3e8 | bellard | cond_t((--env->gregs[PARAM1]) == 0);
|
837 | fdf9b3e8 | bellard | RETURN(); |
838 | fdf9b3e8 | bellard | } |
839 | fdf9b3e8 | bellard | |
840 | fdf9b3e8 | bellard | void OPPROTO op_tst_imm_rN(void) |
841 | fdf9b3e8 | bellard | { |
842 | fdf9b3e8 | bellard | cond_t((env->gregs[PARAM2] & PARAM1) == 0);
|
843 | fdf9b3e8 | bellard | RETURN(); |
844 | fdf9b3e8 | bellard | } |
845 | fdf9b3e8 | bellard | |
846 | fdf9b3e8 | bellard | void OPPROTO op_movl_T0_T1(void) |
847 | fdf9b3e8 | bellard | { |
848 | fdf9b3e8 | bellard | T1 = T0; |
849 | fdf9b3e8 | bellard | RETURN(); |
850 | fdf9b3e8 | bellard | } |
851 | fdf9b3e8 | bellard | |
852 | eda9b09b | bellard | void OPPROTO op_movl_fpul_FT0(void) |
853 | eda9b09b | bellard | { |
854 | eda9b09b | bellard | FT0 = *(float32 *)&env->fpul; |
855 | eda9b09b | bellard | RETURN(); |
856 | eda9b09b | bellard | } |
857 | eda9b09b | bellard | |
858 | eda9b09b | bellard | void OPPROTO op_movl_FT0_fpul(void) |
859 | eda9b09b | bellard | { |
860 | eda9b09b | bellard | *(float32 *)&env->fpul = FT0; |
861 | eda9b09b | bellard | RETURN(); |
862 | eda9b09b | bellard | } |
863 | eda9b09b | bellard | |
864 | fdf9b3e8 | bellard | void OPPROTO op_goto_tb0(void) |
865 | fdf9b3e8 | bellard | { |
866 | fdf9b3e8 | bellard | GOTO_TB(op_goto_tb0, PARAM1, 0);
|
867 | fdf9b3e8 | bellard | RETURN(); |
868 | fdf9b3e8 | bellard | } |
869 | fdf9b3e8 | bellard | |
870 | fdf9b3e8 | bellard | void OPPROTO op_goto_tb1(void) |
871 | fdf9b3e8 | bellard | { |
872 | fdf9b3e8 | bellard | GOTO_TB(op_goto_tb1, PARAM1, 1);
|
873 | fdf9b3e8 | bellard | RETURN(); |
874 | fdf9b3e8 | bellard | } |
875 | fdf9b3e8 | bellard | |
876 | fdf9b3e8 | bellard | void OPPROTO op_movl_imm_PC(void) |
877 | fdf9b3e8 | bellard | { |
878 | fdf9b3e8 | bellard | env->pc = PARAM1; |
879 | fdf9b3e8 | bellard | RETURN(); |
880 | fdf9b3e8 | bellard | } |
881 | fdf9b3e8 | bellard | |
882 | fdf9b3e8 | bellard | void OPPROTO op_jT(void) |
883 | fdf9b3e8 | bellard | { |
884 | fdf9b3e8 | bellard | if (env->sr & SR_T)
|
885 | fdf9b3e8 | bellard | GOTO_LABEL_PARAM(1);
|
886 | fdf9b3e8 | bellard | RETURN(); |
887 | fdf9b3e8 | bellard | } |
888 | fdf9b3e8 | bellard | |
889 | 9c2a9ea1 | pbrook | void OPPROTO op_jdelayed(void) |
890 | fdf9b3e8 | bellard | { |
891 | 9c2a9ea1 | pbrook | uint32_t flags; |
892 | 9c2a9ea1 | pbrook | flags = env->flags; |
893 | 9c2a9ea1 | pbrook | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
894 | 9c2a9ea1 | pbrook | if (flags & DELAY_SLOT)
|
895 | fdf9b3e8 | bellard | GOTO_LABEL_PARAM(1);
|
896 | fdf9b3e8 | bellard | RETURN(); |
897 | fdf9b3e8 | bellard | } |
898 | fdf9b3e8 | bellard | |
899 | fdf9b3e8 | bellard | void OPPROTO op_movl_delayed_pc_PC(void) |
900 | fdf9b3e8 | bellard | { |
901 | fdf9b3e8 | bellard | env->pc = env->delayed_pc; |
902 | fdf9b3e8 | bellard | RETURN(); |
903 | fdf9b3e8 | bellard | } |
904 | fdf9b3e8 | bellard | |
905 | fdf9b3e8 | bellard | void OPPROTO op_addl_GBR_T0(void) |
906 | fdf9b3e8 | bellard | { |
907 | fdf9b3e8 | bellard | T0 += env->gbr; |
908 | fdf9b3e8 | bellard | RETURN(); |
909 | fdf9b3e8 | bellard | } |
910 | fdf9b3e8 | bellard | |
911 | fdf9b3e8 | bellard | void OPPROTO op_and_imm_T0(void) |
912 | fdf9b3e8 | bellard | { |
913 | fdf9b3e8 | bellard | T0 &= PARAM1; |
914 | fdf9b3e8 | bellard | RETURN(); |
915 | fdf9b3e8 | bellard | } |
916 | fdf9b3e8 | bellard | |
917 | fdf9b3e8 | bellard | void OPPROTO op_or_imm_T0(void) |
918 | fdf9b3e8 | bellard | { |
919 | fdf9b3e8 | bellard | T0 |= PARAM1; |
920 | fdf9b3e8 | bellard | RETURN(); |
921 | fdf9b3e8 | bellard | } |
922 | fdf9b3e8 | bellard | |
923 | fdf9b3e8 | bellard | void OPPROTO op_xor_imm_T0(void) |
924 | fdf9b3e8 | bellard | { |
925 | fdf9b3e8 | bellard | T0 ^= PARAM1; |
926 | fdf9b3e8 | bellard | RETURN(); |
927 | fdf9b3e8 | bellard | } |
928 | fdf9b3e8 | bellard | |
929 | fdf9b3e8 | bellard | void OPPROTO op_tst_imm_T0(void) |
930 | fdf9b3e8 | bellard | { |
931 | fdf9b3e8 | bellard | cond_t((T0 & PARAM1) == 0);
|
932 | fdf9b3e8 | bellard | RETURN(); |
933 | fdf9b3e8 | bellard | } |
934 | fdf9b3e8 | bellard | |
935 | fdf9b3e8 | bellard | void OPPROTO op_raise_illegal_instruction(void) |
936 | fdf9b3e8 | bellard | { |
937 | fdf9b3e8 | bellard | env->exception_index = 0x180;
|
938 | fdf9b3e8 | bellard | do_raise_exception(); |
939 | fdf9b3e8 | bellard | RETURN(); |
940 | fdf9b3e8 | bellard | } |
941 | fdf9b3e8 | bellard | |
942 | fdf9b3e8 | bellard | void OPPROTO op_raise_slot_illegal_instruction(void) |
943 | fdf9b3e8 | bellard | { |
944 | fdf9b3e8 | bellard | env->exception_index = 0x1a0;
|
945 | fdf9b3e8 | bellard | do_raise_exception(); |
946 | fdf9b3e8 | bellard | RETURN(); |
947 | fdf9b3e8 | bellard | } |
948 | fdf9b3e8 | bellard | |
949 | fdf9b3e8 | bellard | void OPPROTO op_debug(void) |
950 | fdf9b3e8 | bellard | { |
951 | fdf9b3e8 | bellard | env->exception_index = EXCP_DEBUG; |
952 | fdf9b3e8 | bellard | cpu_loop_exit(); |
953 | fdf9b3e8 | bellard | } |
954 | fdf9b3e8 | bellard | |
955 | fdf9b3e8 | bellard | /* Load and store */
|
956 | fdf9b3e8 | bellard | #define MEMSUFFIX _raw
|
957 | fdf9b3e8 | bellard | #include "op_mem.c" |
958 | fdf9b3e8 | bellard | #undef MEMSUFFIX
|
959 | fdf9b3e8 | bellard | #if !defined(CONFIG_USER_ONLY)
|
960 | fdf9b3e8 | bellard | #define MEMSUFFIX _user
|
961 | fdf9b3e8 | bellard | #include "op_mem.c" |
962 | fdf9b3e8 | bellard | #undef MEMSUFFIX
|
963 | fdf9b3e8 | bellard | |
964 | fdf9b3e8 | bellard | #define MEMSUFFIX _kernel
|
965 | fdf9b3e8 | bellard | #include "op_mem.c" |
966 | fdf9b3e8 | bellard | #undef MEMSUFFIX
|
967 | fdf9b3e8 | bellard | #endif |