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/*
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 * QEMU System Emulator header
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 * 
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 * Copyright (c) 2003 Fabrice Bellard
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 * 
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#ifndef VL_H
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#define VL_H
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/* we put basic includes here to avoid repeating them in device drivers */
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <time.h>
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#include <ctype.h>
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#include <errno.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <sys/stat.h>
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#ifndef O_LARGEFILE
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#define O_LARGEFILE 0
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#endif
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#ifndef O_BINARY
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#define O_BINARY 0
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#endif
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#ifndef ENOMEDIUM
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#define ENOMEDIUM ENODEV
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#endif
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#ifdef _WIN32
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#include <windows.h>
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#define fsync _commit
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#define lseek _lseeki64
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#define ENOTSUP 4096
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extern int qemu_ftruncate64(int, int64_t);
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#define ftruncate qemu_ftruncate64
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static inline char *realpath(const char *path, char *resolved_path)
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{
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    _fullpath(resolved_path, path, _MAX_PATH);
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    return resolved_path;
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}
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#define PRId64 "I64d"
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#define PRIx64 "I64x"
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#define PRIu64 "I64u"
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#define PRIo64 "I64o"
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#endif
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#ifdef QEMU_TOOL
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/* we use QEMU_TOOL in the command line tools which do not depend on
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   the target CPU type */
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#include "config-host.h"
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#include <setjmp.h>
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#include "osdep.h"
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#include "bswap.h"
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#else
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#include "audio/audio.h"
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#include "cpu.h"
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#endif /* !defined(QEMU_TOOL) */
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#ifndef glue
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#define xglue(x, y) x ## y
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#define glue(x, y) xglue(x, y)
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#define stringify(s)        tostring(s)
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#define tostring(s)        #s
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a) < (b)) ? (a) : (b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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#endif
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/* cutils.c */
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void pstrcpy(char *buf, int buf_size, const char *str);
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char *pstrcat(char *buf, int buf_size, const char *s);
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int strstart(const char *str, const char *val, const char **ptr);
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int stristart(const char *str, const char *val, const char **ptr);
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/* vl.c */
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uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
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void hw_error(const char *fmt, ...);
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extern const char *bios_dir;
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extern int vm_running;
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extern const char *qemu_name;
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typedef struct vm_change_state_entry VMChangeStateEntry;
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typedef void VMChangeStateHandler(void *opaque, int running);
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typedef void VMStopHandler(void *opaque, int reason);
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VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
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                                                     void *opaque);
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void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
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int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void vm_start(void);
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void vm_stop(int reason);
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typedef void QEMUResetHandler(void *opaque);
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void qemu_register_reset(QEMUResetHandler *func, void *opaque);
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void qemu_system_reset_request(void);
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void qemu_system_shutdown_request(void);
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void qemu_system_powerdown_request(void);
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#if !defined(TARGET_SPARC)
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// Please implement a power failure function to signal the OS
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#define qemu_system_powerdown() do{}while(0)
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#else
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void qemu_system_powerdown(void);
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#endif
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void main_loop_wait(int timeout);
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extern int ram_size;
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extern int bios_size;
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extern int rtc_utc;
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extern int cirrus_vga_enabled;
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extern int graphic_width;
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extern int graphic_height;
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extern int graphic_depth;
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extern const char *keyboard_layout;
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extern int kqemu_allowed;
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extern int win2k_install_hack;
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extern int usb_enabled;
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extern int smp_cpus;
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extern int no_quit;
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extern int semihosting_enabled;
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extern int autostart;
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extern const char *bootp_filename;
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#define MAX_OPTION_ROMS 16
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extern const char *option_rom[MAX_OPTION_ROMS];
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extern int nb_option_roms;
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/* XXX: make it dynamic */
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#define MAX_BIOS_SIZE (4 * 1024 * 1024)
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#if defined (TARGET_PPC) || defined (TARGET_SPARC64)
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#define BIOS_SIZE ((512 + 32) * 1024)
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#elif defined(TARGET_MIPS)
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#define BIOS_SIZE (4 * 1024 * 1024)
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#endif
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/* keyboard/mouse support */
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#define MOUSE_EVENT_LBUTTON 0x01
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#define MOUSE_EVENT_RBUTTON 0x02
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#define MOUSE_EVENT_MBUTTON 0x04
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typedef void QEMUPutKBDEvent(void *opaque, int keycode);
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typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
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typedef struct QEMUPutMouseEntry {
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    QEMUPutMouseEvent *qemu_put_mouse_event;
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    void *qemu_put_mouse_event_opaque;
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    int qemu_put_mouse_event_absolute;
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    char *qemu_put_mouse_event_name;
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    /* used internally by qemu for handling mice */
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    struct QEMUPutMouseEntry *next;
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} QEMUPutMouseEntry;
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void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
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QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
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                                                void *opaque, int absolute,
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                                                const char *name);
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void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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void kbd_put_keycode(int keycode);
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
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int kbd_mouse_is_absolute(void);
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void do_info_mice(void);
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void do_mouse_set(int index);
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/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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   constants) */
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#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
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#define QEMU_KEY_BACKSPACE  0x007f
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#define QEMU_KEY_UP         QEMU_KEY_ESC1('A')
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#define QEMU_KEY_DOWN       QEMU_KEY_ESC1('B')
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#define QEMU_KEY_RIGHT      QEMU_KEY_ESC1('C')
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#define QEMU_KEY_LEFT       QEMU_KEY_ESC1('D')
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#define QEMU_KEY_HOME       QEMU_KEY_ESC1(1)
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#define QEMU_KEY_END        QEMU_KEY_ESC1(4)
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#define QEMU_KEY_PAGEUP     QEMU_KEY_ESC1(5)
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#define QEMU_KEY_PAGEDOWN   QEMU_KEY_ESC1(6)
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#define QEMU_KEY_DELETE     QEMU_KEY_ESC1(3)
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#define QEMU_KEY_CTRL_UP         0xe400
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#define QEMU_KEY_CTRL_DOWN       0xe401
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#define QEMU_KEY_CTRL_LEFT       0xe402
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#define QEMU_KEY_CTRL_RIGHT      0xe403
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#define QEMU_KEY_CTRL_HOME       0xe404
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#define QEMU_KEY_CTRL_END        0xe405
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#define QEMU_KEY_CTRL_PAGEUP     0xe406
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#define QEMU_KEY_CTRL_PAGEDOWN   0xe407
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void kbd_put_keysym(int keysym);
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/* async I/O support */
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typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
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typedef int IOCanRWHandler(void *opaque);
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typedef void IOHandler(void *opaque);
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int qemu_set_fd_handler2(int fd, 
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                         IOCanRWHandler *fd_read_poll, 
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                         IOHandler *fd_read, 
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                         IOHandler *fd_write, 
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                         void *opaque);
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int qemu_set_fd_handler(int fd,
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                        IOHandler *fd_read, 
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                        IOHandler *fd_write,
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                        void *opaque);
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/* Polling handling */
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/* return TRUE if no sleep should be done afterwards */
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typedef int PollingFunc(void *opaque);
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int qemu_add_polling_cb(PollingFunc *func, void *opaque);
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void qemu_del_polling_cb(PollingFunc *func, void *opaque);
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#ifdef _WIN32
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/* Wait objects handling */
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typedef void WaitObjectFunc(void *opaque);
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int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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#endif
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typedef struct QEMUBH QEMUBH;
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/* character device */
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#define CHR_EVENT_BREAK 0 /* serial break char */
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#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
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#define CHR_EVENT_RESET 2 /* new connection established */
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#define CHR_IOCTL_SERIAL_SET_PARAMS   1
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typedef struct {
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    int speed;
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    int parity;
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    int data_bits;
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    int stop_bits;
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} QEMUSerialSetParams;
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#define CHR_IOCTL_SERIAL_SET_BREAK    2
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#define CHR_IOCTL_PP_READ_DATA        3
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#define CHR_IOCTL_PP_WRITE_DATA       4
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#define CHR_IOCTL_PP_READ_CONTROL     5
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#define CHR_IOCTL_PP_WRITE_CONTROL    6
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#define CHR_IOCTL_PP_READ_STATUS      7
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#define CHR_IOCTL_PP_EPP_READ_ADDR    8
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#define CHR_IOCTL_PP_EPP_READ         9
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#define CHR_IOCTL_PP_EPP_WRITE_ADDR  10
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#define CHR_IOCTL_PP_EPP_WRITE       11
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typedef void IOEventHandler(void *opaque, int event);
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typedef struct CharDriverState {
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    int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
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    void (*chr_update_read_handler)(struct CharDriverState *s);
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    int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
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    IOEventHandler *chr_event;
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    IOCanRWHandler *chr_can_read;
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    IOReadHandler *chr_read;
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    void *handler_opaque;
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    void (*chr_send_event)(struct CharDriverState *chr, int event);
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    void (*chr_close)(struct CharDriverState *chr);
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    void *opaque;
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    int focus;
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    QEMUBH *bh;
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} CharDriverState;
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CharDriverState *qemu_chr_open(const char *filename);
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void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
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int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
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void qemu_chr_send_event(CharDriverState *s, int event);
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void qemu_chr_add_handlers(CharDriverState *s, 
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                           IOCanRWHandler *fd_can_read, 
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                           IOReadHandler *fd_read,
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                           IOEventHandler *fd_event,
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                           void *opaque);
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int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
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void qemu_chr_reset(CharDriverState *s);
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int qemu_chr_can_read(CharDriverState *s);
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void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
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/* consoles */
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typedef struct DisplayState DisplayState;
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typedef struct TextConsole TextConsole;
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typedef void (*vga_hw_update_ptr)(void *);
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typedef void (*vga_hw_invalidate_ptr)(void *);
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typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
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TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
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                                  vga_hw_invalidate_ptr invalidate,
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                                  vga_hw_screen_dump_ptr screen_dump,
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                                  void *opaque);
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void vga_hw_update(void);
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void vga_hw_invalidate(void);
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void vga_hw_screen_dump(const char *filename);
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int is_graphic_console(void);
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CharDriverState *text_console_init(DisplayState *ds);
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void console_select(unsigned int index);
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/* serial ports */
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#define MAX_SERIAL_PORTS 4
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extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
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/* parallel ports */
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#define MAX_PARALLEL_PORTS 3
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extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
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struct ParallelIOArg {
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    void *buffer;
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    int count;
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};
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/* VLANs support */
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typedef struct VLANClientState VLANClientState;
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struct VLANClientState {
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    IOReadHandler *fd_read;
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    /* Packets may still be sent if this returns zero.  It's used to
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       rate-limit the slirp code.  */
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    IOCanRWHandler *fd_can_read;
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    void *opaque;
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    struct VLANClientState *next;
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    struct VLANState *vlan;
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    char info_str[256];
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};
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typedef struct VLANState {
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    int id;
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    VLANClientState *first_client;
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    struct VLANState *next;
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} VLANState;
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VLANState *qemu_find_vlan(int id);
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VLANClientState *qemu_new_vlan_client(VLANState *vlan,
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                                      IOReadHandler *fd_read,
388 d861b05e pbrook
                                      IOCanRWHandler *fd_can_read,
389 d861b05e pbrook
                                      void *opaque);
390 d861b05e pbrook
int qemu_can_send_packet(VLANClientState *vc);
391 7c9d8e07 bellard
void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
392 d861b05e pbrook
void qemu_handler_true(void *opaque);
393 7c9d8e07 bellard
394 7c9d8e07 bellard
void do_info_network(void);
395 7c9d8e07 bellard
396 7fb843f8 bellard
/* TAP win32 */
397 7fb843f8 bellard
int tap_win32_init(VLANState *vlan, const char *ifname);
398 7fb843f8 bellard
399 7c9d8e07 bellard
/* NIC info */
400 c4b1fcc0 bellard
401 c4b1fcc0 bellard
#define MAX_NICS 8
402 c4b1fcc0 bellard
403 7c9d8e07 bellard
typedef struct NICInfo {
404 c4b1fcc0 bellard
    uint8_t macaddr[6];
405 a41b2ff2 pbrook
    const char *model;
406 7c9d8e07 bellard
    VLANState *vlan;
407 7c9d8e07 bellard
} NICInfo;
408 c4b1fcc0 bellard
409 c4b1fcc0 bellard
extern int nb_nics;
410 7c9d8e07 bellard
extern NICInfo nd_table[MAX_NICS];
411 8a7ddc38 bellard
412 8a7ddc38 bellard
/* timers */
413 8a7ddc38 bellard
414 8a7ddc38 bellard
typedef struct QEMUClock QEMUClock;
415 8a7ddc38 bellard
typedef struct QEMUTimer QEMUTimer;
416 8a7ddc38 bellard
typedef void QEMUTimerCB(void *opaque);
417 8a7ddc38 bellard
418 8a7ddc38 bellard
/* The real time clock should be used only for stuff which does not
419 8a7ddc38 bellard
   change the virtual machine state, as it is run even if the virtual
420 69b91039 bellard
   machine is stopped. The real time clock has a frequency of 1000
421 8a7ddc38 bellard
   Hz. */
422 8a7ddc38 bellard
extern QEMUClock *rt_clock;
423 8a7ddc38 bellard
424 e80cfcfc bellard
/* The virtual clock is only run during the emulation. It is stopped
425 8a7ddc38 bellard
   when the virtual machine is stopped. Virtual timers use a high
426 8a7ddc38 bellard
   precision clock, usually cpu cycles (use ticks_per_sec). */
427 8a7ddc38 bellard
extern QEMUClock *vm_clock;
428 8a7ddc38 bellard
429 8a7ddc38 bellard
int64_t qemu_get_clock(QEMUClock *clock);
430 8a7ddc38 bellard
431 8a7ddc38 bellard
QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
432 8a7ddc38 bellard
void qemu_free_timer(QEMUTimer *ts);
433 8a7ddc38 bellard
void qemu_del_timer(QEMUTimer *ts);
434 8a7ddc38 bellard
void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
435 8a7ddc38 bellard
int qemu_timer_pending(QEMUTimer *ts);
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extern int64_t ticks_per_sec;
438 8a7ddc38 bellard
extern int pit_min_timer_count;
439 8a7ddc38 bellard
440 1dce7c3c bellard
int64_t cpu_get_ticks(void);
441 8a7ddc38 bellard
void cpu_enable_ticks(void);
442 8a7ddc38 bellard
void cpu_disable_ticks(void);
443 8a7ddc38 bellard
444 8a7ddc38 bellard
/* VM Load/Save */
445 8a7ddc38 bellard
446 faea38e7 bellard
typedef struct QEMUFile QEMUFile;
447 8a7ddc38 bellard
448 faea38e7 bellard
QEMUFile *qemu_fopen(const char *filename, const char *mode);
449 faea38e7 bellard
void qemu_fflush(QEMUFile *f);
450 faea38e7 bellard
void qemu_fclose(QEMUFile *f);
451 8a7ddc38 bellard
void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
452 8a7ddc38 bellard
void qemu_put_byte(QEMUFile *f, int v);
453 8a7ddc38 bellard
void qemu_put_be16(QEMUFile *f, unsigned int v);
454 8a7ddc38 bellard
void qemu_put_be32(QEMUFile *f, unsigned int v);
455 8a7ddc38 bellard
void qemu_put_be64(QEMUFile *f, uint64_t v);
456 8a7ddc38 bellard
int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
457 8a7ddc38 bellard
int qemu_get_byte(QEMUFile *f);
458 8a7ddc38 bellard
unsigned int qemu_get_be16(QEMUFile *f);
459 8a7ddc38 bellard
unsigned int qemu_get_be32(QEMUFile *f);
460 8a7ddc38 bellard
uint64_t qemu_get_be64(QEMUFile *f);
461 8a7ddc38 bellard
462 8a7ddc38 bellard
static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
463 8a7ddc38 bellard
{
464 8a7ddc38 bellard
    qemu_put_be64(f, *pv);
465 8a7ddc38 bellard
}
466 8a7ddc38 bellard
467 8a7ddc38 bellard
static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
468 8a7ddc38 bellard
{
469 8a7ddc38 bellard
    qemu_put_be32(f, *pv);
470 8a7ddc38 bellard
}
471 8a7ddc38 bellard
472 8a7ddc38 bellard
static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
473 8a7ddc38 bellard
{
474 8a7ddc38 bellard
    qemu_put_be16(f, *pv);
475 8a7ddc38 bellard
}
476 8a7ddc38 bellard
477 8a7ddc38 bellard
static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
478 8a7ddc38 bellard
{
479 8a7ddc38 bellard
    qemu_put_byte(f, *pv);
480 8a7ddc38 bellard
}
481 8a7ddc38 bellard
482 8a7ddc38 bellard
static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
483 8a7ddc38 bellard
{
484 8a7ddc38 bellard
    *pv = qemu_get_be64(f);
485 8a7ddc38 bellard
}
486 8a7ddc38 bellard
487 8a7ddc38 bellard
static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
488 8a7ddc38 bellard
{
489 8a7ddc38 bellard
    *pv = qemu_get_be32(f);
490 8a7ddc38 bellard
}
491 8a7ddc38 bellard
492 8a7ddc38 bellard
static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
493 8a7ddc38 bellard
{
494 8a7ddc38 bellard
    *pv = qemu_get_be16(f);
495 8a7ddc38 bellard
}
496 8a7ddc38 bellard
497 8a7ddc38 bellard
static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
498 8a7ddc38 bellard
{
499 8a7ddc38 bellard
    *pv = qemu_get_byte(f);
500 8a7ddc38 bellard
}
501 8a7ddc38 bellard
502 c27004ec bellard
#if TARGET_LONG_BITS == 64
503 c27004ec bellard
#define qemu_put_betl qemu_put_be64
504 c27004ec bellard
#define qemu_get_betl qemu_get_be64
505 c27004ec bellard
#define qemu_put_betls qemu_put_be64s
506 c27004ec bellard
#define qemu_get_betls qemu_get_be64s
507 c27004ec bellard
#else
508 c27004ec bellard
#define qemu_put_betl qemu_put_be32
509 c27004ec bellard
#define qemu_get_betl qemu_get_be32
510 c27004ec bellard
#define qemu_put_betls qemu_put_be32s
511 c27004ec bellard
#define qemu_get_betls qemu_get_be32s
512 c27004ec bellard
#endif
513 c27004ec bellard
514 8a7ddc38 bellard
int64_t qemu_ftell(QEMUFile *f);
515 8a7ddc38 bellard
int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
516 8a7ddc38 bellard
517 8a7ddc38 bellard
typedef void SaveStateHandler(QEMUFile *f, void *opaque);
518 8a7ddc38 bellard
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
519 8a7ddc38 bellard
520 8a7ddc38 bellard
int register_savevm(const char *idstr, 
521 8a7ddc38 bellard
                    int instance_id, 
522 8a7ddc38 bellard
                    int version_id,
523 8a7ddc38 bellard
                    SaveStateHandler *save_state,
524 8a7ddc38 bellard
                    LoadStateHandler *load_state,
525 8a7ddc38 bellard
                    void *opaque);
526 8a7ddc38 bellard
void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
527 8a7ddc38 bellard
void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
528 c4b1fcc0 bellard
529 6a00d601 bellard
void cpu_save(QEMUFile *f, void *opaque);
530 6a00d601 bellard
int cpu_load(QEMUFile *f, void *opaque, int version_id);
531 6a00d601 bellard
532 faea38e7 bellard
void do_savevm(const char *name);
533 faea38e7 bellard
void do_loadvm(const char *name);
534 faea38e7 bellard
void do_delvm(const char *name);
535 faea38e7 bellard
void do_info_snapshots(void);
536 faea38e7 bellard
537 83f64091 bellard
/* bottom halves */
538 83f64091 bellard
typedef void QEMUBHFunc(void *opaque);
539 83f64091 bellard
540 83f64091 bellard
QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
541 83f64091 bellard
void qemu_bh_schedule(QEMUBH *bh);
542 83f64091 bellard
void qemu_bh_cancel(QEMUBH *bh);
543 83f64091 bellard
void qemu_bh_delete(QEMUBH *bh);
544 6eb5733a bellard
int qemu_bh_poll(void);
545 83f64091 bellard
546 fc01f7e7 bellard
/* block.c */
547 fc01f7e7 bellard
typedef struct BlockDriverState BlockDriverState;
548 ea2384d3 bellard
typedef struct BlockDriver BlockDriver;
549 ea2384d3 bellard
550 ea2384d3 bellard
extern BlockDriver bdrv_raw;
551 19cb3738 bellard
extern BlockDriver bdrv_host_device;
552 ea2384d3 bellard
extern BlockDriver bdrv_cow;
553 ea2384d3 bellard
extern BlockDriver bdrv_qcow;
554 ea2384d3 bellard
extern BlockDriver bdrv_vmdk;
555 3c56521b bellard
extern BlockDriver bdrv_cloop;
556 585d0ed9 bellard
extern BlockDriver bdrv_dmg;
557 a8753c34 bellard
extern BlockDriver bdrv_bochs;
558 6a0f9e82 bellard
extern BlockDriver bdrv_vpc;
559 de167e41 bellard
extern BlockDriver bdrv_vvfat;
560 faea38e7 bellard
extern BlockDriver bdrv_qcow2;
561 faea38e7 bellard
562 faea38e7 bellard
typedef struct BlockDriverInfo {
563 faea38e7 bellard
    /* in bytes, 0 if irrelevant */
564 faea38e7 bellard
    int cluster_size; 
565 faea38e7 bellard
    /* offset at which the VM state can be saved (0 if not possible) */
566 faea38e7 bellard
    int64_t vm_state_offset; 
567 faea38e7 bellard
} BlockDriverInfo;
568 faea38e7 bellard
569 faea38e7 bellard
typedef struct QEMUSnapshotInfo {
570 faea38e7 bellard
    char id_str[128]; /* unique snapshot id */
571 faea38e7 bellard
    /* the following fields are informative. They are not needed for
572 faea38e7 bellard
       the consistency of the snapshot */
573 faea38e7 bellard
    char name[256]; /* user choosen name */
574 faea38e7 bellard
    uint32_t vm_state_size; /* VM state info size */
575 faea38e7 bellard
    uint32_t date_sec; /* UTC date of the snapshot */
576 faea38e7 bellard
    uint32_t date_nsec;
577 faea38e7 bellard
    uint64_t vm_clock_nsec; /* VM clock relative to boot */
578 faea38e7 bellard
} QEMUSnapshotInfo;
579 ea2384d3 bellard
580 83f64091 bellard
#define BDRV_O_RDONLY      0x0000
581 83f64091 bellard
#define BDRV_O_RDWR        0x0002
582 83f64091 bellard
#define BDRV_O_ACCESS      0x0003
583 83f64091 bellard
#define BDRV_O_CREAT       0x0004 /* create an empty file */
584 83f64091 bellard
#define BDRV_O_SNAPSHOT    0x0008 /* open the file read only and save writes in a snapshot */
585 83f64091 bellard
#define BDRV_O_FILE        0x0010 /* open as a raw file (do not try to
586 83f64091 bellard
                                     use a disk image format on top of
587 83f64091 bellard
                                     it (default for
588 83f64091 bellard
                                     bdrv_file_open()) */
589 83f64091 bellard
590 ea2384d3 bellard
void bdrv_init(void);
591 ea2384d3 bellard
BlockDriver *bdrv_find_format(const char *format_name);
592 ea2384d3 bellard
int bdrv_create(BlockDriver *drv, 
593 ea2384d3 bellard
                const char *filename, int64_t size_in_sectors,
594 ea2384d3 bellard
                const char *backing_file, int flags);
595 c4b1fcc0 bellard
BlockDriverState *bdrv_new(const char *device_name);
596 c4b1fcc0 bellard
void bdrv_delete(BlockDriverState *bs);
597 83f64091 bellard
int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
598 83f64091 bellard
int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
599 83f64091 bellard
int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
600 ea2384d3 bellard
               BlockDriver *drv);
601 fc01f7e7 bellard
void bdrv_close(BlockDriverState *bs);
602 fc01f7e7 bellard
int bdrv_read(BlockDriverState *bs, int64_t sector_num, 
603 fc01f7e7 bellard
              uint8_t *buf, int nb_sectors);
604 fc01f7e7 bellard
int bdrv_write(BlockDriverState *bs, int64_t sector_num, 
605 fc01f7e7 bellard
               const uint8_t *buf, int nb_sectors);
606 83f64091 bellard
int bdrv_pread(BlockDriverState *bs, int64_t offset, 
607 83f64091 bellard
               void *buf, int count);
608 83f64091 bellard
int bdrv_pwrite(BlockDriverState *bs, int64_t offset, 
609 83f64091 bellard
                const void *buf, int count);
610 83f64091 bellard
int bdrv_truncate(BlockDriverState *bs, int64_t offset);
611 83f64091 bellard
int64_t bdrv_getlength(BlockDriverState *bs);
612 fc01f7e7 bellard
void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
613 33e3963e bellard
int bdrv_commit(BlockDriverState *bs);
614 77fef8c1 bellard
void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
615 83f64091 bellard
/* async block I/O */
616 83f64091 bellard
typedef struct BlockDriverAIOCB BlockDriverAIOCB;
617 83f64091 bellard
typedef void BlockDriverCompletionFunc(void *opaque, int ret);
618 83f64091 bellard
619 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
620 ce1a14dc pbrook
                                uint8_t *buf, int nb_sectors,
621 ce1a14dc pbrook
                                BlockDriverCompletionFunc *cb, void *opaque);
622 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
623 ce1a14dc pbrook
                                 const uint8_t *buf, int nb_sectors,
624 ce1a14dc pbrook
                                 BlockDriverCompletionFunc *cb, void *opaque);
625 83f64091 bellard
void bdrv_aio_cancel(BlockDriverAIOCB *acb);
626 83f64091 bellard
627 83f64091 bellard
void qemu_aio_init(void);
628 83f64091 bellard
void qemu_aio_poll(void);
629 6192bc37 pbrook
void qemu_aio_flush(void);
630 83f64091 bellard
void qemu_aio_wait_start(void);
631 83f64091 bellard
void qemu_aio_wait(void);
632 83f64091 bellard
void qemu_aio_wait_end(void);
633 83f64091 bellard
634 7a6cba61 pbrook
/* Ensure contents are flushed to disk.  */
635 7a6cba61 pbrook
void bdrv_flush(BlockDriverState *bs);
636 33e3963e bellard
637 c4b1fcc0 bellard
#define BDRV_TYPE_HD     0
638 c4b1fcc0 bellard
#define BDRV_TYPE_CDROM  1
639 c4b1fcc0 bellard
#define BDRV_TYPE_FLOPPY 2
640 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_AUTO   0
641 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_NONE   1
642 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LBA    2
643 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LARGE  3
644 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_RECHS  4
645 c4b1fcc0 bellard
646 c4b1fcc0 bellard
void bdrv_set_geometry_hint(BlockDriverState *bs, 
647 c4b1fcc0 bellard
                            int cyls, int heads, int secs);
648 c4b1fcc0 bellard
void bdrv_set_type_hint(BlockDriverState *bs, int type);
649 46d4767d bellard
void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
650 c4b1fcc0 bellard
void bdrv_get_geometry_hint(BlockDriverState *bs, 
651 c4b1fcc0 bellard
                            int *pcyls, int *pheads, int *psecs);
652 c4b1fcc0 bellard
int bdrv_get_type_hint(BlockDriverState *bs);
653 46d4767d bellard
int bdrv_get_translation_hint(BlockDriverState *bs);
654 c4b1fcc0 bellard
int bdrv_is_removable(BlockDriverState *bs);
655 c4b1fcc0 bellard
int bdrv_is_read_only(BlockDriverState *bs);
656 c4b1fcc0 bellard
int bdrv_is_inserted(BlockDriverState *bs);
657 19cb3738 bellard
int bdrv_media_changed(BlockDriverState *bs);
658 c4b1fcc0 bellard
int bdrv_is_locked(BlockDriverState *bs);
659 c4b1fcc0 bellard
void bdrv_set_locked(BlockDriverState *bs, int locked);
660 19cb3738 bellard
void bdrv_eject(BlockDriverState *bs, int eject_flag);
661 c4b1fcc0 bellard
void bdrv_set_change_cb(BlockDriverState *bs, 
662 c4b1fcc0 bellard
                        void (*change_cb)(void *opaque), void *opaque);
663 ea2384d3 bellard
void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
664 c4b1fcc0 bellard
void bdrv_info(void);
665 c4b1fcc0 bellard
BlockDriverState *bdrv_find(const char *name);
666 82c643ff bellard
void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
667 ea2384d3 bellard
int bdrv_is_encrypted(BlockDriverState *bs);
668 ea2384d3 bellard
int bdrv_set_key(BlockDriverState *bs, const char *key);
669 ea2384d3 bellard
void bdrv_iterate_format(void (*it)(void *opaque, const char *name), 
670 ea2384d3 bellard
                         void *opaque);
671 ea2384d3 bellard
const char *bdrv_get_device_name(BlockDriverState *bs);
672 faea38e7 bellard
int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num, 
673 faea38e7 bellard
                          const uint8_t *buf, int nb_sectors);
674 faea38e7 bellard
int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
675 c4b1fcc0 bellard
676 83f64091 bellard
void bdrv_get_backing_filename(BlockDriverState *bs, 
677 83f64091 bellard
                               char *filename, int filename_size);
678 faea38e7 bellard
int bdrv_snapshot_create(BlockDriverState *bs, 
679 faea38e7 bellard
                         QEMUSnapshotInfo *sn_info);
680 faea38e7 bellard
int bdrv_snapshot_goto(BlockDriverState *bs, 
681 faea38e7 bellard
                       const char *snapshot_id);
682 faea38e7 bellard
int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
683 faea38e7 bellard
int bdrv_snapshot_list(BlockDriverState *bs, 
684 faea38e7 bellard
                       QEMUSnapshotInfo **psn_info);
685 faea38e7 bellard
char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
686 faea38e7 bellard
687 faea38e7 bellard
char *get_human_readable_size(char *buf, int buf_size, int64_t size);
688 83f64091 bellard
int path_is_absolute(const char *path);
689 83f64091 bellard
void path_combine(char *dest, int dest_size,
690 83f64091 bellard
                  const char *base_path,
691 83f64091 bellard
                  const char *filename);
692 ea2384d3 bellard
693 ea2384d3 bellard
#ifndef QEMU_TOOL
694 54fa5af5 bellard
695 54fa5af5 bellard
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size, 
696 54fa5af5 bellard
                                 int boot_device,
697 54fa5af5 bellard
             DisplayState *ds, const char **fd_filename, int snapshot,
698 54fa5af5 bellard
             const char *kernel_filename, const char *kernel_cmdline,
699 94fc95cd j_mayer
             const char *initrd_filename, const char *cpu_model);
700 54fa5af5 bellard
701 54fa5af5 bellard
typedef struct QEMUMachine {
702 54fa5af5 bellard
    const char *name;
703 54fa5af5 bellard
    const char *desc;
704 54fa5af5 bellard
    QEMUMachineInitFunc *init;
705 54fa5af5 bellard
    struct QEMUMachine *next;
706 54fa5af5 bellard
} QEMUMachine;
707 54fa5af5 bellard
708 54fa5af5 bellard
int qemu_register_machine(QEMUMachine *m);
709 54fa5af5 bellard
710 54fa5af5 bellard
typedef void SetIRQFunc(void *opaque, int irq_num, int level);
711 3de388f6 bellard
typedef void IRQRequestFunc(void *opaque, int level);
712 54fa5af5 bellard
713 94fc95cd j_mayer
#if defined(TARGET_PPC)
714 94fc95cd j_mayer
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
715 94fc95cd j_mayer
#endif
716 94fc95cd j_mayer
717 33d68b5f ths
#if defined(TARGET_MIPS)
718 33d68b5f ths
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
719 33d68b5f ths
#endif
720 33d68b5f ths
721 26aa7d72 bellard
/* ISA bus */
722 26aa7d72 bellard
723 26aa7d72 bellard
extern target_phys_addr_t isa_mem_base;
724 26aa7d72 bellard
725 26aa7d72 bellard
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
726 26aa7d72 bellard
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
727 26aa7d72 bellard
728 26aa7d72 bellard
int register_ioport_read(int start, int length, int size, 
729 26aa7d72 bellard
                         IOPortReadFunc *func, void *opaque);
730 26aa7d72 bellard
int register_ioport_write(int start, int length, int size, 
731 26aa7d72 bellard
                          IOPortWriteFunc *func, void *opaque);
732 69b91039 bellard
void isa_unassign_ioport(int start, int length);
733 69b91039 bellard
734 aef445bd pbrook
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
735 aef445bd pbrook
736 69b91039 bellard
/* PCI bus */
737 69b91039 bellard
738 69b91039 bellard
extern target_phys_addr_t pci_mem_base;
739 69b91039 bellard
740 46e50e9d bellard
typedef struct PCIBus PCIBus;
741 69b91039 bellard
typedef struct PCIDevice PCIDevice;
742 69b91039 bellard
743 69b91039 bellard
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 
744 69b91039 bellard
                                uint32_t address, uint32_t data, int len);
745 69b91039 bellard
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 
746 69b91039 bellard
                                   uint32_t address, int len);
747 69b91039 bellard
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 
748 69b91039 bellard
                                uint32_t addr, uint32_t size, int type);
749 69b91039 bellard
750 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM                0x00
751 69b91039 bellard
#define PCI_ADDRESS_SPACE_IO                0x01
752 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM_PREFETCH        0x08
753 69b91039 bellard
754 69b91039 bellard
typedef struct PCIIORegion {
755 5768f5ac bellard
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
756 69b91039 bellard
    uint32_t size;
757 69b91039 bellard
    uint8_t type;
758 69b91039 bellard
    PCIMapIORegionFunc *map_func;
759 69b91039 bellard
} PCIIORegion;
760 69b91039 bellard
761 8a8696a3 bellard
#define PCI_ROM_SLOT 6
762 8a8696a3 bellard
#define PCI_NUM_REGIONS 7
763 502a5395 pbrook
764 502a5395 pbrook
#define PCI_DEVICES_MAX 64
765 502a5395 pbrook
766 502a5395 pbrook
#define PCI_VENDOR_ID                0x00        /* 16 bits */
767 502a5395 pbrook
#define PCI_DEVICE_ID                0x02        /* 16 bits */
768 502a5395 pbrook
#define PCI_COMMAND                0x04        /* 16 bits */
769 502a5395 pbrook
#define  PCI_COMMAND_IO                0x1        /* Enable response in I/O space */
770 502a5395 pbrook
#define  PCI_COMMAND_MEMORY        0x2        /* Enable response in Memory space */
771 502a5395 pbrook
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
772 502a5395 pbrook
#define PCI_INTERRUPT_LINE        0x3c        /* 8 bits */
773 502a5395 pbrook
#define PCI_INTERRUPT_PIN        0x3d        /* 8 bits */
774 502a5395 pbrook
#define PCI_MIN_GNT                0x3e        /* 8 bits */
775 502a5395 pbrook
#define PCI_MAX_LAT                0x3f        /* 8 bits */
776 502a5395 pbrook
777 69b91039 bellard
struct PCIDevice {
778 69b91039 bellard
    /* PCI config space */
779 69b91039 bellard
    uint8_t config[256];
780 69b91039 bellard
781 69b91039 bellard
    /* the following fields are read only */
782 46e50e9d bellard
    PCIBus *bus;
783 69b91039 bellard
    int devfn;
784 69b91039 bellard
    char name[64];
785 8a8696a3 bellard
    PCIIORegion io_regions[PCI_NUM_REGIONS];
786 69b91039 bellard
    
787 69b91039 bellard
    /* do not access the following fields */
788 69b91039 bellard
    PCIConfigReadFunc *config_read;
789 69b91039 bellard
    PCIConfigWriteFunc *config_write;
790 502a5395 pbrook
    /* ??? This is a PC-specific hack, and should be removed.  */
791 5768f5ac bellard
    int irq_index;
792 d2b59317 pbrook
793 d2b59317 pbrook
    /* Current IRQ levels.  Used internally by the generic PCI code.  */
794 d2b59317 pbrook
    int irq_state[4];
795 69b91039 bellard
};
796 69b91039 bellard
797 46e50e9d bellard
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
798 46e50e9d bellard
                               int instance_size, int devfn,
799 69b91039 bellard
                               PCIConfigReadFunc *config_read, 
800 69b91039 bellard
                               PCIConfigWriteFunc *config_write);
801 69b91039 bellard
802 69b91039 bellard
void pci_register_io_region(PCIDevice *pci_dev, int region_num, 
803 69b91039 bellard
                            uint32_t size, int type, 
804 69b91039 bellard
                            PCIMapIORegionFunc *map_func);
805 69b91039 bellard
806 5768f5ac bellard
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level);
807 5768f5ac bellard
808 5768f5ac bellard
uint32_t pci_default_read_config(PCIDevice *d, 
809 5768f5ac bellard
                                 uint32_t address, int len);
810 5768f5ac bellard
void pci_default_write_config(PCIDevice *d, 
811 5768f5ac bellard
                              uint32_t address, uint32_t val, int len);
812 89b6b508 bellard
void pci_device_save(PCIDevice *s, QEMUFile *f);
813 89b6b508 bellard
int pci_device_load(PCIDevice *s, QEMUFile *f);
814 5768f5ac bellard
815 d2b59317 pbrook
typedef void (*pci_set_irq_fn)(void *pic, int irq_num, int level);
816 d2b59317 pbrook
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
817 d2b59317 pbrook
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
818 80b3ada7 pbrook
                         void *pic, int devfn_min, int nirq);
819 502a5395 pbrook
820 abcebc7e ths
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
821 502a5395 pbrook
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
822 502a5395 pbrook
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
823 502a5395 pbrook
int pci_bus_num(PCIBus *s);
824 80b3ada7 pbrook
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
825 9995c51f bellard
826 5768f5ac bellard
void pci_info(void);
827 80b3ada7 pbrook
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
828 80b3ada7 pbrook
                        pci_map_irq_fn map_irq, const char *name);
829 26aa7d72 bellard
830 502a5395 pbrook
/* prep_pci.c */
831 46e50e9d bellard
PCIBus *pci_prep_init(void);
832 77d4bc34 bellard
833 502a5395 pbrook
/* grackle_pci.c */
834 502a5395 pbrook
PCIBus *pci_grackle_init(uint32_t base, void *pic);
835 502a5395 pbrook
836 502a5395 pbrook
/* unin_pci.c */
837 502a5395 pbrook
PCIBus *pci_pmac_init(void *pic);
838 502a5395 pbrook
839 502a5395 pbrook
/* apb_pci.c */
840 502a5395 pbrook
PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base,
841 502a5395 pbrook
                     void *pic);
842 502a5395 pbrook
843 e69954b9 pbrook
PCIBus *pci_vpb_init(void *pic, int irq, int realview);
844 502a5395 pbrook
845 502a5395 pbrook
/* piix_pci.c */
846 f00fc47c bellard
PCIBus *i440fx_init(PCIDevice **pi440fx_state);
847 f00fc47c bellard
void i440fx_set_smm(PCIDevice *d, int val);
848 8f1c91d8 ths
int piix3_init(PCIBus *bus, int devfn);
849 f00fc47c bellard
void i440fx_init_memory_mappings(PCIDevice *d);
850 a41b2ff2 pbrook
851 5856de80 ths
int piix4_init(PCIBus *bus, int devfn);
852 5856de80 ths
853 28b9b5af bellard
/* openpic.c */
854 28b9b5af bellard
typedef struct openpic_t openpic_t;
855 54fa5af5 bellard
void openpic_set_irq(void *opaque, int n_IRQ, int level);
856 7668a27f bellard
openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
857 7668a27f bellard
                         CPUState **envp);
858 28b9b5af bellard
859 54fa5af5 bellard
/* heathrow_pic.c */
860 54fa5af5 bellard
typedef struct HeathrowPICS HeathrowPICS;
861 54fa5af5 bellard
void heathrow_pic_set_irq(void *opaque, int num, int level);
862 54fa5af5 bellard
HeathrowPICS *heathrow_pic_init(int *pmem_index);
863 54fa5af5 bellard
864 fde7d5bd ths
/* gt64xxx.c */
865 fde7d5bd ths
PCIBus *pci_gt64120_init(void *pic);
866 fde7d5bd ths
867 6a36d84e bellard
#ifdef HAS_AUDIO
868 6a36d84e bellard
struct soundhw {
869 6a36d84e bellard
    const char *name;
870 6a36d84e bellard
    const char *descr;
871 6a36d84e bellard
    int enabled;
872 6a36d84e bellard
    int isa;
873 6a36d84e bellard
    union {
874 6a36d84e bellard
        int (*init_isa) (AudioState *s);
875 6a36d84e bellard
        int (*init_pci) (PCIBus *bus, AudioState *s);
876 6a36d84e bellard
    } init;
877 6a36d84e bellard
};
878 6a36d84e bellard
879 6a36d84e bellard
extern struct soundhw soundhw[];
880 6a36d84e bellard
#endif
881 6a36d84e bellard
882 313aa567 bellard
/* vga.c */
883 313aa567 bellard
884 74a14f22 bellard
#define VGA_RAM_SIZE (8192 * 1024)
885 313aa567 bellard
886 82c643ff bellard
struct DisplayState {
887 313aa567 bellard
    uint8_t *data;
888 313aa567 bellard
    int linesize;
889 313aa567 bellard
    int depth;
890 d3079cd2 bellard
    int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
891 82c643ff bellard
    int width;
892 82c643ff bellard
    int height;
893 24236869 bellard
    void *opaque;
894 24236869 bellard
895 313aa567 bellard
    void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
896 313aa567 bellard
    void (*dpy_resize)(struct DisplayState *s, int w, int h);
897 313aa567 bellard
    void (*dpy_refresh)(struct DisplayState *s);
898 24236869 bellard
    void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y, int dst_x, int dst_y, int w, int h);
899 82c643ff bellard
};
900 313aa567 bellard
901 313aa567 bellard
static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
902 313aa567 bellard
{
903 313aa567 bellard
    s->dpy_update(s, x, y, w, h);
904 313aa567 bellard
}
905 313aa567 bellard
906 313aa567 bellard
static inline void dpy_resize(DisplayState *s, int w, int h)
907 313aa567 bellard
{
908 313aa567 bellard
    s->dpy_resize(s, w, h);
909 313aa567 bellard
}
910 313aa567 bellard
911 89b6b508 bellard
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base, 
912 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size);
913 89b6b508 bellard
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base, 
914 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size,
915 89b6b508 bellard
                 unsigned long vga_bios_offset, int vga_bios_size);
916 313aa567 bellard
917 d6bfa22f bellard
/* cirrus_vga.c */
918 46e50e9d bellard
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base, 
919 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
920 d6bfa22f bellard
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base, 
921 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
922 d6bfa22f bellard
923 313aa567 bellard
/* sdl.c */
924 43523e93 ths
void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
925 313aa567 bellard
926 da4dbf74 bellard
/* cocoa.m */
927 da4dbf74 bellard
void cocoa_display_init(DisplayState *ds, int full_screen);
928 da4dbf74 bellard
929 24236869 bellard
/* vnc.c */
930 73fc9742 ths
void vnc_display_init(DisplayState *ds, const char *display);
931 a9ce8590 bellard
void do_info_vnc(void);
932 24236869 bellard
933 6070dd07 ths
/* x_keymap.c */
934 6070dd07 ths
extern uint8_t _translate_keycode(const int key);
935 6070dd07 ths
936 5391d806 bellard
/* ide.c */
937 5391d806 bellard
#define MAX_DISKS 4
938 5391d806 bellard
939 faea38e7 bellard
extern BlockDriverState *bs_table[MAX_DISKS + 1];
940 5391d806 bellard
941 69b91039 bellard
void isa_ide_init(int iobase, int iobase2, int irq,
942 69b91039 bellard
                  BlockDriverState *hd0, BlockDriverState *hd1);
943 54fa5af5 bellard
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
944 54fa5af5 bellard
                         int secondary_ide_enabled);
945 502a5395 pbrook
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn);
946 28b9b5af bellard
int pmac_ide_init (BlockDriverState **hd_table,
947 54fa5af5 bellard
                   SetIRQFunc *set_irq, void *irq_opaque, int irq);
948 5391d806 bellard
949 2e5d83bb pbrook
/* cdrom.c */
950 2e5d83bb pbrook
int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
951 2e5d83bb pbrook
int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
952 2e5d83bb pbrook
953 9542611a ths
/* ds1225y.c */
954 9542611a ths
typedef struct ds1225y_t ds1225y_t;
955 9542611a ths
ds1225y_t *ds1225y_init(target_ulong mem_base, const char *filename);
956 9542611a ths
957 1d14ffa9 bellard
/* es1370.c */
958 c0fe3827 bellard
int es1370_init (PCIBus *bus, AudioState *s);
959 1d14ffa9 bellard
960 fb065187 bellard
/* sb16.c */
961 c0fe3827 bellard
int SB16_init (AudioState *s);
962 fb065187 bellard
963 fb065187 bellard
/* adlib.c */
964 c0fe3827 bellard
int Adlib_init (AudioState *s);
965 fb065187 bellard
966 fb065187 bellard
/* gus.c */
967 c0fe3827 bellard
int GUS_init (AudioState *s);
968 27503323 bellard
969 27503323 bellard
/* dma.c */
970 85571bc7 bellard
typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
971 27503323 bellard
int DMA_get_channel_mode (int nchan);
972 85571bc7 bellard
int DMA_read_memory (int nchan, void *buf, int pos, int size);
973 85571bc7 bellard
int DMA_write_memory (int nchan, void *buf, int pos, int size);
974 27503323 bellard
void DMA_hold_DREQ (int nchan);
975 27503323 bellard
void DMA_release_DREQ (int nchan);
976 16f62432 bellard
void DMA_schedule(int nchan);
977 27503323 bellard
void DMA_run (void);
978 28b9b5af bellard
void DMA_init (int high_page_enable);
979 27503323 bellard
void DMA_register_channel (int nchan,
980 85571bc7 bellard
                           DMA_transfer_handler transfer_handler,
981 85571bc7 bellard
                           void *opaque);
982 7138fcfb bellard
/* fdc.c */
983 7138fcfb bellard
#define MAX_FD 2
984 7138fcfb bellard
extern BlockDriverState *fd_table[MAX_FD];
985 7138fcfb bellard
986 baca51fa bellard
typedef struct fdctrl_t fdctrl_t;
987 baca51fa bellard
988 baca51fa bellard
fdctrl_t *fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped, 
989 baca51fa bellard
                       uint32_t io_base,
990 baca51fa bellard
                       BlockDriverState **fds);
991 baca51fa bellard
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
992 7138fcfb bellard
993 80cabfad bellard
/* ne2000.c */
994 80cabfad bellard
995 7c9d8e07 bellard
void isa_ne2000_init(int base, int irq, NICInfo *nd);
996 abcebc7e ths
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
997 80cabfad bellard
998 a41b2ff2 pbrook
/* rtl8139.c */
999 a41b2ff2 pbrook
1000 abcebc7e ths
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1001 a41b2ff2 pbrook
1002 e3c2613f bellard
/* pcnet.c */
1003 e3c2613f bellard
1004 abcebc7e ths
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1005 67e999be bellard
void pcnet_h_reset(void *opaque);
1006 67e999be bellard
void *lance_init(NICInfo *nd, uint32_t leaddr, void *dma_opaque);
1007 67e999be bellard
1008 e3c2613f bellard
1009 80cabfad bellard
/* pckbd.c */
1010 80cabfad bellard
1011 80cabfad bellard
void kbd_init(void);
1012 80cabfad bellard
1013 80cabfad bellard
/* mc146818rtc.c */
1014 80cabfad bellard
1015 8a7ddc38 bellard
typedef struct RTCState RTCState;
1016 80cabfad bellard
1017 8a7ddc38 bellard
RTCState *rtc_init(int base, int irq);
1018 8a7ddc38 bellard
void rtc_set_memory(RTCState *s, int addr, int val);
1019 8a7ddc38 bellard
void rtc_set_date(RTCState *s, const struct tm *tm);
1020 80cabfad bellard
1021 80cabfad bellard
/* serial.c */
1022 80cabfad bellard
1023 c4b1fcc0 bellard
typedef struct SerialState SerialState;
1024 e5d13e2f bellard
SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
1025 e5d13e2f bellard
                         int base, int irq, CharDriverState *chr);
1026 e5d13e2f bellard
SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
1027 e5d13e2f bellard
                             target_ulong base, int it_shift,
1028 e5d13e2f bellard
                             int irq, CharDriverState *chr);
1029 80cabfad bellard
1030 6508fe59 bellard
/* parallel.c */
1031 6508fe59 bellard
1032 6508fe59 bellard
typedef struct ParallelState ParallelState;
1033 6508fe59 bellard
ParallelState *parallel_init(int base, int irq, CharDriverState *chr);
1034 6508fe59 bellard
1035 80cabfad bellard
/* i8259.c */
1036 80cabfad bellard
1037 3de388f6 bellard
typedef struct PicState2 PicState2;
1038 3de388f6 bellard
extern PicState2 *isa_pic;
1039 80cabfad bellard
void pic_set_irq(int irq, int level);
1040 54fa5af5 bellard
void pic_set_irq_new(void *opaque, int irq, int level);
1041 3de388f6 bellard
PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque);
1042 d592d303 bellard
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1043 d592d303 bellard
                          void *alt_irq_opaque);
1044 3de388f6 bellard
int pic_read_irq(PicState2 *s);
1045 3de388f6 bellard
void pic_update_irq(PicState2 *s);
1046 3de388f6 bellard
uint32_t pic_intack_read(PicState2 *s);
1047 c20709aa bellard
void pic_info(void);
1048 4a0fb71e bellard
void irq_info(void);
1049 80cabfad bellard
1050 c27004ec bellard
/* APIC */
1051 d592d303 bellard
typedef struct IOAPICState IOAPICState;
1052 d592d303 bellard
1053 c27004ec bellard
int apic_init(CPUState *env);
1054 c27004ec bellard
int apic_get_interrupt(CPUState *env);
1055 d592d303 bellard
IOAPICState *ioapic_init(void);
1056 d592d303 bellard
void ioapic_set_irq(void *opaque, int vector, int level);
1057 c27004ec bellard
1058 80cabfad bellard
/* i8254.c */
1059 80cabfad bellard
1060 80cabfad bellard
#define PIT_FREQ 1193182
1061 80cabfad bellard
1062 ec844b96 bellard
typedef struct PITState PITState;
1063 ec844b96 bellard
1064 ec844b96 bellard
PITState *pit_init(int base, int irq);
1065 ec844b96 bellard
void pit_set_gate(PITState *pit, int channel, int val);
1066 ec844b96 bellard
int pit_get_gate(PITState *pit, int channel);
1067 fd06c375 bellard
int pit_get_initial_count(PITState *pit, int channel);
1068 fd06c375 bellard
int pit_get_mode(PITState *pit, int channel);
1069 ec844b96 bellard
int pit_get_out(PITState *pit, int channel, int64_t current_time);
1070 80cabfad bellard
1071 fd06c375 bellard
/* pcspk.c */
1072 fd06c375 bellard
void pcspk_init(PITState *);
1073 fd06c375 bellard
int pcspk_audio_init(AudioState *);
1074 fd06c375 bellard
1075 3fffc223 ths
#include "hw/smbus.h"
1076 3fffc223 ths
1077 6515b203 bellard
/* acpi.c */
1078 6515b203 bellard
extern int acpi_enabled;
1079 502a5395 pbrook
void piix4_pm_init(PCIBus *bus, int devfn);
1080 3fffc223 ths
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1081 6515b203 bellard
void acpi_bios_init(void);
1082 6515b203 bellard
1083 3fffc223 ths
/* smbus_eeprom.c */
1084 3fffc223 ths
SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf);
1085 3fffc223 ths
1086 80cabfad bellard
/* pc.c */
1087 54fa5af5 bellard
extern QEMUMachine pc_machine;
1088 3dbbdc25 bellard
extern QEMUMachine isapc_machine;
1089 52ca8d6a bellard
extern int fd_bootchk;
1090 80cabfad bellard
1091 6a00d601 bellard
void ioport_set_a20(int enable);
1092 6a00d601 bellard
int ioport_get_a20(void);
1093 6a00d601 bellard
1094 26aa7d72 bellard
/* ppc.c */
1095 54fa5af5 bellard
extern QEMUMachine prep_machine;
1096 54fa5af5 bellard
extern QEMUMachine core99_machine;
1097 54fa5af5 bellard
extern QEMUMachine heathrow_machine;
1098 54fa5af5 bellard
1099 6af0bf9c bellard
/* mips_r4k.c */
1100 6af0bf9c bellard
extern QEMUMachine mips_machine;
1101 6af0bf9c bellard
1102 5856de80 ths
/* mips_malta.c */
1103 5856de80 ths
extern QEMUMachine mips_malta_machine;
1104 5856de80 ths
1105 4de9b249 ths
/* mips_int */
1106 4de9b249 ths
extern void cpu_mips_irq_request(void *opaque, int irq, int level);
1107 4de9b249 ths
1108 e16fe40c ths
/* mips_timer.c */
1109 e16fe40c ths
extern void cpu_mips_clock_init(CPUState *);
1110 e16fe40c ths
extern void cpu_mips_irqctrl_init (void);
1111 e16fe40c ths
1112 27c7ca7e bellard
/* shix.c */
1113 27c7ca7e bellard
extern QEMUMachine shix_machine;
1114 27c7ca7e bellard
1115 8cc43fef bellard
#ifdef TARGET_PPC
1116 8cc43fef bellard
ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1117 8cc43fef bellard
#endif
1118 64201201 bellard
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1119 77d4bc34 bellard
1120 77d4bc34 bellard
extern CPUWriteMemoryFunc *PPC_io_write[];
1121 77d4bc34 bellard
extern CPUReadMemoryFunc *PPC_io_read[];
1122 54fa5af5 bellard
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1123 26aa7d72 bellard
1124 e95c8d51 bellard
/* sun4m.c */
1125 54fa5af5 bellard
extern QEMUMachine sun4m_machine;
1126 ba3c64fb bellard
void pic_set_irq_cpu(int irq, int level, unsigned int cpu);
1127 e95c8d51 bellard
1128 e95c8d51 bellard
/* iommu.c */
1129 e80cfcfc bellard
void *iommu_init(uint32_t addr);
1130 67e999be bellard
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1131 a917d384 pbrook
                                 uint8_t *buf, int len, int is_write);
1132 67e999be bellard
static inline void sparc_iommu_memory_read(void *opaque,
1133 67e999be bellard
                                           target_phys_addr_t addr,
1134 67e999be bellard
                                           uint8_t *buf, int len)
1135 67e999be bellard
{
1136 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1137 67e999be bellard
}
1138 e95c8d51 bellard
1139 67e999be bellard
static inline void sparc_iommu_memory_write(void *opaque,
1140 67e999be bellard
                                            target_phys_addr_t addr,
1141 67e999be bellard
                                            uint8_t *buf, int len)
1142 67e999be bellard
{
1143 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1144 67e999be bellard
}
1145 e95c8d51 bellard
1146 e95c8d51 bellard
/* tcx.c */
1147 95219897 pbrook
void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
1148 6f7e9aec bellard
               unsigned long vram_offset, int vram_size, int width, int height);
1149 e80cfcfc bellard
1150 e80cfcfc bellard
/* slavio_intctl.c */
1151 e80cfcfc bellard
void *slavio_intctl_init();
1152 ba3c64fb bellard
void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
1153 e80cfcfc bellard
void slavio_pic_info(void *opaque);
1154 e80cfcfc bellard
void slavio_irq_info(void *opaque);
1155 e80cfcfc bellard
void slavio_pic_set_irq(void *opaque, int irq, int level);
1156 ba3c64fb bellard
void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);
1157 e95c8d51 bellard
1158 5fe141fd bellard
/* loader.c */
1159 5fe141fd bellard
int get_image_size(const char *filename);
1160 5fe141fd bellard
int load_image(const char *filename, uint8_t *addr);
1161 9ee3c029 bellard
int load_elf(const char *filename, int64_t virt_to_phys_addend, uint64_t *pentry);
1162 e80cfcfc bellard
int load_aout(const char *filename, uint8_t *addr);
1163 1c7b3754 pbrook
int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1164 e80cfcfc bellard
1165 e80cfcfc bellard
/* slavio_timer.c */
1166 ba3c64fb bellard
void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu);
1167 8d5f07fa bellard
1168 e80cfcfc bellard
/* slavio_serial.c */
1169 e80cfcfc bellard
SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2);
1170 e80cfcfc bellard
void slavio_serial_ms_kbd_init(int base, int irq);
1171 e95c8d51 bellard
1172 3475187d bellard
/* slavio_misc.c */
1173 3475187d bellard
void *slavio_misc_init(uint32_t base, int irq);
1174 3475187d bellard
void slavio_set_power_fail(void *opaque, int power_failing);
1175 3475187d bellard
1176 6f7e9aec bellard
/* esp.c */
1177 fa1fb14c ths
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1178 67e999be bellard
void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque);
1179 67e999be bellard
void esp_reset(void *opaque);
1180 67e999be bellard
1181 67e999be bellard
/* sparc32_dma.c */
1182 67e999be bellard
void *sparc32_dma_init(uint32_t daddr, int espirq, int leirq, void *iommu,
1183 67e999be bellard
                       void *intctl);
1184 67e999be bellard
void ledma_set_irq(void *opaque, int isr);
1185 9b94dc32 bellard
void ledma_memory_read(void *opaque, target_phys_addr_t addr, 
1186 9b94dc32 bellard
                       uint8_t *buf, int len, int do_bswap);
1187 9b94dc32 bellard
void ledma_memory_write(void *opaque, target_phys_addr_t addr, 
1188 9b94dc32 bellard
                        uint8_t *buf, int len, int do_bswap);
1189 67e999be bellard
void espdma_raise_irq(void *opaque);
1190 67e999be bellard
void espdma_clear_irq(void *opaque);
1191 67e999be bellard
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1192 67e999be bellard
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1193 67e999be bellard
void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
1194 67e999be bellard
                                void *lance_opaque);
1195 6f7e9aec bellard
1196 b8174937 bellard
/* cs4231.c */
1197 b8174937 bellard
void cs_init(target_phys_addr_t base, int irq, void *intctl);
1198 b8174937 bellard
1199 3475187d bellard
/* sun4u.c */
1200 3475187d bellard
extern QEMUMachine sun4u_machine;
1201 3475187d bellard
1202 64201201 bellard
/* NVRAM helpers */
1203 64201201 bellard
#include "hw/m48t59.h"
1204 64201201 bellard
1205 64201201 bellard
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1206 64201201 bellard
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1207 64201201 bellard
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1208 64201201 bellard
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1209 64201201 bellard
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1210 64201201 bellard
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1211 64201201 bellard
void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1212 64201201 bellard
                       const unsigned char *str, uint32_t max);
1213 64201201 bellard
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1214 64201201 bellard
void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1215 64201201 bellard
                    uint32_t start, uint32_t count);
1216 64201201 bellard
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1217 64201201 bellard
                          const unsigned char *arch,
1218 64201201 bellard
                          uint32_t RAM_size, int boot_device,
1219 64201201 bellard
                          uint32_t kernel_image, uint32_t kernel_size,
1220 28b9b5af bellard
                          const char *cmdline,
1221 64201201 bellard
                          uint32_t initrd_image, uint32_t initrd_size,
1222 28b9b5af bellard
                          uint32_t NVRAM_image,
1223 28b9b5af bellard
                          int width, int height, int depth);
1224 64201201 bellard
1225 63066f4f bellard
/* adb.c */
1226 63066f4f bellard
1227 63066f4f bellard
#define MAX_ADB_DEVICES 16
1228 63066f4f bellard
1229 e2733d20 bellard
#define ADB_MAX_OUT_LEN 16
1230 63066f4f bellard
1231 e2733d20 bellard
typedef struct ADBDevice ADBDevice;
1232 63066f4f bellard
1233 e2733d20 bellard
/* buf = NULL means polling */
1234 e2733d20 bellard
typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1235 e2733d20 bellard
                              const uint8_t *buf, int len);
1236 12c28fed bellard
typedef int ADBDeviceReset(ADBDevice *d);
1237 12c28fed bellard
1238 63066f4f bellard
struct ADBDevice {
1239 63066f4f bellard
    struct ADBBusState *bus;
1240 63066f4f bellard
    int devaddr;
1241 63066f4f bellard
    int handler;
1242 e2733d20 bellard
    ADBDeviceRequest *devreq;
1243 12c28fed bellard
    ADBDeviceReset *devreset;
1244 63066f4f bellard
    void *opaque;
1245 63066f4f bellard
};
1246 63066f4f bellard
1247 63066f4f bellard
typedef struct ADBBusState {
1248 63066f4f bellard
    ADBDevice devices[MAX_ADB_DEVICES];
1249 63066f4f bellard
    int nb_devices;
1250 e2733d20 bellard
    int poll_index;
1251 63066f4f bellard
} ADBBusState;
1252 63066f4f bellard
1253 e2733d20 bellard
int adb_request(ADBBusState *s, uint8_t *buf_out,
1254 e2733d20 bellard
                const uint8_t *buf, int len);
1255 e2733d20 bellard
int adb_poll(ADBBusState *s, uint8_t *buf_out);
1256 63066f4f bellard
1257 63066f4f bellard
ADBDevice *adb_register_device(ADBBusState *s, int devaddr, 
1258 e2733d20 bellard
                               ADBDeviceRequest *devreq, 
1259 12c28fed bellard
                               ADBDeviceReset *devreset, 
1260 63066f4f bellard
                               void *opaque);
1261 63066f4f bellard
void adb_kbd_init(ADBBusState *bus);
1262 63066f4f bellard
void adb_mouse_init(ADBBusState *bus);
1263 63066f4f bellard
1264 63066f4f bellard
/* cuda.c */
1265 63066f4f bellard
1266 63066f4f bellard
extern ADBBusState adb_bus;
1267 54fa5af5 bellard
int cuda_init(SetIRQFunc *set_irq, void *irq_opaque, int irq);
1268 63066f4f bellard
1269 bb36d470 bellard
#include "hw/usb.h"
1270 bb36d470 bellard
1271 a594cfbf bellard
/* usb ports of the VM */
1272 a594cfbf bellard
1273 0d92ed30 pbrook
void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1274 0d92ed30 pbrook
                            usb_attachfn attach);
1275 a594cfbf bellard
1276 0d92ed30 pbrook
#define VM_USB_HUB_SIZE 8
1277 a594cfbf bellard
1278 a594cfbf bellard
void do_usb_add(const char *devname);
1279 a594cfbf bellard
void do_usb_del(const char *devname);
1280 a594cfbf bellard
void usb_info(void);
1281 a594cfbf bellard
1282 2e5d83bb pbrook
/* scsi-disk.c */
1283 4d611c9a pbrook
enum scsi_reason {
1284 4d611c9a pbrook
    SCSI_REASON_DONE, /* Command complete.  */
1285 4d611c9a pbrook
    SCSI_REASON_DATA  /* Transfer complete, more data required.  */
1286 4d611c9a pbrook
};
1287 4d611c9a pbrook
1288 2e5d83bb pbrook
typedef struct SCSIDevice SCSIDevice;
1289 a917d384 pbrook
typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1290 a917d384 pbrook
                                  uint32_t arg);
1291 2e5d83bb pbrook
1292 2e5d83bb pbrook
SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1293 a917d384 pbrook
                           int tcq,
1294 2e5d83bb pbrook
                           scsi_completionfn completion,
1295 2e5d83bb pbrook
                           void *opaque);
1296 2e5d83bb pbrook
void scsi_disk_destroy(SCSIDevice *s);
1297 2e5d83bb pbrook
1298 0fc5c15a pbrook
int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1299 4d611c9a pbrook
/* SCSI data transfers are asynchrnonous.  However, unlike the block IO
1300 4d611c9a pbrook
   layer the completion routine may be called directly by
1301 4d611c9a pbrook
   scsi_{read,write}_data.  */
1302 a917d384 pbrook
void scsi_read_data(SCSIDevice *s, uint32_t tag);
1303 a917d384 pbrook
int scsi_write_data(SCSIDevice *s, uint32_t tag);
1304 a917d384 pbrook
void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1305 a917d384 pbrook
uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1306 2e5d83bb pbrook
1307 7d8406be pbrook
/* lsi53c895a.c */
1308 7d8406be pbrook
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1309 7d8406be pbrook
void *lsi_scsi_init(PCIBus *bus, int devfn);
1310 7d8406be pbrook
1311 b5ff1b31 bellard
/* integratorcp.c */
1312 3371d272 pbrook
extern QEMUMachine integratorcp_machine;
1313 b5ff1b31 bellard
1314 cdbdb648 pbrook
/* versatilepb.c */
1315 cdbdb648 pbrook
extern QEMUMachine versatilepb_machine;
1316 16406950 pbrook
extern QEMUMachine versatileab_machine;
1317 cdbdb648 pbrook
1318 e69954b9 pbrook
/* realview.c */
1319 e69954b9 pbrook
extern QEMUMachine realview_machine;
1320 e69954b9 pbrook
1321 daa57963 bellard
/* ps2.c */
1322 daa57963 bellard
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1323 daa57963 bellard
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1324 daa57963 bellard
void ps2_write_mouse(void *, int val);
1325 daa57963 bellard
void ps2_write_keyboard(void *, int val);
1326 daa57963 bellard
uint32_t ps2_read_data(void *);
1327 daa57963 bellard
void ps2_queue(void *, int b);
1328 f94f5d71 pbrook
void ps2_keyboard_set_translation(void *opaque, int mode);
1329 daa57963 bellard
1330 80337b66 bellard
/* smc91c111.c */
1331 80337b66 bellard
void smc91c111_init(NICInfo *, uint32_t, void *, int);
1332 80337b66 bellard
1333 bdd5003a pbrook
/* pl110.c */
1334 95219897 pbrook
void *pl110_init(DisplayState *ds, uint32_t base, void *pic, int irq, int);
1335 bdd5003a pbrook
1336 cdbdb648 pbrook
/* pl011.c */
1337 cdbdb648 pbrook
void pl011_init(uint32_t base, void *pic, int irq, CharDriverState *chr);
1338 cdbdb648 pbrook
1339 cdbdb648 pbrook
/* pl050.c */
1340 cdbdb648 pbrook
void pl050_init(uint32_t base, void *pic, int irq, int is_mouse);
1341 cdbdb648 pbrook
1342 cdbdb648 pbrook
/* pl080.c */
1343 e69954b9 pbrook
void *pl080_init(uint32_t base, void *pic, int irq, int nchannels);
1344 cdbdb648 pbrook
1345 cdbdb648 pbrook
/* pl190.c */
1346 cdbdb648 pbrook
void *pl190_init(uint32_t base, void *parent, int irq, int fiq);
1347 cdbdb648 pbrook
1348 cdbdb648 pbrook
/* arm-timer.c */
1349 cdbdb648 pbrook
void sp804_init(uint32_t base, void *pic, int irq);
1350 cdbdb648 pbrook
void icp_pit_init(uint32_t base, void *pic, int irq);
1351 cdbdb648 pbrook
1352 e69954b9 pbrook
/* arm_sysctl.c */
1353 e69954b9 pbrook
void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1354 e69954b9 pbrook
1355 e69954b9 pbrook
/* arm_gic.c */
1356 e69954b9 pbrook
void *arm_gic_init(uint32_t base, void *parent, int parent_irq);
1357 e69954b9 pbrook
1358 16406950 pbrook
/* arm_boot.c */
1359 16406950 pbrook
1360 daf90626 pbrook
void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1361 16406950 pbrook
                     const char *kernel_cmdline, const char *initrd_filename,
1362 16406950 pbrook
                     int board_id);
1363 16406950 pbrook
1364 27c7ca7e bellard
/* sh7750.c */
1365 27c7ca7e bellard
struct SH7750State;
1366 27c7ca7e bellard
1367 008a8818 pbrook
struct SH7750State *sh7750_init(CPUState * cpu);
1368 27c7ca7e bellard
1369 27c7ca7e bellard
typedef struct {
1370 27c7ca7e bellard
    /* The callback will be triggered if any of the designated lines change */
1371 27c7ca7e bellard
    uint16_t portamask_trigger;
1372 27c7ca7e bellard
    uint16_t portbmask_trigger;
1373 27c7ca7e bellard
    /* Return 0 if no action was taken */
1374 27c7ca7e bellard
    int (*port_change_cb) (uint16_t porta, uint16_t portb,
1375 27c7ca7e bellard
                           uint16_t * periph_pdtra,
1376 27c7ca7e bellard
                           uint16_t * periph_portdira,
1377 27c7ca7e bellard
                           uint16_t * periph_pdtrb,
1378 27c7ca7e bellard
                           uint16_t * periph_portdirb);
1379 27c7ca7e bellard
} sh7750_io_device;
1380 27c7ca7e bellard
1381 27c7ca7e bellard
int sh7750_register_io_device(struct SH7750State *s,
1382 27c7ca7e bellard
                              sh7750_io_device * device);
1383 27c7ca7e bellard
/* tc58128.c */
1384 27c7ca7e bellard
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1385 27c7ca7e bellard
1386 29133e9a bellard
/* NOR flash devices */
1387 29133e9a bellard
typedef struct pflash_t pflash_t;
1388 29133e9a bellard
1389 29133e9a bellard
pflash_t *pflash_register (target_ulong base, ram_addr_t off,
1390 29133e9a bellard
                           BlockDriverState *bs,
1391 29133e9a bellard
                           target_ulong sector_len, int nb_blocs, int width,
1392 29133e9a bellard
                           uint16_t id0, uint16_t id1, 
1393 29133e9a bellard
                           uint16_t id2, uint16_t id3);
1394 29133e9a bellard
1395 4046d913 pbrook
#include "gdbstub.h"
1396 4046d913 pbrook
1397 ea2384d3 bellard
#endif /* defined(QEMU_TOOL) */
1398 ea2384d3 bellard
1399 c4b1fcc0 bellard
/* monitor.c */
1400 82c643ff bellard
void monitor_init(CharDriverState *hd, int show_banner);
1401 ea2384d3 bellard
void term_puts(const char *str);
1402 ea2384d3 bellard
void term_vprintf(const char *fmt, va_list ap);
1403 40c3bac3 bellard
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1404 fef30743 ths
void term_print_filename(const char *filename);
1405 c4b1fcc0 bellard
void term_flush(void);
1406 c4b1fcc0 bellard
void term_print_help(void);
1407 ea2384d3 bellard
void monitor_readline(const char *prompt, int is_password,
1408 ea2384d3 bellard
                      char *buf, int buf_size);
1409 ea2384d3 bellard
1410 ea2384d3 bellard
/* readline.c */
1411 ea2384d3 bellard
typedef void ReadLineFunc(void *opaque, const char *str);
1412 ea2384d3 bellard
1413 ea2384d3 bellard
extern int completion_index;
1414 ea2384d3 bellard
void add_completion(const char *str);
1415 ea2384d3 bellard
void readline_handle_byte(int ch);
1416 ea2384d3 bellard
void readline_find_completion(const char *cmdline);
1417 ea2384d3 bellard
const char *readline_get_history(unsigned int index);
1418 ea2384d3 bellard
void readline_start(const char *prompt, int is_password,
1419 ea2384d3 bellard
                    ReadLineFunc *readline_func, void *opaque);
1420 c4b1fcc0 bellard
1421 5e6ad6f9 bellard
void kqemu_record_dump(void);
1422 5e6ad6f9 bellard
1423 fc01f7e7 bellard
#endif /* VL_H */