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/*
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* ARM Integrator CP System emulation.
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*
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* Copyright (c) 2005-2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL
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*/
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|
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#include "vl.h" |
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#include "arm_pic.h" |
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|
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void DMA_run (void) |
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{ |
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} |
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|
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typedef struct { |
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uint32_t flash_offset; |
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uint32_t cm_osc; |
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uint32_t cm_ctrl; |
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uint32_t cm_lock; |
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uint32_t cm_auxosc; |
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uint32_t cm_sdram; |
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uint32_t cm_init; |
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uint32_t cm_flags; |
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uint32_t cm_nvflags; |
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uint32_t int_level; |
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uint32_t irq_enabled; |
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uint32_t fiq_enabled; |
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} integratorcm_state; |
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|
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static uint8_t integrator_spd[128] = { |
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128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, |
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0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 |
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}; |
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static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset) |
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{ |
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integratorcm_state *s = (integratorcm_state *)opaque; |
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offset -= 0x10000000;
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if (offset >= 0x100 && offset < 0x200) { |
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/* CM_SPD */
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if (offset >= 0x180) |
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return 0; |
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return integrator_spd[offset >> 2]; |
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} |
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switch (offset >> 2) { |
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case 0: /* CM_ID */ |
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return 0x411a3001; |
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case 1: /* CM_PROC */ |
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return 0; |
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case 2: /* CM_OSC */ |
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return s->cm_osc;
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case 3: /* CM_CTRL */ |
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return s->cm_ctrl;
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case 4: /* CM_STAT */ |
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return 0x00100000; |
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case 5: /* CM_LOCK */ |
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if (s->cm_lock == 0xa05f) { |
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return 0x1a05f; |
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} else {
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return s->cm_lock;
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} |
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case 6: /* CM_LMBUSCNT */ |
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/* ??? High frequency timer. */
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cpu_abort(cpu_single_env, "integratorcm_read: CM_LMBUSCNT");
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case 7: /* CM_AUXOSC */ |
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return s->cm_auxosc;
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case 8: /* CM_SDRAM */ |
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return s->cm_sdram;
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case 9: /* CM_INIT */ |
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return s->cm_init;
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case 10: /* CM_REFCT */ |
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/* ??? High frequency timer. */
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cpu_abort(cpu_single_env, "integratorcm_read: CM_REFCT");
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case 12: /* CM_FLAGS */ |
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return s->cm_flags;
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case 14: /* CM_NVFLAGS */ |
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return s->cm_nvflags;
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case 16: /* CM_IRQ_STAT */ |
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return s->int_level & s->irq_enabled;
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case 17: /* CM_IRQ_RSTAT */ |
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return s->int_level;
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case 18: /* CM_IRQ_ENSET */ |
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return s->irq_enabled;
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case 20: /* CM_SOFT_INTSET */ |
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return s->int_level & 1; |
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case 24: /* CM_FIQ_STAT */ |
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return s->int_level & s->fiq_enabled;
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case 25: /* CM_FIQ_RSTAT */ |
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return s->int_level;
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case 26: /* CM_FIQ_ENSET */ |
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return s->fiq_enabled;
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case 32: /* CM_VOLTAGE_CTL0 */ |
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case 33: /* CM_VOLTAGE_CTL1 */ |
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case 34: /* CM_VOLTAGE_CTL2 */ |
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case 35: /* CM_VOLTAGE_CTL3 */ |
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/* ??? Voltage control unimplemented. */
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return 0; |
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default:
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cpu_abort (cpu_single_env, |
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"integratorcm_read: Unimplemented offset 0x%x\n", offset);
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return 0; |
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} |
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} |
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|
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static void integratorcm_do_remap(integratorcm_state *s, int flash) |
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{ |
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if (flash) {
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cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM); |
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} else {
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cpu_register_physical_memory(0, 0x100000, s->flash_offset | IO_MEM_RAM); |
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} |
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//??? tlb_flush (cpu_single_env, 1);
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} |
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|
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static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value) |
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{ |
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if (value & 8) { |
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cpu_abort(cpu_single_env, "Board reset\n");
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} |
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if ((s->cm_init ^ value) & 4) { |
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integratorcm_do_remap(s, (value & 4) == 0); |
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} |
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if ((s->cm_init ^ value) & 1) { |
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printf("Green LED %s\n", (value & 1) ? "on" : "off"); |
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} |
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s->cm_init = (s->cm_init & ~ 5) | (value ^ 5); |
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} |
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|
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static void integratorcm_update(integratorcm_state *s) |
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{ |
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/* ??? The CPU irq/fiq is raised when either the core module or base PIC
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are active. */
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if (s->int_level & (s->irq_enabled | s->fiq_enabled))
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cpu_abort(cpu_single_env, "Core module interrupt\n");
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} |
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static void integratorcm_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
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integratorcm_state *s = (integratorcm_state *)opaque; |
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offset -= 0x10000000;
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switch (offset >> 2) { |
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case 2: /* CM_OSC */ |
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if (s->cm_lock == 0xa05f) |
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s->cm_osc = value; |
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break;
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case 3: /* CM_CTRL */ |
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integratorcm_set_ctrl(s, value); |
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break;
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case 5: /* CM_LOCK */ |
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s->cm_lock = value & 0xffff;
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break;
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case 7: /* CM_AUXOSC */ |
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if (s->cm_lock == 0xa05f) |
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s->cm_auxosc = value; |
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break;
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case 8: /* CM_SDRAM */ |
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s->cm_sdram = value; |
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break;
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case 9: /* CM_INIT */ |
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/* ??? This can change the memory bus frequency. */
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s->cm_init = value; |
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break;
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case 12: /* CM_FLAGSS */ |
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s->cm_flags |= value; |
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break;
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case 13: /* CM_FLAGSC */ |
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s->cm_flags &= ~value; |
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break;
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case 14: /* CM_NVFLAGSS */ |
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s->cm_nvflags |= value; |
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break;
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case 15: /* CM_NVFLAGSS */ |
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s->cm_nvflags &= ~value; |
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break;
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case 18: /* CM_IRQ_ENSET */ |
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s->irq_enabled |= value; |
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integratorcm_update(s); |
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break;
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case 19: /* CM_IRQ_ENCLR */ |
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s->irq_enabled &= ~value; |
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integratorcm_update(s); |
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break;
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case 20: /* CM_SOFT_INTSET */ |
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s->int_level |= (value & 1);
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integratorcm_update(s); |
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break;
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case 21: /* CM_SOFT_INTCLR */ |
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s->int_level &= ~(value & 1);
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integratorcm_update(s); |
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break;
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case 26: /* CM_FIQ_ENSET */ |
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s->fiq_enabled |= value; |
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integratorcm_update(s); |
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break;
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case 27: /* CM_FIQ_ENCLR */ |
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s->fiq_enabled &= ~value; |
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integratorcm_update(s); |
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break;
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case 32: /* CM_VOLTAGE_CTL0 */ |
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case 33: /* CM_VOLTAGE_CTL1 */ |
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case 34: /* CM_VOLTAGE_CTL2 */ |
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case 35: /* CM_VOLTAGE_CTL3 */ |
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/* ??? Voltage control unimplemented. */
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break;
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default:
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cpu_abort (cpu_single_env, |
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"integratorcm_write: Unimplemented offset 0x%x\n", offset);
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break;
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} |
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} |
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|
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/* Integrator/CM control registers. */
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static CPUReadMemoryFunc *integratorcm_readfn[] = {
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integratorcm_read, |
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integratorcm_read, |
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integratorcm_read |
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}; |
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static CPUWriteMemoryFunc *integratorcm_writefn[] = {
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integratorcm_write, |
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integratorcm_write, |
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integratorcm_write |
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}; |
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static void integratorcm_init(int memsz, uint32_t flash_offset) |
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{ |
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int iomemtype;
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integratorcm_state *s; |
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s = (integratorcm_state *)qemu_mallocz(sizeof(integratorcm_state));
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s->cm_osc = 0x01000048;
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/* ??? What should the high bits of this value be? */
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s->cm_auxosc = 0x0007feff;
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s->cm_sdram = 0x00011122;
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if (memsz >= 256) { |
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integrator_spd[31] = 64; |
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s->cm_sdram |= 0x10;
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} else if (memsz >= 128) { |
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integrator_spd[31] = 32; |
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s->cm_sdram |= 0x0c;
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} else if (memsz >= 64) { |
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integrator_spd[31] = 16; |
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s->cm_sdram |= 0x08;
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} else if (memsz >= 32) { |
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integrator_spd[31] = 4; |
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s->cm_sdram |= 0x04;
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} else {
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integrator_spd[31] = 2; |
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} |
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memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); |
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s->cm_init = 0x00000112;
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s->flash_offset = flash_offset; |
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iomemtype = cpu_register_io_memory(0, integratorcm_readfn,
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integratorcm_writefn, s); |
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cpu_register_physical_memory(0x10000000, 0x007fffff, iomemtype); |
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integratorcm_do_remap(s, 1);
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/* ??? Save/restore. */
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} |
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|
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/* Integrator/CP hardware emulation. */
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/* Primary interrupt controller. */
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|
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typedef struct icp_pic_state |
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{ |
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arm_pic_handler handler; |
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uint32_t base; |
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uint32_t level; |
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uint32_t irq_enabled; |
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uint32_t fiq_enabled; |
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void *parent;
|
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int parent_irq;
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int parent_fiq;
|
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} icp_pic_state; |
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|
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static void icp_pic_update(icp_pic_state *s) |
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{ |
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uint32_t flags; |
283 |
|
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if (s->parent_irq != -1) { |
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flags = (s->level & s->irq_enabled); |
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pic_set_irq_new(s->parent, s->parent_irq, flags != 0);
|
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} |
288 |
if (s->parent_fiq != -1) { |
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flags = (s->level & s->fiq_enabled); |
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pic_set_irq_new(s->parent, s->parent_fiq, flags != 0);
|
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} |
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} |
293 |
|
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static void icp_pic_set_irq(void *opaque, int irq, int level) |
295 |
{ |
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icp_pic_state *s = (icp_pic_state *)opaque; |
297 |
if (level)
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s->level |= 1 << irq;
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else
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s->level &= ~(1 << irq);
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icp_pic_update(s); |
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} |
303 |
|
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static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset) |
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{ |
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icp_pic_state *s = (icp_pic_state *)opaque; |
307 |
|
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offset -= s->base; |
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switch (offset >> 2) { |
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case 0: /* IRQ_STATUS */ |
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return s->level & s->irq_enabled;
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case 1: /* IRQ_RAWSTAT */ |
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return s->level;
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case 2: /* IRQ_ENABLESET */ |
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return s->irq_enabled;
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case 4: /* INT_SOFTSET */ |
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return s->level & 1; |
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case 8: /* FRQ_STATUS */ |
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return s->level & s->fiq_enabled;
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case 9: /* FRQ_RAWSTAT */ |
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return s->level;
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case 10: /* FRQ_ENABLESET */ |
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return s->fiq_enabled;
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case 3: /* IRQ_ENABLECLR */ |
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case 5: /* INT_SOFTCLR */ |
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case 11: /* FRQ_ENABLECLR */ |
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default:
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printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset); |
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return 0; |
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} |
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} |
332 |
|
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static void icp_pic_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
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icp_pic_state *s = (icp_pic_state *)opaque; |
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offset -= s->base; |
338 |
|
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switch (offset >> 2) { |
340 |
case 2: /* IRQ_ENABLESET */ |
341 |
s->irq_enabled |= value; |
342 |
break;
|
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case 3: /* IRQ_ENABLECLR */ |
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s->irq_enabled &= ~value; |
345 |
break;
|
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case 4: /* INT_SOFTSET */ |
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if (value & 1) |
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pic_set_irq_new(s, 0, 1); |
349 |
break;
|
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case 5: /* INT_SOFTCLR */ |
351 |
if (value & 1) |
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pic_set_irq_new(s, 0, 0); |
353 |
break;
|
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case 10: /* FRQ_ENABLESET */ |
355 |
s->fiq_enabled |= value; |
356 |
break;
|
357 |
case 11: /* FRQ_ENABLECLR */ |
358 |
s->fiq_enabled &= ~value; |
359 |
break;
|
360 |
case 0: /* IRQ_STATUS */ |
361 |
case 1: /* IRQ_RAWSTAT */ |
362 |
case 8: /* FRQ_STATUS */ |
363 |
case 9: /* FRQ_RAWSTAT */ |
364 |
default:
|
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printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset); |
366 |
return;
|
367 |
} |
368 |
icp_pic_update(s); |
369 |
} |
370 |
|
371 |
static CPUReadMemoryFunc *icp_pic_readfn[] = {
|
372 |
icp_pic_read, |
373 |
icp_pic_read, |
374 |
icp_pic_read |
375 |
}; |
376 |
|
377 |
static CPUWriteMemoryFunc *icp_pic_writefn[] = {
|
378 |
icp_pic_write, |
379 |
icp_pic_write, |
380 |
icp_pic_write |
381 |
}; |
382 |
|
383 |
static icp_pic_state *icp_pic_init(uint32_t base, void *parent, |
384 |
int parent_irq, int parent_fiq) |
385 |
{ |
386 |
icp_pic_state *s; |
387 |
int iomemtype;
|
388 |
|
389 |
s = (icp_pic_state *)qemu_mallocz(sizeof(icp_pic_state));
|
390 |
if (!s)
|
391 |
return NULL; |
392 |
s->handler = icp_pic_set_irq; |
393 |
s->base = base; |
394 |
s->parent = parent; |
395 |
s->parent_irq = parent_irq; |
396 |
s->parent_fiq = parent_fiq; |
397 |
iomemtype = cpu_register_io_memory(0, icp_pic_readfn,
|
398 |
icp_pic_writefn, s); |
399 |
cpu_register_physical_memory(base, 0x007fffff, iomemtype);
|
400 |
/* ??? Save/restore. */
|
401 |
return s;
|
402 |
} |
403 |
|
404 |
/* CP control registers. */
|
405 |
typedef struct { |
406 |
uint32_t base; |
407 |
} icp_control_state; |
408 |
|
409 |
static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset) |
410 |
{ |
411 |
icp_control_state *s = (icp_control_state *)opaque; |
412 |
offset -= s->base; |
413 |
switch (offset >> 2) { |
414 |
case 0: /* CP_IDFIELD */ |
415 |
return 0x41034003; |
416 |
case 1: /* CP_FLASHPROG */ |
417 |
return 0; |
418 |
case 2: /* CP_INTREG */ |
419 |
return 0; |
420 |
case 3: /* CP_DECODE */ |
421 |
return 0x11; |
422 |
default:
|
423 |
cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n", offset);
|
424 |
return 0; |
425 |
} |
426 |
} |
427 |
|
428 |
static void icp_control_write(void *opaque, target_phys_addr_t offset, |
429 |
uint32_t value) |
430 |
{ |
431 |
icp_control_state *s = (icp_control_state *)opaque; |
432 |
offset -= s->base; |
433 |
switch (offset >> 2) { |
434 |
case 1: /* CP_FLASHPROG */ |
435 |
case 2: /* CP_INTREG */ |
436 |
case 3: /* CP_DECODE */ |
437 |
/* Nothing interesting implemented yet. */
|
438 |
break;
|
439 |
default:
|
440 |
cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n", offset);
|
441 |
} |
442 |
} |
443 |
static CPUReadMemoryFunc *icp_control_readfn[] = {
|
444 |
icp_control_read, |
445 |
icp_control_read, |
446 |
icp_control_read |
447 |
}; |
448 |
|
449 |
static CPUWriteMemoryFunc *icp_control_writefn[] = {
|
450 |
icp_control_write, |
451 |
icp_control_write, |
452 |
icp_control_write |
453 |
}; |
454 |
|
455 |
static void icp_control_init(uint32_t base) |
456 |
{ |
457 |
int iomemtype;
|
458 |
icp_control_state *s; |
459 |
|
460 |
s = (icp_control_state *)qemu_mallocz(sizeof(icp_control_state));
|
461 |
iomemtype = cpu_register_io_memory(0, icp_control_readfn,
|
462 |
icp_control_writefn, s); |
463 |
cpu_register_physical_memory(base, 0x007fffff, iomemtype);
|
464 |
s->base = base; |
465 |
/* ??? Save/restore. */
|
466 |
} |
467 |
|
468 |
|
469 |
/* Board init. */
|
470 |
|
471 |
static void integratorcp_init(int ram_size, int vga_ram_size, int boot_device, |
472 |
DisplayState *ds, const char **fd_filename, int snapshot, |
473 |
const char *kernel_filename, const char *kernel_cmdline, |
474 |
const char *initrd_filename, const char *cpu_model) |
475 |
{ |
476 |
CPUState *env; |
477 |
uint32_t bios_offset; |
478 |
icp_pic_state *pic; |
479 |
void *cpu_pic;
|
480 |
|
481 |
env = cpu_init(); |
482 |
if (!cpu_model)
|
483 |
cpu_model = "arm926";
|
484 |
cpu_arm_set_model(env, cpu_model); |
485 |
bios_offset = ram_size + vga_ram_size; |
486 |
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
|
487 |
/* ??? RAM shoud repeat to fill physical memory space. */
|
488 |
/* SDRAM at address zero*/
|
489 |
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
490 |
/* And again at address 0x80000000 */
|
491 |
cpu_register_physical_memory(0x80000000, ram_size, IO_MEM_RAM);
|
492 |
|
493 |
integratorcm_init(ram_size >> 20, bios_offset);
|
494 |
cpu_pic = arm_pic_init_cpu(env); |
495 |
pic = icp_pic_init(0x14000000, cpu_pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ);
|
496 |
icp_pic_init(0xca000000, pic, 26, -1); |
497 |
icp_pit_init(0x13000000, pic, 5); |
498 |
pl011_init(0x16000000, pic, 1, serial_hds[0]); |
499 |
pl011_init(0x17000000, pic, 2, serial_hds[1]); |
500 |
icp_control_init(0xcb000000);
|
501 |
pl050_init(0x18000000, pic, 3, 0); |
502 |
pl050_init(0x19000000, pic, 4, 1); |
503 |
if (nd_table[0].vlan) { |
504 |
if (nd_table[0].model == NULL |
505 |
|| strcmp(nd_table[0].model, "smc91c111") == 0) { |
506 |
smc91c111_init(&nd_table[0], 0xc8000000, pic, 27); |
507 |
} else {
|
508 |
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
509 |
exit (1);
|
510 |
} |
511 |
} |
512 |
pl110_init(ds, 0xc0000000, pic, 22, 0); |
513 |
|
514 |
arm_load_kernel(env, ram_size, kernel_filename, kernel_cmdline, |
515 |
initrd_filename, 0x113);
|
516 |
} |
517 |
|
518 |
QEMUMachine integratorcp_machine = { |
519 |
"integratorcp",
|
520 |
"ARM Integrator/CP (ARM926EJ-S)",
|
521 |
integratorcp_init, |
522 |
}; |