root / hw / mips_timer.c @ 50d3eeae
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#include "vl.h" |
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void cpu_mips_irqctrl_init (void) |
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{
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} |
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/* XXX: do not use a global */
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uint32_t cpu_mips_get_random (CPUState *env) |
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{
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static uint32_t seed = 0; |
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uint32_t idx; |
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seed = seed * 314159 + 1; |
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idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
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return idx;
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} |
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/* MIPS R4K timer */
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uint32_t cpu_mips_get_count (CPUState *env) |
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{
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return env->CP0_Count +
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(uint32_t)muldiv64(qemu_get_clock(vm_clock), |
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100 * 1000 * 1000, ticks_per_sec); |
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} |
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static void cpu_mips_update_count (CPUState *env, uint32_t count, |
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uint32_t compare) |
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{
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uint64_t now, next; |
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uint32_t tmp; |
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if (env->CP0_Cause & (1 << CP0Ca_DC)) |
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return;
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tmp = count; |
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if (count == compare)
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tmp++; |
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now = qemu_get_clock(vm_clock); |
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next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000); |
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if (next == now)
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next++; |
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#if 0
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if (logfile) {
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fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",
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__func__, now, count, compare, next - now);
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}
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#endif
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/* Store new count and compare registers */
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env->CP0_Compare = compare; |
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env->CP0_Count = |
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count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec); |
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/* Adjust timer */
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qemu_mod_timer(env->timer, next); |
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} |
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void cpu_mips_store_count (CPUState *env, uint32_t value)
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{
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cpu_mips_update_count(env, value, env->CP0_Compare); |
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} |
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void cpu_mips_store_compare (CPUState *env, uint32_t value)
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{
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cpu_mips_update_count(env, cpu_mips_get_count(env), value); |
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if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) |
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env->CP0_Cause &= ~(1 << CP0Ca_TI);
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cpu_mips_irq_request(env, 7, 0); |
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} |
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static void mips_timer_cb (void *opaque) |
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{
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CPUState *env; |
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env = opaque; |
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#if 0
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if (logfile) {
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fprintf(logfile, "%s\n", __func__);
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}
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#endif
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cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare); |
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if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) |
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env->CP0_Cause |= 1 << CP0Ca_TI;
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cpu_mips_irq_request(env, 7, 1); |
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} |
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void cpu_mips_clock_init (CPUState *env)
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{
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env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); |
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env->CP0_Compare = 0;
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cpu_mips_update_count(env, 1, 0); |
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} |
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