Revision 50d8ff8b
| b/hw/acpi_piix4.c | ||
|---|---|---|
| 27 | 27 |
|
| 28 | 28 |
//#define DEBUG |
| 29 | 29 |
|
| 30 |
#ifdef DEBUG |
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# define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
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#else |
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# define PIIX4_DPRINTF(format, ...) do { } while (0)
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#endif |
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|
|
| 30 | 36 |
#define ACPI_DBG_IO_ADDR 0xb044 |
| 31 | 37 |
|
| 32 | 38 |
#define GPE_BASE 0xafe0 |
| ... | ... | |
| 172 | 178 |
default: |
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break; |
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} |
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#ifdef DEBUG |
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printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
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#endif |
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PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val);
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} |
| 179 | 183 |
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| 180 | 184 |
static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) |
| ... | ... | |
| 197 | 201 |
val = 0; |
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break; |
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} |
| 200 |
#ifdef DEBUG |
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printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
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#endif |
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PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val);
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return val; |
| 204 | 206 |
} |
| 205 | 207 |
|
| 206 | 208 |
static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
| 207 | 209 |
{
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// PIIX4PMState *s = opaque; |
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#ifdef DEBUG |
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addr &= 0x3f; |
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printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
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#endif |
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PIIX4_DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr & 0x3f, val);
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| 213 | 212 |
} |
| 214 | 213 |
|
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static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) |
| ... | ... | |
| 226 | 225 |
val = 0; |
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break; |
| 228 | 227 |
} |
| 229 |
#ifdef DEBUG |
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printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
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#endif |
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PIIX4_DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
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return val; |
| 233 | 230 |
} |
| 234 | 231 |
|
| ... | ... | |
| 252 | 249 |
|
| 253 | 250 |
static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) |
| 254 | 251 |
{
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#if defined(DEBUG) |
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printf("ACPI: DBG: 0x%08x\n", val);
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#endif |
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PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
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| 258 | 253 |
} |
| 259 | 254 |
|
| 260 | 255 |
static void pm_io_space_update(PIIX4PMState *s) |
| ... | ... | |
| 266 | 261 |
pm_io_base &= 0xffc0; |
| 267 | 262 |
|
| 268 | 263 |
/* XXX: need to improve memory and ioport allocation */ |
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#if defined(DEBUG) |
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printf("PM: mapping to 0x%x\n", pm_io_base);
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#endif |
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PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
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| 272 | 265 |
register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); |
| 273 | 266 |
register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); |
| 274 | 267 |
register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); |
| ... | ... | |
| 456 | 449 |
break; |
| 457 | 450 |
} |
| 458 | 451 |
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#if defined(DEBUG) |
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printf("gpe read %x == %x\n", addr, val);
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#endif |
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PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
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| 462 | 453 |
return val; |
| 463 | 454 |
} |
| 464 | 455 |
|
| ... | ... | |
| 498 | 489 |
break; |
| 499 | 490 |
} |
| 500 | 491 |
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#if defined(DEBUG) |
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printf("gpe write %x <== %d\n", addr, val);
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#endif |
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PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
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| 504 | 493 |
} |
| 505 | 494 |
|
| 506 | 495 |
static uint32_t pcihotplug_read(void *opaque, uint32_t addr) |
| ... | ... | |
| 518 | 507 |
break; |
| 519 | 508 |
} |
| 520 | 509 |
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#if defined(DEBUG) |
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printf("pcihotplug read %x == %x\n", addr, val);
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#endif |
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PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
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return val; |
| 525 | 512 |
} |
| 526 | 513 |
|
| ... | ... | |
| 536 | 523 |
break; |
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} |
| 538 | 525 |
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#if defined(DEBUG) |
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printf("pcihotplug write %x <== %d\n", addr, val);
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#endif |
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PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
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| 542 | 527 |
} |
| 543 | 528 |
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static uint32_t pciej_read(void *opaque, uint32_t addr) |
| 545 | 530 |
{
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#if defined(DEBUG) |
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printf("pciej read %x\n", addr);
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#endif |
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PIIX4_DPRINTF("pciej read %x\n", addr);
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return 0; |
| 550 | 533 |
} |
| 551 | 534 |
|
| ... | ... | |
| 564 | 547 |
} |
| 565 | 548 |
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| 566 | 549 |
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#if defined(DEBUG) |
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printf("pciej write %x <== %d\n", addr, val);
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#endif |
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PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
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| 570 | 551 |
} |
| 571 | 552 |
|
| 572 | 553 |
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state); |
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