root / exec-all.h @ 5169202b
History | View | Annotate | Download (13 kB)
1 | d4e8164f | bellard | /*
|
---|---|---|---|
2 | d4e8164f | bellard | * internal execution defines for qemu
|
3 | 5fafdf24 | ths | *
|
4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
|
5 | d4e8164f | bellard | *
|
6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
|
7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
|
9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | d4e8164f | bellard | *
|
11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
|
12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | d4e8164f | bellard | * Lesser General Public License for more details.
|
15 | d4e8164f | bellard | *
|
16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
18 | d4e8164f | bellard | */
|
19 | d4e8164f | bellard | |
20 | 875cdcf6 | aliguori | #ifndef _EXEC_ALL_H_
|
21 | 875cdcf6 | aliguori | #define _EXEC_ALL_H_
|
22 | 7d99a001 | blueswir1 | |
23 | 7d99a001 | blueswir1 | #include "qemu-common.h" |
24 | 7d99a001 | blueswir1 | |
25 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
|
26 | de9a95f0 | aurel32 | #define DEBUG_DISAS
|
27 | b346ff46 | bellard | |
28 | b346ff46 | bellard | /* is_jmp field values */
|
29 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
30 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
31 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
32 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
33 | b346ff46 | bellard | |
34 | 2e70f6ef | pbrook | typedef struct TranslationBlock TranslationBlock; |
35 | b346ff46 | bellard | |
36 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
|
37 | e83a8673 | edgar_igl | #define MAX_OP_PER_INSTR 64 |
38 | 0115be31 | pbrook | /* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
|
39 | 0115be31 | pbrook | #define MAX_OPC_PARAM 10 |
40 | b346ff46 | bellard | #define OPC_BUF_SIZE 512 |
41 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
|
42 | b346ff46 | bellard | |
43 | a208e54a | pbrook | /* Maximum size a TCG op can expand to. This is complicated because a
|
44 | a208e54a | pbrook | single op may require several host instructions and regirster reloads.
|
45 | a208e54a | pbrook | For now take a wild guess at 128 bytes, which should allow at least
|
46 | a208e54a | pbrook | a couple of fixup instructions per argument. */
|
47 | a208e54a | pbrook | #define TCG_MAX_OP_SIZE 128 |
48 | a208e54a | pbrook | |
49 | 0115be31 | pbrook | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
|
50 | b346ff46 | bellard | |
51 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
|
52 | c27004ec | bellard | extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
|
53 | 66e85a21 | bellard | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
|
54 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
|
55 | 2e70f6ef | pbrook | extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
|
56 | c3278b7b | bellard | extern target_ulong gen_opc_jump_pc[2]; |
57 | 30d6cb84 | bellard | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
|
58 | b346ff46 | bellard | |
59 | 79383c9c | blueswir1 | #include "qemu-log.h" |
60 | b346ff46 | bellard | |
61 | 2cfc5f17 | ths | void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
62 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
63 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, struct TranslationBlock *tb, |
64 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc); |
65 | d2856f1a | aurel32 | |
66 | d07bde88 | blueswir1 | unsigned long code_gen_max_block_size(void); |
67 | 57fec1fe | bellard | void cpu_gen_init(void); |
68 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
69 | d07bde88 | blueswir1 | int *gen_code_size_ptr);
|
70 | 5fafdf24 | ths | int cpu_restore_state(struct TranslationBlock *tb, |
71 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
72 | 58fe2f10 | bellard | void *puc);
|
73 | 5fafdf24 | ths | int cpu_restore_state_copy(struct TranslationBlock *tb, |
74 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
75 | 58fe2f10 | bellard | void *puc);
|
76 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
77 | 2e70f6ef | pbrook | void cpu_io_recompile(CPUState *env, void *retaddr); |
78 | 2e70f6ef | pbrook | TranslationBlock *tb_gen_code(CPUState *env, |
79 | 2e70f6ef | pbrook | target_ulong pc, target_ulong cs_base, int flags,
|
80 | 2e70f6ef | pbrook | int cflags);
|
81 | 6a00d601 | bellard | void cpu_exec_init(CPUState *env);
|
82 | a5e50b26 | malc | void QEMU_NORETURN cpu_loop_exit(void); |
83 | 53a5960a | pbrook | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
84 | 00f82b8a | aurel32 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
|
85 | 2e12669a | bellard | int is_cpu_write_access);
|
86 | 4390df51 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end);
|
87 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
|
88 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
89 | 5fafdf24 | ths | int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
|
90 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
|
91 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu); |
92 | 4d7a0880 | blueswir1 | static inline int tlb_set_page(CPUState *env1, target_ulong vaddr, |
93 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
|
94 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
95 | 84b7b8e7 | bellard | { |
96 | 84b7b8e7 | bellard | if (prot & PAGE_READ)
|
97 | 84b7b8e7 | bellard | prot |= PAGE_EXEC; |
98 | 4d7a0880 | blueswir1 | return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
|
99 | 84b7b8e7 | bellard | } |
100 | d4e8164f | bellard | |
101 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
102 | d4e8164f | bellard | |
103 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
104 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
105 | 4390df51 | bellard | |
106 | 26a5f13b | bellard | #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024) |
107 | d4e8164f | bellard | |
108 | 4390df51 | bellard | /* estimated block size for TB allocation */
|
109 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
|
110 | 4390df51 | bellard | according to the host CPU */
|
111 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
|
112 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
113 | 4390df51 | bellard | #else
|
114 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
115 | 4390df51 | bellard | #endif
|
116 | 4390df51 | bellard | |
117 | a8cd70fc | Filip Navara | #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
|
118 | d4e8164f | bellard | #define USE_DIRECT_JUMP
|
119 | d4e8164f | bellard | #endif
|
120 | d4e8164f | bellard | |
121 | 2e70f6ef | pbrook | struct TranslationBlock {
|
122 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
|
123 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
|
124 | c068688b | j_mayer | uint64_t flags; /* flags defining in which context the code was generated */
|
125 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
|
126 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
|
127 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
|
128 | 2e70f6ef | pbrook | #define CF_COUNT_MASK 0x7fff |
129 | 2e70f6ef | pbrook | #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ |
130 | 58fe2f10 | bellard | |
131 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
|
132 | 4390df51 | bellard | /* next matching tb for physical address. */
|
133 | 5fafdf24 | ths | struct TranslationBlock *phys_hash_next;
|
134 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
|
135 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
|
136 | 5fafdf24 | ths | struct TranslationBlock *page_next[2]; |
137 | 5fafdf24 | ths | target_ulong page_addr[2];
|
138 | 4390df51 | bellard | |
139 | d4e8164f | bellard | /* the following data are used to directly call another TB from
|
140 | d4e8164f | bellard | the code of this one. */
|
141 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
142 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
|
143 | 4cbb86e1 | bellard | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
144 | d4e8164f | bellard | #else
|
145 | 57fec1fe | bellard | unsigned long tb_next[2]; /* address of jump generated code */ |
146 | d4e8164f | bellard | #endif
|
147 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
|
148 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
|
149 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
|
150 | d4e8164f | bellard | jmp_first */
|
151 | 5fafdf24 | ths | struct TranslationBlock *jmp_next[2]; |
152 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
|
153 | 2e70f6ef | pbrook | uint32_t icount; |
154 | 2e70f6ef | pbrook | }; |
155 | d4e8164f | bellard | |
156 | b362e5e0 | pbrook | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
157 | b362e5e0 | pbrook | { |
158 | b362e5e0 | pbrook | target_ulong tmp; |
159 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
160 | b5e19d4c | edgar_igl | return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
|
161 | b362e5e0 | pbrook | } |
162 | b362e5e0 | pbrook | |
163 | 8a40a180 | bellard | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
164 | d4e8164f | bellard | { |
165 | b362e5e0 | pbrook | target_ulong tmp; |
166 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
167 | b5e19d4c | edgar_igl | return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
|
168 | b5e19d4c | edgar_igl | | (tmp & TB_JMP_ADDR_MASK)); |
169 | d4e8164f | bellard | } |
170 | d4e8164f | bellard | |
171 | 4390df51 | bellard | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
172 | 4390df51 | bellard | { |
173 | 4390df51 | bellard | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
174 | 4390df51 | bellard | } |
175 | 4390df51 | bellard | |
176 | c27004ec | bellard | TranslationBlock *tb_alloc(target_ulong pc); |
177 | 2e70f6ef | pbrook | void tb_free(TranslationBlock *tb);
|
178 | 0124311e | bellard | void tb_flush(CPUState *env);
|
179 | 5fafdf24 | ths | void tb_link_phys(TranslationBlock *tb,
|
180 | 4390df51 | bellard | target_ulong phys_pc, target_ulong phys_page2); |
181 | 2e70f6ef | pbrook | void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
|
182 | d4e8164f | bellard | |
183 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
|
184 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
|
185 | 26a5f13b | bellard | extern int code_gen_max_blocks; |
186 | d4e8164f | bellard | |
187 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
|
188 | 4390df51 | bellard | |
189 | e58ffeb3 | malc | #if defined(_ARCH_PPC)
|
190 | 810260a8 | malc | extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr); |
191 | 810260a8 | malc | #define tb_set_jmp_target1 ppc_tb_set_jmp_target
|
192 | 57fec1fe | bellard | #elif defined(__i386__) || defined(__x86_64__)
|
193 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
194 | 4390df51 | bellard | { |
195 | 4390df51 | bellard | /* patch the branch destination */
|
196 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
|
197 | 1235fc06 | ths | /* no need to flush icache explicitly */
|
198 | 4390df51 | bellard | } |
199 | 811d4cf4 | balrog | #elif defined(__arm__)
|
200 | 811d4cf4 | balrog | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
201 | 811d4cf4 | balrog | { |
202 | 3233f0d4 | balrog | #if QEMU_GNUC_PREREQ(4, 1) |
203 | 3233f0d4 | balrog | void __clear_cache(char *beg, char *end); |
204 | 3233f0d4 | balrog | #else
|
205 | 811d4cf4 | balrog | register unsigned long _beg __asm ("a1"); |
206 | 811d4cf4 | balrog | register unsigned long _end __asm ("a2"); |
207 | 811d4cf4 | balrog | register unsigned long _flg __asm ("a3"); |
208 | 3233f0d4 | balrog | #endif
|
209 | 811d4cf4 | balrog | |
210 | 811d4cf4 | balrog | /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
|
211 | 811d4cf4 | balrog | *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff; |
212 | 811d4cf4 | balrog | |
213 | 3233f0d4 | balrog | #if QEMU_GNUC_PREREQ(4, 1) |
214 | 3233f0d4 | balrog | __clear_cache((char *) jmp_addr, (char *) jmp_addr + 4); |
215 | 3233f0d4 | balrog | #else
|
216 | 811d4cf4 | balrog | /* flush icache */
|
217 | 811d4cf4 | balrog | _beg = jmp_addr; |
218 | 811d4cf4 | balrog | _end = jmp_addr + 4;
|
219 | 811d4cf4 | balrog | _flg = 0;
|
220 | 811d4cf4 | balrog | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); |
221 | 3233f0d4 | balrog | #endif
|
222 | 811d4cf4 | balrog | } |
223 | 4390df51 | bellard | #endif
|
224 | d4e8164f | bellard | |
225 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
226 | 4cbb86e1 | bellard | int n, unsigned long addr) |
227 | 4cbb86e1 | bellard | { |
228 | 4cbb86e1 | bellard | unsigned long offset; |
229 | 4cbb86e1 | bellard | |
230 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
231 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
232 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n + 2];
|
233 | 4cbb86e1 | bellard | if (offset != 0xffff) |
234 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
235 | 4cbb86e1 | bellard | } |
236 | 4cbb86e1 | bellard | |
237 | d4e8164f | bellard | #else
|
238 | d4e8164f | bellard | |
239 | d4e8164f | bellard | /* set the jump target */
|
240 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
241 | d4e8164f | bellard | int n, unsigned long addr) |
242 | d4e8164f | bellard | { |
243 | 95f7652d | bellard | tb->tb_next[n] = addr; |
244 | d4e8164f | bellard | } |
245 | d4e8164f | bellard | |
246 | d4e8164f | bellard | #endif
|
247 | d4e8164f | bellard | |
248 | 5fafdf24 | ths | static inline void tb_add_jump(TranslationBlock *tb, int n, |
249 | d4e8164f | bellard | TranslationBlock *tb_next) |
250 | d4e8164f | bellard | { |
251 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
|
252 | cf25629d | bellard | if (!tb->jmp_next[n]) {
|
253 | cf25629d | bellard | /* patch the native jump address */
|
254 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
255 | 3b46e624 | ths | |
256 | cf25629d | bellard | /* add in TB jmp circular list */
|
257 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
258 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
|
259 | cf25629d | bellard | } |
260 | d4e8164f | bellard | } |
261 | d4e8164f | bellard | |
262 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
263 | a513fe19 | bellard | |
264 | 33417e70 | bellard | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
265 | 33417e70 | bellard | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
266 | a4193c8a | bellard | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
267 | 33417e70 | bellard | |
268 | d5975363 | pbrook | #include "qemu-lock.h" |
269 | d4e8164f | bellard | |
270 | d4e8164f | bellard | extern spinlock_t tb_lock;
|
271 | d4e8164f | bellard | |
272 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
273 | 6e59c1db | bellard | |
274 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
|
275 | 6e59c1db | bellard | |
276 | 6ebbf390 | j_mayer | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
277 | 6e59c1db | bellard | void *retaddr);
|
278 | 6e59c1db | bellard | |
279 | 79383c9c | blueswir1 | #include "softmmu_defs.h" |
280 | 79383c9c | blueswir1 | |
281 | 6ebbf390 | j_mayer | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
282 | 6e59c1db | bellard | #define MEMSUFFIX _code
|
283 | 6e59c1db | bellard | #define env cpu_single_env
|
284 | 6e59c1db | bellard | |
285 | 6e59c1db | bellard | #define DATA_SIZE 1 |
286 | 6e59c1db | bellard | #include "softmmu_header.h" |
287 | 6e59c1db | bellard | |
288 | 6e59c1db | bellard | #define DATA_SIZE 2 |
289 | 6e59c1db | bellard | #include "softmmu_header.h" |
290 | 6e59c1db | bellard | |
291 | 6e59c1db | bellard | #define DATA_SIZE 4 |
292 | 6e59c1db | bellard | #include "softmmu_header.h" |
293 | 6e59c1db | bellard | |
294 | c27004ec | bellard | #define DATA_SIZE 8 |
295 | c27004ec | bellard | #include "softmmu_header.h" |
296 | c27004ec | bellard | |
297 | 6e59c1db | bellard | #undef ACCESS_TYPE
|
298 | 6e59c1db | bellard | #undef MEMSUFFIX
|
299 | 6e59c1db | bellard | #undef env
|
300 | 6e59c1db | bellard | |
301 | 6e59c1db | bellard | #endif
|
302 | 4390df51 | bellard | |
303 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
|
304 | 4d7a0880 | blueswir1 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) |
305 | 4390df51 | bellard | { |
306 | 4390df51 | bellard | return addr;
|
307 | 4390df51 | bellard | } |
308 | 4390df51 | bellard | #else
|
309 | 4390df51 | bellard | /* NOTE: this function can trigger an exception */
|
310 | 1ccde1cb | bellard | /* NOTE2: the returned address is not exactly the physical address: it
|
311 | 1ccde1cb | bellard | is the offset relative to phys_ram_base */
|
312 | 4d7a0880 | blueswir1 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) |
313 | 4390df51 | bellard | { |
314 | 4d7a0880 | blueswir1 | int mmu_idx, page_index, pd;
|
315 | 5579c7f3 | pbrook | void *p;
|
316 | 4390df51 | bellard | |
317 | 4d7a0880 | blueswir1 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
318 | 4d7a0880 | blueswir1 | mmu_idx = cpu_mmu_index(env1); |
319 | 551bd27f | ths | if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
|
320 | 551bd27f | ths | (addr & TARGET_PAGE_MASK))) { |
321 | c27004ec | bellard | ldub_code(addr); |
322 | c27004ec | bellard | } |
323 | 4d7a0880 | blueswir1 | pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; |
324 | 2a4188a3 | bellard | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
|
325 | 647de6ca | ths | #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
|
326 | e18231a3 | blueswir1 | do_unassigned_access(addr, 0, 1, 0, 4); |
327 | 6c36d3fa | blueswir1 | #else
|
328 | 4d7a0880 | blueswir1 | cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
329 | 6c36d3fa | blueswir1 | #endif
|
330 | 4390df51 | bellard | } |
331 | 5579c7f3 | pbrook | p = (void *)(unsigned long)addr |
332 | 5579c7f3 | pbrook | + env1->tlb_table[mmu_idx][page_index].addend; |
333 | 5579c7f3 | pbrook | return qemu_ram_addr_from_host(p);
|
334 | 4390df51 | bellard | } |
335 | 2e70f6ef | pbrook | |
336 | bf20dc07 | ths | /* Deterministic execution requires that IO only be performed on the last
|
337 | 2e70f6ef | pbrook | instruction of a TB so that interrupts take effect immediately. */
|
338 | 2e70f6ef | pbrook | static inline int can_do_io(CPUState *env) |
339 | 2e70f6ef | pbrook | { |
340 | 2e70f6ef | pbrook | if (!use_icount)
|
341 | 2e70f6ef | pbrook | return 1; |
342 | 2e70f6ef | pbrook | |
343 | 2e70f6ef | pbrook | /* If not executing code then assume we are ok. */
|
344 | 2e70f6ef | pbrook | if (!env->current_tb)
|
345 | 2e70f6ef | pbrook | return 1; |
346 | 2e70f6ef | pbrook | |
347 | 2e70f6ef | pbrook | return env->can_do_io != 0; |
348 | 2e70f6ef | pbrook | } |
349 | 4390df51 | bellard | #endif
|
350 | 9df217a3 | bellard | |
351 | 640f42e4 | blueswir1 | #ifdef CONFIG_KQEMU
|
352 | f32fc648 | bellard | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) |
353 | f32fc648 | bellard | |
354 | da260249 | bellard | #define MSR_QPI_COMMBASE 0xfabe0010 |
355 | da260249 | bellard | |
356 | 9df217a3 | bellard | int kqemu_init(CPUState *env);
|
357 | 9df217a3 | bellard | int kqemu_cpu_exec(CPUState *env);
|
358 | 9df217a3 | bellard | void kqemu_flush_page(CPUState *env, target_ulong addr);
|
359 | 9df217a3 | bellard | void kqemu_flush(CPUState *env, int global); |
360 | 4b7df22f | bellard | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
|
361 | f32fc648 | bellard | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
|
362 | da260249 | bellard | void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size,
|
363 | da260249 | bellard | ram_addr_t phys_offset); |
364 | a332e112 | bellard | void kqemu_cpu_interrupt(CPUState *env);
|
365 | f32fc648 | bellard | void kqemu_record_dump(void); |
366 | 9df217a3 | bellard | |
367 | da260249 | bellard | extern uint32_t kqemu_comm_base;
|
368 | da260249 | bellard | |
369 | 94a6b54f | pbrook | extern ram_addr_t kqemu_phys_ram_size;
|
370 | 94a6b54f | pbrook | extern uint8_t *kqemu_phys_ram_base;
|
371 | 94a6b54f | pbrook | |
372 | 9df217a3 | bellard | static inline int kqemu_is_ok(CPUState *env) |
373 | 9df217a3 | bellard | { |
374 | 9df217a3 | bellard | return(env->kqemu_enabled &&
|
375 | 5fafdf24 | ths | (env->cr[0] & CR0_PE_MASK) &&
|
376 | f32fc648 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK) && |
377 | 9df217a3 | bellard | (env->eflags & IF_MASK) && |
378 | f32fc648 | bellard | !(env->eflags & VM_MASK) && |
379 | 5fafdf24 | ths | (env->kqemu_enabled == 2 ||
|
380 | f32fc648 | bellard | ((env->hflags & HF_CPL_MASK) == 3 &&
|
381 | f32fc648 | bellard | (env->eflags & IOPL_MASK) != IOPL_MASK))); |
382 | 9df217a3 | bellard | } |
383 | 9df217a3 | bellard | |
384 | 9df217a3 | bellard | #endif
|
385 | dde2367e | aliguori | |
386 | dde2367e | aliguori | typedef void (CPUDebugExcpHandler)(CPUState *env); |
387 | dde2367e | aliguori | |
388 | dde2367e | aliguori | CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler); |
389 | 1b530a6d | aurel32 | |
390 | 1b530a6d | aurel32 | /* vl.c */
|
391 | 1b530a6d | aurel32 | extern int singlestep; |
392 | 1b530a6d | aurel32 | |
393 | 875cdcf6 | aliguori | #endif |