Revision 51cc2e78
| b/target-mips/cpu.h | ||
|---|---|---|
| 175 | 175 |
TCState active_tc; |
| 176 | 176 |
CPUMIPSFPUContext active_fpu; |
| 177 | 177 |
|
| 178 |
CPUMIPSMVPContext *mvp; |
|
| 179 |
CPUMIPSTLBContext *tlb; |
|
| 180 | 178 |
uint32_t current_tc; |
| 181 | 179 |
uint32_t current_fpu; |
| 182 | 180 |
|
| ... | ... | |
| 458 | 456 |
|
| 459 | 457 |
CPU_COMMON |
| 460 | 458 |
|
| 459 |
CPUMIPSMVPContext *mvp; |
|
| 460 |
CPUMIPSTLBContext *tlb; |
|
| 461 |
|
|
| 461 | 462 |
const mips_def_t *cpu_model; |
| 462 | 463 |
void *irq[8]; |
| 463 | 464 |
struct QEMUTimer *timer; /* Internal timer */ |
| b/target-mips/translate.c | ||
|---|---|---|
| 8598 | 8598 |
return NULL; |
| 8599 | 8599 |
env = qemu_mallocz(sizeof(CPUMIPSState)); |
| 8600 | 8600 |
env->cpu_model = def; |
| 8601 |
env->cpu_model_str = cpu_model; |
|
| 8601 | 8602 |
|
| 8602 | 8603 |
cpu_exec_init(env); |
| 8603 |
env->cpu_model_str = cpu_model; |
|
| 8604 |
#ifndef CONFIG_USER_ONLY |
|
| 8605 |
mmu_init(env, def); |
|
| 8606 |
#endif |
|
| 8607 |
fpu_init(env, def); |
|
| 8608 |
mvp_init(env, def); |
|
| 8604 | 8609 |
mips_tcg_init(); |
| 8605 | 8610 |
cpu_reset(env); |
| 8606 | 8611 |
qemu_init_vcpu(env); |
| ... | ... | |
| 8615 | 8620 |
} |
| 8616 | 8621 |
|
| 8617 | 8622 |
memset(env, 0, offsetof(CPUMIPSState, breakpoints)); |
| 8618 |
|
|
| 8619 | 8623 |
tlb_flush(env, 1); |
| 8620 | 8624 |
|
| 8621 |
/* Minimal init */ |
|
| 8625 |
/* Reset registers to their default values */ |
|
| 8626 |
env->CP0_PRid = env->cpu_model->CP0_PRid; |
|
| 8627 |
env->CP0_Config0 = env->cpu_model->CP0_Config0; |
|
| 8628 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 8629 |
env->CP0_Config0 |= (1 << CP0C0_BE); |
|
| 8630 |
#endif |
|
| 8631 |
env->CP0_Config1 = env->cpu_model->CP0_Config1; |
|
| 8632 |
env->CP0_Config2 = env->cpu_model->CP0_Config2; |
|
| 8633 |
env->CP0_Config3 = env->cpu_model->CP0_Config3; |
|
| 8634 |
env->CP0_Config6 = env->cpu_model->CP0_Config6; |
|
| 8635 |
env->CP0_Config7 = env->cpu_model->CP0_Config7; |
|
| 8636 |
env->SYNCI_Step = env->cpu_model->SYNCI_Step; |
|
| 8637 |
env->CCRes = env->cpu_model->CCRes; |
|
| 8638 |
env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; |
|
| 8639 |
env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask; |
|
| 8640 |
env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl; |
|
| 8641 |
env->current_tc = 0; |
|
| 8642 |
env->SEGBITS = env->cpu_model->SEGBITS; |
|
| 8643 |
env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1); |
|
| 8644 |
#if defined(TARGET_MIPS64) |
|
| 8645 |
if (env->cpu_model->insn_flags & ISA_MIPS3) {
|
|
| 8646 |
env->SEGMask |= 3ULL << 62; |
|
| 8647 |
} |
|
| 8648 |
#endif |
|
| 8649 |
env->PABITS = env->cpu_model->PABITS; |
|
| 8650 |
env->PAMask = (target_ulong)((1ULL << env->cpu_model->PABITS) - 1); |
|
| 8651 |
env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask; |
|
| 8652 |
env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0; |
|
| 8653 |
env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask; |
|
| 8654 |
env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1; |
|
| 8655 |
env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask; |
|
| 8656 |
env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2; |
|
| 8657 |
env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask; |
|
| 8658 |
env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; |
|
| 8659 |
env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask; |
|
| 8660 |
env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; |
|
| 8661 |
env->insn_flags = env->cpu_model->insn_flags; |
|
| 8662 |
|
|
| 8622 | 8663 |
#if defined(CONFIG_USER_ONLY) |
| 8623 | 8664 |
env->hflags = MIPS_HFLAG_UM; |
| 8624 | 8665 |
/* Enable access to the SYNCI_Step register. */ |
| ... | ... | |
| 8632 | 8673 |
env->CP0_ErrorEPC = env->active_tc.PC; |
| 8633 | 8674 |
} |
| 8634 | 8675 |
env->active_tc.PC = (int32_t)0xBFC00000; |
| 8676 |
env->CP0_Random = env->tlb->nb_tlb - 1; |
|
| 8677 |
env->tlb->tlb_in_use = env->tlb->nb_tlb; |
|
| 8635 | 8678 |
env->CP0_Wired = 0; |
| 8636 | 8679 |
/* SMP not implemented */ |
| 8637 | 8680 |
env->CP0_EBase = 0x80000000; |
| ... | ... | |
| 8653 | 8696 |
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); |
| 8654 | 8697 |
env->hflags = MIPS_HFLAG_CP0; |
| 8655 | 8698 |
#endif |
| 8699 |
#if defined(TARGET_MIPS64) |
|
| 8700 |
if (env->cpu_model->insn_flags & ISA_MIPS3) {
|
|
| 8701 |
env->hflags |= MIPS_HFLAG_64; |
|
| 8702 |
} |
|
| 8703 |
#endif |
|
| 8656 | 8704 |
env->exception_index = EXCP_NONE; |
| 8657 |
cpu_mips_register(env, env->cpu_model); |
|
| 8658 | 8705 |
} |
| 8659 | 8706 |
|
| 8660 | 8707 |
void gen_pc_load(CPUState *env, TranslationBlock *tb, |
| b/target-mips/translate_init.c | ||
|---|---|---|
| 481 | 481 |
default: |
| 482 | 482 |
cpu_abort(env, "MMU type not supported\n"); |
| 483 | 483 |
} |
| 484 |
env->CP0_Random = env->tlb->nb_tlb - 1; |
|
| 485 |
env->tlb->tlb_in_use = env->tlb->nb_tlb; |
|
| 486 | 484 |
} |
| 487 | 485 |
#endif /* CONFIG_USER_ONLY */ |
| 488 | 486 |
|
| ... | ... | |
| 530 | 528 |
(0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | |
| 531 | 529 |
(0x1 << CP0MVPC1_PCP1); |
| 532 | 530 |
} |
| 533 |
|
|
| 534 |
static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def) |
|
| 535 |
{
|
|
| 536 |
env->CP0_PRid = def->CP0_PRid; |
|
| 537 |
env->CP0_Config0 = def->CP0_Config0; |
|
| 538 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 539 |
env->CP0_Config0 |= (1 << CP0C0_BE); |
|
| 540 |
#endif |
|
| 541 |
env->CP0_Config1 = def->CP0_Config1; |
|
| 542 |
env->CP0_Config2 = def->CP0_Config2; |
|
| 543 |
env->CP0_Config3 = def->CP0_Config3; |
|
| 544 |
env->CP0_Config6 = def->CP0_Config6; |
|
| 545 |
env->CP0_Config7 = def->CP0_Config7; |
|
| 546 |
env->SYNCI_Step = def->SYNCI_Step; |
|
| 547 |
env->CCRes = def->CCRes; |
|
| 548 |
env->CP0_Status_rw_bitmask = def->CP0_Status_rw_bitmask; |
|
| 549 |
env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask; |
|
| 550 |
env->CP0_SRSCtl = def->CP0_SRSCtl; |
|
| 551 |
env->current_tc = 0; |
|
| 552 |
env->SEGBITS = def->SEGBITS; |
|
| 553 |
env->SEGMask = (target_ulong)((1ULL << def->SEGBITS) - 1); |
|
| 554 |
#if defined(TARGET_MIPS64) |
|
| 555 |
if (def->insn_flags & ISA_MIPS3) {
|
|
| 556 |
env->hflags |= MIPS_HFLAG_64; |
|
| 557 |
env->SEGMask |= 3ULL << 62; |
|
| 558 |
} |
|
| 559 |
#endif |
|
| 560 |
env->PABITS = def->PABITS; |
|
| 561 |
env->PAMask = (target_ulong)((1ULL << def->PABITS) - 1); |
|
| 562 |
env->CP0_SRSConf0_rw_bitmask = def->CP0_SRSConf0_rw_bitmask; |
|
| 563 |
env->CP0_SRSConf0 = def->CP0_SRSConf0; |
|
| 564 |
env->CP0_SRSConf1_rw_bitmask = def->CP0_SRSConf1_rw_bitmask; |
|
| 565 |
env->CP0_SRSConf1 = def->CP0_SRSConf1; |
|
| 566 |
env->CP0_SRSConf2_rw_bitmask = def->CP0_SRSConf2_rw_bitmask; |
|
| 567 |
env->CP0_SRSConf2 = def->CP0_SRSConf2; |
|
| 568 |
env->CP0_SRSConf3_rw_bitmask = def->CP0_SRSConf3_rw_bitmask; |
|
| 569 |
env->CP0_SRSConf3 = def->CP0_SRSConf3; |
|
| 570 |
env->CP0_SRSConf4_rw_bitmask = def->CP0_SRSConf4_rw_bitmask; |
|
| 571 |
env->CP0_SRSConf4 = def->CP0_SRSConf4; |
|
| 572 |
env->insn_flags = def->insn_flags; |
|
| 573 |
|
|
| 574 |
#ifndef CONFIG_USER_ONLY |
|
| 575 |
mmu_init(env, def); |
|
| 576 |
#endif |
|
| 577 |
fpu_init(env, def); |
|
| 578 |
mvp_init(env, def); |
|
| 579 |
return 0; |
|
| 580 |
} |
|
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