root / target-mips / translate_init.c @ 51cc2e78
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/*
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* MIPS emulation for qemu: CPU initialisation routines.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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* Copyright (c) 2007 Herve Poussineau
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/* CPU / CPU family specific config register values. */
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/* Have config1, uncached coherency */
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#define MIPS_CONFIG0 \
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((1 << CP0C0_M) | (0x2 << CP0C0_K0)) |
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/* Have config2, no coprocessor2 attached, no MDMX support attached,
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no performance counters, watch registers present,
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no code compression, EJTAG present, no FPU */
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#define MIPS_CONFIG1 \
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((1 << CP0C1_M) | \
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(0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ |
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(1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ |
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(0 << CP0C1_FP))
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/* Have config3, no tertiary/secondary caches implemented */
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#define MIPS_CONFIG2 \
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((1 << CP0C2_M))
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/* No config4, no DSP ASE, no large physaddr (PABITS),
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no external interrupt controller, no vectored interupts,
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no 1kb pages, no SmartMIPS ASE, no trace logic */
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#define MIPS_CONFIG3 \
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((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ |
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(0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ |
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(0 << CP0C3_SM) | (0 << CP0C3_TL)) |
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/* Define a implementation number of 1.
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Define a major version 1, minor version 0. */
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#define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV)) |
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/* MMU types, the first four entries have the same layout as the
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CP0C0_MT field. */
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enum mips_mmu_types {
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MMU_TYPE_NONE, |
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MMU_TYPE_R4000, |
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MMU_TYPE_RESERVED, |
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MMU_TYPE_FMT, |
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MMU_TYPE_R3000, |
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MMU_TYPE_R6000, |
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MMU_TYPE_R8000 |
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}; |
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struct mips_def_t {
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const char *name; |
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int32_t CP0_PRid; |
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int32_t CP0_Config0; |
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int32_t CP0_Config1; |
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int32_t CP0_Config2; |
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int32_t CP0_Config3; |
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int32_t CP0_Config6; |
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int32_t CP0_Config7; |
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int32_t SYNCI_Step; |
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int32_t CCRes; |
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int32_t CP0_Status_rw_bitmask; |
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int32_t CP0_TCStatus_rw_bitmask; |
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int32_t CP0_SRSCtl; |
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int32_t CP1_fcr0; |
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int32_t SEGBITS; |
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int32_t PABITS; |
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int32_t CP0_SRSConf0_rw_bitmask; |
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int32_t CP0_SRSConf0; |
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int32_t CP0_SRSConf1_rw_bitmask; |
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int32_t CP0_SRSConf1; |
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int32_t CP0_SRSConf2_rw_bitmask; |
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int32_t CP0_SRSConf2; |
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int32_t CP0_SRSConf3_rw_bitmask; |
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int32_t CP0_SRSConf3; |
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int32_t CP0_SRSConf4_rw_bitmask; |
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int32_t CP0_SRSConf4; |
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int insn_flags;
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enum mips_mmu_types mmu_type;
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}; |
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/*****************************************************************************/
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/* MIPS CPU definitions */
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static const mips_def_t mips_defs[] = |
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{ |
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{ |
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.name = "4Kc",
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.CP0_PRid = 0x00018000,
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.CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1278FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32 | ASE_MIPS16, |
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.mmu_type = MMU_TYPE_R4000, |
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}, |
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{ |
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.name = "4Km",
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.CP0_PRid = 0x00018300,
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/* Config1 implemented, fixed mapping MMU,
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no virtual icache, uncached coherency. */
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.CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1258FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32 | ASE_MIPS16, |
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.mmu_type = MMU_TYPE_FMT, |
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}, |
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{ |
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.name = "4KEcR1",
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.CP0_PRid = 0x00018400,
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.CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1278FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32 | ASE_MIPS16, |
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.mmu_type = MMU_TYPE_R4000, |
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}, |
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{ |
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.name = "4KEmR1",
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.CP0_PRid = 0x00018500,
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.CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1258FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32 | ASE_MIPS16, |
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.mmu_type = MMU_TYPE_FMT, |
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}, |
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{ |
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.name = "4KEc",
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.CP0_PRid = 0x00019000,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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(MMU_TYPE_R4000 << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1278FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
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.mmu_type = MMU_TYPE_R4000, |
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}, |
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{ |
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.name = "4KEm",
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.CP0_PRid = 0x00019100,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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(MMU_TYPE_FMT << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3, |
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1258FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
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.mmu_type = MMU_TYPE_FMT, |
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}, |
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{ |
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.name = "24Kc",
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.CP0_PRid = 0x00019300,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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(MMU_TYPE_R4000 << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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.SYNCI_Step = 32,
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.CCRes = 2,
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/* No DSP implemented. */
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.CP0_Status_rw_bitmask = 0x1278FF1F,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
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.mmu_type = MMU_TYPE_R4000, |
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}, |
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{ |
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.name = "24Kf",
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.CP0_PRid = 0x00019300,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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(MMU_TYPE_R4000 << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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.SYNCI_Step = 32,
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.CCRes = 2,
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/* No DSP implemented. */
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.CP0_Status_rw_bitmask = 0x3678FF1F,
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
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.mmu_type = MMU_TYPE_R4000, |
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}, |
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{ |
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.name = "34Kf",
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.CP0_PRid = 0x00019500,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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(MMU_TYPE_R4000 << CP0C0_MT), |
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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.CP0_Config2 = MIPS_CONFIG2, |
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.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT), |
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.SYNCI_Step = 32,
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.CCRes = 2,
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/* No DSP implemented. */
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.CP0_Status_rw_bitmask = 0x3678FF1F,
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/* No DSP implemented. */
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.CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | |
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(1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | |
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(0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | |
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(1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | |
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(0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | |
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(0xff << CP0TCSt_TASID),
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), |
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.CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
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.CP0_SRSConf0_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | |
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(0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), |
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.CP0_SRSConf1_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | |
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(0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), |
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.CP0_SRSConf2_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | |
277 |
(0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), |
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.CP0_SRSConf3_rw_bitmask = 0x3fffffff,
|
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.CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | |
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(0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), |
281 |
.CP0_SRSConf4_rw_bitmask = 0x3fffffff,
|
282 |
.CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
|
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(0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), |
284 |
.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, |
287 |
.mmu_type = MMU_TYPE_R4000, |
288 |
}, |
289 |
#if defined(TARGET_MIPS64)
|
290 |
{ |
291 |
.name = "R4000",
|
292 |
.CP0_PRid = 0x00000400,
|
293 |
/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
|
294 |
.CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |
295 |
/* Note: Config1 is only used internally, the R4000 has only Config0. */
|
296 |
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
297 |
.SYNCI_Step = 16,
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298 |
.CCRes = 2,
|
299 |
.CP0_Status_rw_bitmask = 0x3678FFFF,
|
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/* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
|
301 |
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), |
302 |
.SEGBITS = 40,
|
303 |
.PABITS = 36,
|
304 |
.insn_flags = CPU_MIPS3, |
305 |
.mmu_type = MMU_TYPE_R4000, |
306 |
}, |
307 |
{ |
308 |
.name = "VR5432",
|
309 |
.CP0_PRid = 0x00005400,
|
310 |
/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
|
311 |
.CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |
312 |
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
313 |
.SYNCI_Step = 16,
|
314 |
.CCRes = 2,
|
315 |
.CP0_Status_rw_bitmask = 0x3678FFFF,
|
316 |
/* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
|
317 |
.CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), |
318 |
.SEGBITS = 40,
|
319 |
.PABITS = 32,
|
320 |
.insn_flags = CPU_VR54XX, |
321 |
.mmu_type = MMU_TYPE_R4000, |
322 |
}, |
323 |
{ |
324 |
.name = "5Kc",
|
325 |
.CP0_PRid = 0x00018100,
|
326 |
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
|
327 |
(MMU_TYPE_R4000 << CP0C0_MT), |
328 |
.CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
|
329 |
(1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
330 |
(1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
331 |
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
332 |
.CP0_Config2 = MIPS_CONFIG2, |
333 |
.CP0_Config3 = MIPS_CONFIG3, |
334 |
.SYNCI_Step = 32,
|
335 |
.CCRes = 2,
|
336 |
.CP0_Status_rw_bitmask = 0x32F8FFFF,
|
337 |
.SEGBITS = 42,
|
338 |
.PABITS = 36,
|
339 |
.insn_flags = CPU_MIPS64, |
340 |
.mmu_type = MMU_TYPE_R4000, |
341 |
}, |
342 |
{ |
343 |
.name = "5Kf",
|
344 |
.CP0_PRid = 0x00018100,
|
345 |
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
|
346 |
(MMU_TYPE_R4000 << CP0C0_MT), |
347 |
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | |
348 |
(1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
349 |
(1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
350 |
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
351 |
.CP0_Config2 = MIPS_CONFIG2, |
352 |
.CP0_Config3 = MIPS_CONFIG3, |
353 |
.SYNCI_Step = 32,
|
354 |
.CCRes = 2,
|
355 |
.CP0_Status_rw_bitmask = 0x36F8FFFF,
|
356 |
/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
|
357 |
.CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | |
358 |
(0x81 << FCR0_PRID) | (0x0 << FCR0_REV), |
359 |
.SEGBITS = 42,
|
360 |
.PABITS = 36,
|
361 |
.insn_flags = CPU_MIPS64, |
362 |
.mmu_type = MMU_TYPE_R4000, |
363 |
}, |
364 |
{ |
365 |
.name = "20Kc",
|
366 |
/* We emulate a later version of the 20Kc, earlier ones had a broken
|
367 |
WAIT instruction. */
|
368 |
.CP0_PRid = 0x000182a0,
|
369 |
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
|
370 |
(MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
|
371 |
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | |
372 |
(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
373 |
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
374 |
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
375 |
.CP0_Config2 = MIPS_CONFIG2, |
376 |
.CP0_Config3 = MIPS_CONFIG3, |
377 |
.SYNCI_Step = 32,
|
378 |
.CCRes = 1,
|
379 |
.CP0_Status_rw_bitmask = 0x36FBFFFF,
|
380 |
/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
|
381 |
.CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | |
382 |
(1 << FCR0_D) | (1 << FCR0_S) | |
383 |
(0x82 << FCR0_PRID) | (0x0 << FCR0_REV), |
384 |
.SEGBITS = 40,
|
385 |
.PABITS = 36,
|
386 |
.insn_flags = CPU_MIPS64 | ASE_MIPS3D, |
387 |
.mmu_type = MMU_TYPE_R4000, |
388 |
}, |
389 |
{ |
390 |
/* A generic CPU providing MIPS64 Release 2 features.
|
391 |
FIXME: Eventually this should be replaced by a real CPU model. */
|
392 |
.name = "MIPS64R2-generic",
|
393 |
.CP0_PRid = 0x00010000,
|
394 |
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
395 |
(MMU_TYPE_R4000 << CP0C0_MT), |
396 |
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |
397 |
(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
398 |
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
399 |
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
400 |
.CP0_Config2 = MIPS_CONFIG2, |
401 |
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
|
402 |
.SYNCI_Step = 32,
|
403 |
.CCRes = 2,
|
404 |
.CP0_Status_rw_bitmask = 0x36FBFFFF,
|
405 |
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | |
406 |
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
407 |
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), |
408 |
.SEGBITS = 42,
|
409 |
/* The architectural limit is 59, but we have hardcoded 36 bit
|
410 |
in some places...
|
411 |
.PABITS = 59, */ /* the architectural limit */ |
412 |
.PABITS = 36,
|
413 |
.insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, |
414 |
.mmu_type = MMU_TYPE_R4000, |
415 |
}, |
416 |
#endif
|
417 |
}; |
418 |
|
419 |
static const mips_def_t *cpu_mips_find_by_name (const char *name) |
420 |
{ |
421 |
int i;
|
422 |
|
423 |
for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |
424 |
if (strcasecmp(name, mips_defs[i].name) == 0) { |
425 |
return &mips_defs[i];
|
426 |
} |
427 |
} |
428 |
return NULL; |
429 |
} |
430 |
|
431 |
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
432 |
{ |
433 |
int i;
|
434 |
|
435 |
for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |
436 |
(*cpu_fprintf)(f, "MIPS '%s'\n",
|
437 |
mips_defs[i].name); |
438 |
} |
439 |
} |
440 |
|
441 |
#ifndef CONFIG_USER_ONLY
|
442 |
static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
443 |
{ |
444 |
env->tlb->nb_tlb = 1;
|
445 |
env->tlb->map_address = &no_mmu_map_address; |
446 |
} |
447 |
|
448 |
static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
449 |
{ |
450 |
env->tlb->nb_tlb = 1;
|
451 |
env->tlb->map_address = &fixed_mmu_map_address; |
452 |
} |
453 |
|
454 |
static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
455 |
{ |
456 |
env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
457 |
env->tlb->map_address = &r4k_map_address; |
458 |
env->tlb->helper_tlbwi = r4k_helper_tlbwi; |
459 |
env->tlb->helper_tlbwr = r4k_helper_tlbwr; |
460 |
env->tlb->helper_tlbp = r4k_helper_tlbp; |
461 |
env->tlb->helper_tlbr = r4k_helper_tlbr; |
462 |
} |
463 |
|
464 |
static void mmu_init (CPUMIPSState *env, const mips_def_t *def) |
465 |
{ |
466 |
env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext));
|
467 |
|
468 |
switch (def->mmu_type) {
|
469 |
case MMU_TYPE_NONE:
|
470 |
no_mmu_init(env, def); |
471 |
break;
|
472 |
case MMU_TYPE_R4000:
|
473 |
r4k_mmu_init(env, def); |
474 |
break;
|
475 |
case MMU_TYPE_FMT:
|
476 |
fixed_mmu_init(env, def); |
477 |
break;
|
478 |
case MMU_TYPE_R3000:
|
479 |
case MMU_TYPE_R6000:
|
480 |
case MMU_TYPE_R8000:
|
481 |
default:
|
482 |
cpu_abort(env, "MMU type not supported\n");
|
483 |
} |
484 |
} |
485 |
#endif /* CONFIG_USER_ONLY */ |
486 |
|
487 |
static void fpu_init (CPUMIPSState *env, const mips_def_t *def) |
488 |
{ |
489 |
int i;
|
490 |
|
491 |
for (i = 0; i < MIPS_FPU_MAX; i++) |
492 |
env->fpus[i].fcr0 = def->CP1_fcr0; |
493 |
|
494 |
memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); |
495 |
#if defined(CONFIG_USER_ONLY)
|
496 |
if (env->CP0_Config1 & (1 << CP0C1_FP)) |
497 |
env->hflags |= MIPS_HFLAG_FPU; |
498 |
#ifdef TARGET_MIPS64
|
499 |
if (env->active_fpu.fcr0 & (1 << FCR0_F64)) |
500 |
env->hflags |= MIPS_HFLAG_F64; |
501 |
#endif
|
502 |
#endif
|
503 |
} |
504 |
|
505 |
static void mvp_init (CPUMIPSState *env, const mips_def_t *def) |
506 |
{ |
507 |
env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext));
|
508 |
|
509 |
/* MVPConf1 implemented, TLB sharable, no gating storage support,
|
510 |
programmable cache partitioning implemented, number of allocatable
|
511 |
and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
|
512 |
implemented, 5 TCs implemented. */
|
513 |
env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | |
514 |
(0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | |
515 |
// TODO: actually do 2 VPEs.
|
516 |
// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
|
517 |
// (0x04 << CP0MVPC0_PTC);
|
518 |
(1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | |
519 |
(0x04 << CP0MVPC0_PTC);
|
520 |
#if !defined(CONFIG_USER_ONLY)
|
521 |
/* Usermode has no TLB support */
|
522 |
env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); |
523 |
#endif
|
524 |
|
525 |
/* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
|
526 |
no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
|
527 |
env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | |
528 |
(0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | |
529 |
(0x1 << CP0MVPC1_PCP1);
|
530 |
} |