Revision 51fec3cc hw/omap_clk.c
| b/hw/omap_clk.c | ||
|---|---|---|
| 510 | 510 |
.parent = &xtal_osc32k, |
| 511 | 511 |
}; |
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static struct clk ref_clk = {
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.name = "ref_clk", |
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
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.rate = 12000000, /* 12 MHz or 13 MHz or 19.2 MHz */ |
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/*.parent = sys.xtalin */ |
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}; |
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static struct clk apll_96m = {
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| 514 | 521 |
.name = "apll_96m", |
| 515 | 522 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
| 516 | 523 |
.rate = 96000000, |
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/*.parent = sys.xtalin */
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/*.parent = ref_clk */
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}; |
| 519 | 526 |
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static struct clk apll_54m = {
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| 521 | 528 |
.name = "apll_54m", |
| 522 | 529 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
| 523 | 530 |
.rate = 54000000, |
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/*.parent = sys.xtalin */
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/*.parent = ref_clk */
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}; |
| 526 | 533 |
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static struct clk sys_clk = {
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| ... | ... | |
| 541 | 548 |
static struct clk dpll_ck = {
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| 542 | 549 |
.name = "dpll", |
| 543 | 550 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
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/*.parent = sys.xtalin */
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.parent = &ref_clk,
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| 545 | 552 |
}; |
| 546 | 553 |
|
| 547 | 554 |
static struct clk dpll_x2_ck = {
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| 548 | 555 |
.name = "dpll_x2", |
| 549 | 556 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
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/*.parent = sys.xtalin */
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.parent = &ref_clk,
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| 551 | 558 |
}; |
| 552 | 559 |
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| 553 | 560 |
static struct clk wdt1_sys_clk = {
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| ... | ... | |
| 600 | 607 |
static struct clk core_clk = {
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| 601 | 608 |
.name = "core_clk", |
| 602 | 609 |
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 603 |
.parent = &dpll_ck,
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.parent = &dpll_x2_ck, /* Switchable between dpll_ck and clk32k */
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| 604 | 611 |
}; |
| 605 | 612 |
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| 606 | 613 |
static struct clk l3_clk = {
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| ... | ... | |
| 1009 | 1016 |
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| 1010 | 1017 |
/* OMAP 2 */ |
| 1011 | 1018 |
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&ref_clk, |
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| 1012 | 1020 |
&apll_96m, |
| 1013 | 1021 |
&apll_54m, |
| 1014 | 1022 |
&sys_clk, |
Also available in: Unified diff