Revision 522777bb
b/dyngen-exec.h | ||
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89 | 89 |
#undef NULL |
90 | 90 |
#define NULL 0 |
91 | 91 |
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92 |
#ifdef __i386__
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92 |
#if defined(__i386__)
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93 | 93 |
#define AREG0 "ebp" |
94 | 94 |
#define AREG1 "ebx" |
95 | 95 |
#define AREG2 "esi" |
96 | 96 |
#define AREG3 "edi" |
97 |
#endif |
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98 |
#ifdef __x86_64__ |
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#elif defined(__x86_64__) |
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99 | 98 |
#define AREG0 "r14" |
100 | 99 |
#define AREG1 "r15" |
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#define AREG2 "r12" |
102 | 101 |
#define AREG3 "r13" |
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//#define AREG4 "rbp" |
104 | 103 |
//#define AREG5 "rbx" |
105 |
#endif |
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#ifdef __powerpc__ |
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#elif defined(__powerpc__) |
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107 | 105 |
#define AREG0 "r27" |
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#define AREG1 "r24" |
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#define AREG2 "r25" |
... | ... | |
121 | 119 |
#endif |
122 | 120 |
#define USE_INT_TO_FLOAT_HELPERS |
123 | 121 |
#define BUGGY_GCC_DIV64 |
124 |
#endif |
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#ifdef __arm__ |
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#elif defined(__arm__) |
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126 | 123 |
#define AREG0 "r7" |
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#define AREG1 "r4" |
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#define AREG2 "r5" |
129 | 126 |
#define AREG3 "r6" |
130 |
#endif |
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#ifdef __mips__ |
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#elif defined(__mips__) |
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132 | 128 |
#define AREG0 "fp" |
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#define AREG1 "s0" |
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#define AREG2 "s1" |
... | ... | |
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#define AREG6 "s5" |
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#define AREG7 "s6" |
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#define AREG8 "s7" |
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#endif |
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#ifdef __sparc__ |
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#elif defined(__sparc__) |
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143 | 138 |
#ifdef HOST_SOLARIS |
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#define AREG0 "g2" |
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#define AREG1 "g3" |
... | ... | |
168 | 163 |
#endif |
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#endif |
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#define USE_FP_CONVERT |
171 |
#endif |
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#ifdef __s390__ |
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#elif defined(__s390__) |
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#define AREG0 "r10" |
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#define AREG1 "r7" |
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#define AREG2 "r8" |
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#define AREG3 "r9" |
177 |
#endif |
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#ifdef __alpha__ |
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#elif defined(__alpha__) |
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/* Note $15 is the frame pointer, so anything in op-i386.c that would |
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require a frame pointer, like alloca, would probably loose. */ |
181 | 174 |
#define AREG0 "$15" |
... | ... | |
185 | 178 |
#define AREG4 "$12" |
186 | 179 |
#define AREG5 "$13" |
187 | 180 |
#define AREG6 "$14" |
188 |
#endif |
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#ifdef __mc68000 |
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#elif defined(__mc68000) |
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#define AREG0 "%a5" |
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#define AREG1 "%a4" |
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#define AREG2 "%d7" |
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#define AREG3 "%d6" |
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#define AREG4 "%d5" |
195 |
#endif |
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#ifdef __ia64__ |
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#elif defined(__ia64__) |
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#define AREG0 "r7" |
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#define AREG1 "r4" |
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#define AREG2 "r5" |
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#define AREG3 "r6" |
192 |
#else |
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#error unsupported CPU |
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#endif |
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/* force GCC to generate only one epilog at the end of the function */ |
... | ... | |
250 | 243 |
#define ASM_NAME(x) #x |
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#endif |
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#ifdef __i386__
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#if defined(__i386__)
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#define EXIT_TB() asm volatile ("ret") |
255 | 248 |
#define GOTO_LABEL_PARAM(n) asm volatile ("jmp " ASM_NAME(__op_gen_label) #n) |
256 |
#endif |
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#ifdef __x86_64__ |
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#elif defined(__x86_64__) |
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#define EXIT_TB() asm volatile ("ret") |
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#define GOTO_LABEL_PARAM(n) asm volatile ("jmp " ASM_NAME(__op_gen_label) #n) |
260 |
#endif |
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#ifdef __powerpc__ |
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#elif defined(__powerpc__) |
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262 | 253 |
#define EXIT_TB() asm volatile ("blr") |
263 | 254 |
#define GOTO_LABEL_PARAM(n) asm volatile ("b " ASM_NAME(__op_gen_label) #n) |
264 |
#endif |
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#ifdef __s390__ |
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#elif defined(__s390__) |
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#define EXIT_TB() asm volatile ("br %r14") |
267 | 257 |
#define GOTO_LABEL_PARAM(n) asm volatile ("b " ASM_NAME(__op_gen_label) #n) |
268 |
#endif |
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#ifdef __alpha__ |
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#elif defined(__alpha__) |
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#define EXIT_TB() asm volatile ("ret") |
271 |
#endif |
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#ifdef __ia64__ |
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#elif defined(__ia64__) |
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#define EXIT_TB() asm volatile ("br.ret.sptk.many b0;;") |
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#define GOTO_LABEL_PARAM(n) asm volatile ("br.sptk.many " \ |
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ASM_NAME(__op_gen_label) #n) |
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#endif |
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#ifdef __sparc__ |
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#elif defined(__sparc__) |
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#define EXIT_TB() asm volatile ("jmpl %i0 + 8, %g0; nop") |
279 | 266 |
#define GOTO_LABEL_PARAM(n) asm volatile ("ba " ASM_NAME(__op_gen_label) #n ";nop") |
280 |
#endif |
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#ifdef __arm__ |
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#elif defined(__arm__) |
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282 | 268 |
#define EXIT_TB() asm volatile ("b exec_loop") |
283 | 269 |
#define GOTO_LABEL_PARAM(n) asm volatile ("b " ASM_NAME(__op_gen_label) #n) |
284 |
#endif |
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#ifdef __mc68000 |
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#elif defined(__mc68000) |
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#define EXIT_TB() asm volatile ("rts") |
287 |
#endif |
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#ifdef __mips__ |
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#elif defined(__mips__) |
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289 | 273 |
#define EXIT_TB() asm volatile ("jr $ra") |
290 | 274 |
#define GOTO_LABEL_PARAM(n) asm volatile (".set noat; la $1, " ASM_NAME(__op_gen_label) #n "; jr $1; .set at") |
275 |
#else |
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#error unsupported CPU |
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#endif |
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293 | 279 |
#endif /* !defined(__DYNGEN_EXEC_H__) */ |
b/dyngen.h | ||
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28 | 28 |
#endif |
29 | 29 |
int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3; |
30 | 30 |
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#ifdef __i386__
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#if defined(__i386__) || defined(__x86_64__) || defined(__s390__)
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
33 | 33 |
{ |
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} |
35 |
#endif |
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#ifdef __x86_64__ |
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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} |
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#endif |
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#ifdef __s390__ |
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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} |
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#endif |
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#ifdef __ia64__ |
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#elif defined(__ia64__) |
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50 | 36 |
static inline void flush_icache_range(unsigned long start, unsigned long stop) |
51 | 37 |
{ |
52 | 38 |
while (start < stop) { |
... | ... | |
55 | 41 |
} |
56 | 42 |
asm volatile (";;sync.i;;srlz.i;;"); |
57 | 43 |
} |
58 |
#endif |
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#ifdef __powerpc__ |
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#elif defined(__powerpc__) |
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61 | 45 |
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62 | 46 |
#define MIN_CACHE_LINE_SIZE 8 /* conservative value */ |
63 | 47 |
|
... | ... | |
78 | 62 |
asm volatile ("sync" : : : "memory"); |
79 | 63 |
asm volatile ("isync" : : : "memory"); |
80 | 64 |
} |
81 |
#endif |
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82 |
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#ifdef __alpha__ |
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#elif defined(__alpha__) |
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84 | 66 |
static inline void flush_icache_range(unsigned long start, unsigned long stop) |
85 | 67 |
{ |
86 | 68 |
asm ("imb"); |
87 | 69 |
} |
88 |
#endif |
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89 |
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#ifdef __sparc__ |
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#elif defined(__sparc__) |
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92 | 71 |
static void inline flush_icache_range(unsigned long start, unsigned long stop) |
93 | 72 |
{ |
94 | 73 |
unsigned long p; |
... | ... | |
99 | 78 |
for (; p < stop; p += 8) |
100 | 79 |
__asm__ __volatile__("flush\t%0" : : "r" (p)); |
101 | 80 |
} |
102 |
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#endif |
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#ifdef __arm__ |
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81 |
#elif defined(__arm__) |
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106 | 82 |
static inline void flush_icache_range(unsigned long start, unsigned long stop) |
107 | 83 |
{ |
108 | 84 |
register unsigned long _beg __asm ("a1") = start; |
... | ... | |
110 | 86 |
register unsigned long _flg __asm ("a3") = 0; |
111 | 87 |
__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); |
112 | 88 |
} |
113 |
#endif
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89 |
#elif defined(__mc68000)
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114 | 90 |
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#ifdef __mc68000 |
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#include <asm/cachectl.h> |
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# include <asm/cachectl.h> |
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117 | 92 |
static inline void flush_icache_range(unsigned long start, unsigned long stop) |
118 | 93 |
{ |
119 | 94 |
cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16); |
120 | 95 |
} |
96 |
#elif defined(__mips__) |
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#include <sys/cachectl.h> |
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static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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{ |
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_flush_cache ((void *)start, stop - start, BCACHE); |
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102 |
} |
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103 |
#else |
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104 |
#error unsupported CPU |
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121 | 105 |
#endif |
122 | 106 |
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123 | 107 |
#ifdef __alpha__ |
... | ... | |
248 | 232 |
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249 | 233 |
#ifdef __ia64 |
250 | 234 |
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251 |
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252 | 235 |
/* Patch instruction with "val" where "mask" has 1 bits. */ |
253 | 236 |
static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val) |
254 | 237 |
{ |
... | ... | |
463 | 446 |
} |
464 | 447 |
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465 | 448 |
#endif |
466 |
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467 |
#ifdef __mips__ |
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468 |
#include <sys/cachectl.h> |
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469 |
static inline void flush_icache_range(unsigned long start, unsigned long stop) |
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470 |
{ |
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471 |
_flush_cache ((void *)start, stop - start, BCACHE); |
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472 |
} |
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473 |
#endif |
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