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1 | c3d2689d | balrog | /*
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2 | c3d2689d | balrog | * OMAP clocks.
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3 | c3d2689d | balrog | *
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4 | c3d2689d | balrog | * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
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5 | c3d2689d | balrog | *
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6 | c3d2689d | balrog | * Clocks data comes in part from arch/arm/mach-omap1/clock.h in Linux.
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7 | c3d2689d | balrog | *
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8 | c3d2689d | balrog | * This program is free software; you can redistribute it and/or
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9 | c3d2689d | balrog | * modify it under the terms of the GNU General Public License as
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10 | c3d2689d | balrog | * published by the Free Software Foundation; either version 2 of
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11 | c3d2689d | balrog | * the License, or (at your option) any later version.
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12 | c3d2689d | balrog | *
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13 | c3d2689d | balrog | * This program is distributed in the hope that it will be useful,
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14 | c3d2689d | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 | c3d2689d | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 | c3d2689d | balrog | * GNU General Public License for more details.
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17 | c3d2689d | balrog | *
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18 | c3d2689d | balrog | * You should have received a copy of the GNU General Public License
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19 | c3d2689d | balrog | * along with this program; if not, write to the Free Software
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20 | c3d2689d | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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21 | c3d2689d | balrog | * MA 02111-1307 USA
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22 | c3d2689d | balrog | */
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23 | 87ecb68b | pbrook | #include "hw.h" |
24 | 87ecb68b | pbrook | #include "omap.h" |
25 | c3d2689d | balrog | |
26 | c3d2689d | balrog | struct clk {
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27 | c3d2689d | balrog | const char *name; |
28 | c3d2689d | balrog | const char *alias; |
29 | c3d2689d | balrog | struct clk *parent;
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30 | c3d2689d | balrog | struct clk *child1;
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31 | c3d2689d | balrog | struct clk *sibling;
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32 | c3d2689d | balrog | #define ALWAYS_ENABLED (1 << 0) |
33 | c3d2689d | balrog | #define CLOCK_IN_OMAP310 (1 << 10) |
34 | c3d2689d | balrog | #define CLOCK_IN_OMAP730 (1 << 11) |
35 | c3d2689d | balrog | #define CLOCK_IN_OMAP1510 (1 << 12) |
36 | c3d2689d | balrog | #define CLOCK_IN_OMAP16XX (1 << 13) |
37 | c3d2689d | balrog | uint32_t flags; |
38 | c3d2689d | balrog | int id;
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39 | c3d2689d | balrog | |
40 | c3d2689d | balrog | int running; /* Is currently ticking */ |
41 | c3d2689d | balrog | int enabled; /* Is enabled, regardless of its input clk */ |
42 | c3d2689d | balrog | unsigned long rate; /* Current rate (if .running) */ |
43 | c3d2689d | balrog | unsigned int divisor; /* Rate relative to input (if .enabled) */ |
44 | c3d2689d | balrog | unsigned int multiplier; /* Rate relative to input (if .enabled) */ |
45 | c3d2689d | balrog | qemu_irq users[16]; /* Who to notify on change */ |
46 | c3d2689d | balrog | int usecount; /* Automatically idle when unused */ |
47 | c3d2689d | balrog | }; |
48 | c3d2689d | balrog | |
49 | c3d2689d | balrog | static struct clk xtal_osc12m = { |
50 | c3d2689d | balrog | .name = "xtal_osc_12m",
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51 | c3d2689d | balrog | .rate = 12000000,
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52 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
53 | c3d2689d | balrog | }; |
54 | c3d2689d | balrog | |
55 | c3d2689d | balrog | static struct clk xtal_osc32k = { |
56 | c3d2689d | balrog | .name = "xtal_osc_32k",
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57 | c3d2689d | balrog | .rate = 32768,
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58 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
59 | c3d2689d | balrog | }; |
60 | c3d2689d | balrog | |
61 | c3d2689d | balrog | static struct clk ck_ref = { |
62 | c3d2689d | balrog | .name = "ck_ref",
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63 | c3d2689d | balrog | .alias = "clkin",
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64 | c3d2689d | balrog | .parent = &xtal_osc12m, |
65 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
66 | c3d2689d | balrog | ALWAYS_ENABLED, |
67 | c3d2689d | balrog | }; |
68 | c3d2689d | balrog | |
69 | c3d2689d | balrog | /* If a dpll is disabled it becomes a bypass, child clocks don't stop */
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70 | c3d2689d | balrog | static struct clk dpll1 = { |
71 | c3d2689d | balrog | .name = "dpll1",
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72 | c3d2689d | balrog | .parent = &ck_ref, |
73 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
74 | c3d2689d | balrog | ALWAYS_ENABLED, |
75 | c3d2689d | balrog | }; |
76 | c3d2689d | balrog | |
77 | c3d2689d | balrog | static struct clk dpll2 = { |
78 | c3d2689d | balrog | .name = "dpll2",
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79 | c3d2689d | balrog | .parent = &ck_ref, |
80 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
81 | c3d2689d | balrog | }; |
82 | c3d2689d | balrog | |
83 | c3d2689d | balrog | static struct clk dpll3 = { |
84 | c3d2689d | balrog | .name = "dpll3",
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85 | c3d2689d | balrog | .parent = &ck_ref, |
86 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
87 | c3d2689d | balrog | }; |
88 | c3d2689d | balrog | |
89 | c3d2689d | balrog | static struct clk dpll4 = { |
90 | c3d2689d | balrog | .name = "dpll4",
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91 | c3d2689d | balrog | .parent = &ck_ref, |
92 | c3d2689d | balrog | .multiplier = 4,
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93 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
94 | c3d2689d | balrog | }; |
95 | c3d2689d | balrog | |
96 | c3d2689d | balrog | static struct clk apll = { |
97 | c3d2689d | balrog | .name = "apll",
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98 | c3d2689d | balrog | .parent = &ck_ref, |
99 | c3d2689d | balrog | .multiplier = 48,
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100 | c3d2689d | balrog | .divisor = 12,
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101 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
102 | c3d2689d | balrog | }; |
103 | c3d2689d | balrog | |
104 | c3d2689d | balrog | static struct clk ck_48m = { |
105 | c3d2689d | balrog | .name = "ck_48m",
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106 | c3d2689d | balrog | .parent = &dpll4, /* either dpll4 or apll */
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107 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
108 | c3d2689d | balrog | }; |
109 | c3d2689d | balrog | |
110 | c3d2689d | balrog | static struct clk ck_dpll1out = { |
111 | c3d2689d | balrog | .name = "ck_dpll1out",
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112 | c3d2689d | balrog | .parent = &dpll1, |
113 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
114 | c3d2689d | balrog | }; |
115 | c3d2689d | balrog | |
116 | c3d2689d | balrog | static struct clk sossi_ck = { |
117 | c3d2689d | balrog | .name = "ck_sossi",
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118 | c3d2689d | balrog | .parent = &ck_dpll1out, |
119 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
120 | c3d2689d | balrog | }; |
121 | c3d2689d | balrog | |
122 | c3d2689d | balrog | static struct clk clkm1 = { |
123 | c3d2689d | balrog | .name = "clkm1",
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124 | c3d2689d | balrog | .alias = "ck_gen1",
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125 | c3d2689d | balrog | .parent = &dpll1, |
126 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
127 | c3d2689d | balrog | ALWAYS_ENABLED, |
128 | c3d2689d | balrog | }; |
129 | c3d2689d | balrog | |
130 | c3d2689d | balrog | static struct clk clkm2 = { |
131 | c3d2689d | balrog | .name = "clkm2",
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132 | c3d2689d | balrog | .alias = "ck_gen2",
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133 | c3d2689d | balrog | .parent = &dpll1, |
134 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
135 | c3d2689d | balrog | ALWAYS_ENABLED, |
136 | c3d2689d | balrog | }; |
137 | c3d2689d | balrog | |
138 | c3d2689d | balrog | static struct clk clkm3 = { |
139 | c3d2689d | balrog | .name = "clkm3",
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140 | c3d2689d | balrog | .alias = "ck_gen3",
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141 | c3d2689d | balrog | .parent = &dpll1, /* either dpll1 or ck_ref */
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142 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
143 | c3d2689d | balrog | ALWAYS_ENABLED, |
144 | c3d2689d | balrog | }; |
145 | c3d2689d | balrog | |
146 | c3d2689d | balrog | static struct clk arm_ck = { |
147 | c3d2689d | balrog | .name = "arm_ck",
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148 | c3d2689d | balrog | .alias = "mpu_ck",
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149 | c3d2689d | balrog | .parent = &clkm1, |
150 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
151 | c3d2689d | balrog | ALWAYS_ENABLED, |
152 | c3d2689d | balrog | }; |
153 | c3d2689d | balrog | |
154 | c3d2689d | balrog | static struct clk armper_ck = { |
155 | c3d2689d | balrog | .name = "armper_ck",
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156 | c3d2689d | balrog | .alias = "mpuper_ck",
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157 | c3d2689d | balrog | .parent = &clkm1, |
158 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
159 | c3d2689d | balrog | }; |
160 | c3d2689d | balrog | |
161 | c3d2689d | balrog | static struct clk arm_gpio_ck = { |
162 | c3d2689d | balrog | .name = "arm_gpio_ck",
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163 | c3d2689d | balrog | .alias = "mpu_gpio_ck",
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164 | c3d2689d | balrog | .parent = &clkm1, |
165 | c3d2689d | balrog | .divisor = 1,
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166 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
167 | c3d2689d | balrog | }; |
168 | c3d2689d | balrog | |
169 | c3d2689d | balrog | static struct clk armxor_ck = { |
170 | c3d2689d | balrog | .name = "armxor_ck",
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171 | c3d2689d | balrog | .alias = "mpuxor_ck",
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172 | c3d2689d | balrog | .parent = &ck_ref, |
173 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
174 | c3d2689d | balrog | }; |
175 | c3d2689d | balrog | |
176 | c3d2689d | balrog | static struct clk armtim_ck = { |
177 | c3d2689d | balrog | .name = "armtim_ck",
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178 | c3d2689d | balrog | .alias = "mputim_ck",
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179 | c3d2689d | balrog | .parent = &ck_ref, /* either CLKIN or DPLL1 */
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180 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
181 | c3d2689d | balrog | }; |
182 | c3d2689d | balrog | |
183 | c3d2689d | balrog | static struct clk armwdt_ck = { |
184 | c3d2689d | balrog | .name = "armwdt_ck",
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185 | c3d2689d | balrog | .alias = "mpuwd_ck",
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186 | c3d2689d | balrog | .parent = &clkm1, |
187 | c3d2689d | balrog | .divisor = 14,
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188 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
189 | c3d2689d | balrog | ALWAYS_ENABLED, |
190 | c3d2689d | balrog | }; |
191 | c3d2689d | balrog | |
192 | c3d2689d | balrog | static struct clk arminth_ck16xx = { |
193 | c3d2689d | balrog | .name = "arminth_ck",
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194 | c3d2689d | balrog | .parent = &arm_ck, |
195 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
196 | c3d2689d | balrog | /* Note: On 16xx the frequency can be divided by 2 by programming
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197 | c3d2689d | balrog | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
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198 | c3d2689d | balrog | *
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199 | c3d2689d | balrog | * 1510 version is in TC clocks.
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200 | c3d2689d | balrog | */
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201 | c3d2689d | balrog | }; |
202 | c3d2689d | balrog | |
203 | c3d2689d | balrog | static struct clk dsp_ck = { |
204 | c3d2689d | balrog | .name = "dsp_ck",
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205 | c3d2689d | balrog | .parent = &clkm2, |
206 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
207 | c3d2689d | balrog | }; |
208 | c3d2689d | balrog | |
209 | c3d2689d | balrog | static struct clk dspmmu_ck = { |
210 | c3d2689d | balrog | .name = "dspmmu_ck",
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211 | c3d2689d | balrog | .parent = &clkm2, |
212 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
213 | c3d2689d | balrog | ALWAYS_ENABLED, |
214 | c3d2689d | balrog | }; |
215 | c3d2689d | balrog | |
216 | c3d2689d | balrog | static struct clk dspper_ck = { |
217 | c3d2689d | balrog | .name = "dspper_ck",
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218 | c3d2689d | balrog | .parent = &clkm2, |
219 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
220 | c3d2689d | balrog | }; |
221 | c3d2689d | balrog | |
222 | c3d2689d | balrog | static struct clk dspxor_ck = { |
223 | c3d2689d | balrog | .name = "dspxor_ck",
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224 | c3d2689d | balrog | .parent = &ck_ref, |
225 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
226 | c3d2689d | balrog | }; |
227 | c3d2689d | balrog | |
228 | c3d2689d | balrog | static struct clk dsptim_ck = { |
229 | c3d2689d | balrog | .name = "dsptim_ck",
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230 | c3d2689d | balrog | .parent = &ck_ref, |
231 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
232 | c3d2689d | balrog | }; |
233 | c3d2689d | balrog | |
234 | c3d2689d | balrog | static struct clk tc_ck = { |
235 | c3d2689d | balrog | .name = "tc_ck",
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236 | c3d2689d | balrog | .parent = &clkm3, |
237 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
238 | c3d2689d | balrog | CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 | |
239 | c3d2689d | balrog | ALWAYS_ENABLED, |
240 | c3d2689d | balrog | }; |
241 | c3d2689d | balrog | |
242 | c3d2689d | balrog | static struct clk arminth_ck15xx = { |
243 | c3d2689d | balrog | .name = "arminth_ck",
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244 | c3d2689d | balrog | .parent = &tc_ck, |
245 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
246 | c3d2689d | balrog | /* Note: On 1510 the frequency follows TC_CK
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247 | c3d2689d | balrog | *
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248 | c3d2689d | balrog | * 16xx version is in MPU clocks.
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249 | c3d2689d | balrog | */
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250 | c3d2689d | balrog | }; |
251 | c3d2689d | balrog | |
252 | c3d2689d | balrog | static struct clk tipb_ck = { |
253 | c3d2689d | balrog | /* No-idle controlled by "tc_ck" */
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254 | c3d2689d | balrog | .name = "tipb_ck",
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255 | c3d2689d | balrog | .parent = &tc_ck, |
256 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
257 | c3d2689d | balrog | }; |
258 | c3d2689d | balrog | |
259 | c3d2689d | balrog | static struct clk l3_ocpi_ck = { |
260 | c3d2689d | balrog | /* No-idle controlled by "tc_ck" */
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261 | c3d2689d | balrog | .name = "l3_ocpi_ck",
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262 | c3d2689d | balrog | .parent = &tc_ck, |
263 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
264 | c3d2689d | balrog | }; |
265 | c3d2689d | balrog | |
266 | c3d2689d | balrog | static struct clk tc1_ck = { |
267 | c3d2689d | balrog | .name = "tc1_ck",
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268 | c3d2689d | balrog | .parent = &tc_ck, |
269 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
270 | c3d2689d | balrog | }; |
271 | c3d2689d | balrog | |
272 | c3d2689d | balrog | static struct clk tc2_ck = { |
273 | c3d2689d | balrog | .name = "tc2_ck",
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274 | c3d2689d | balrog | .parent = &tc_ck, |
275 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
276 | c3d2689d | balrog | }; |
277 | c3d2689d | balrog | |
278 | c3d2689d | balrog | static struct clk dma_ck = { |
279 | c3d2689d | balrog | /* No-idle controlled by "tc_ck" */
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280 | c3d2689d | balrog | .name = "dma_ck",
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281 | c3d2689d | balrog | .parent = &tc_ck, |
282 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
283 | c3d2689d | balrog | ALWAYS_ENABLED, |
284 | c3d2689d | balrog | }; |
285 | c3d2689d | balrog | |
286 | c3d2689d | balrog | static struct clk dma_lcdfree_ck = { |
287 | c3d2689d | balrog | .name = "dma_lcdfree_ck",
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288 | c3d2689d | balrog | .parent = &tc_ck, |
289 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
290 | c3d2689d | balrog | }; |
291 | c3d2689d | balrog | |
292 | c3d2689d | balrog | static struct clk api_ck = { |
293 | c3d2689d | balrog | .name = "api_ck",
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294 | c3d2689d | balrog | .alias = "mpui_ck",
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295 | c3d2689d | balrog | .parent = &tc_ck, |
296 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
297 | c3d2689d | balrog | }; |
298 | c3d2689d | balrog | |
299 | c3d2689d | balrog | static struct clk lb_ck = { |
300 | c3d2689d | balrog | .name = "lb_ck",
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301 | c3d2689d | balrog | .parent = &tc_ck, |
302 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
303 | c3d2689d | balrog | }; |
304 | c3d2689d | balrog | |
305 | c3d2689d | balrog | static struct clk lbfree_ck = { |
306 | c3d2689d | balrog | .name = "lbfree_ck",
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307 | c3d2689d | balrog | .parent = &tc_ck, |
308 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
309 | c3d2689d | balrog | }; |
310 | c3d2689d | balrog | |
311 | d8f699cb | balrog | static struct clk hsab_ck = { |
312 | d8f699cb | balrog | .name = "hsab_ck",
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313 | d8f699cb | balrog | .parent = &tc_ck, |
314 | d8f699cb | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
315 | d8f699cb | balrog | }; |
316 | d8f699cb | balrog | |
317 | c3d2689d | balrog | static struct clk rhea1_ck = { |
318 | c3d2689d | balrog | .name = "rhea1_ck",
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319 | c3d2689d | balrog | .parent = &tc_ck, |
320 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
321 | c3d2689d | balrog | }; |
322 | c3d2689d | balrog | |
323 | c3d2689d | balrog | static struct clk rhea2_ck = { |
324 | c3d2689d | balrog | .name = "rhea2_ck",
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325 | c3d2689d | balrog | .parent = &tc_ck, |
326 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
327 | c3d2689d | balrog | }; |
328 | c3d2689d | balrog | |
329 | c3d2689d | balrog | static struct clk lcd_ck_16xx = { |
330 | c3d2689d | balrog | .name = "lcd_ck",
|
331 | c3d2689d | balrog | .parent = &clkm3, |
332 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730, |
333 | c3d2689d | balrog | }; |
334 | c3d2689d | balrog | |
335 | c3d2689d | balrog | static struct clk lcd_ck_1510 = { |
336 | c3d2689d | balrog | .name = "lcd_ck",
|
337 | c3d2689d | balrog | .parent = &clkm3, |
338 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
339 | c3d2689d | balrog | }; |
340 | c3d2689d | balrog | |
341 | c3d2689d | balrog | static struct clk uart1_1510 = { |
342 | c3d2689d | balrog | .name = "uart1_ck",
|
343 | c3d2689d | balrog | /* Direct from ULPD, no real parent */
|
344 | c3d2689d | balrog | .parent = &armper_ck, /* either armper_ck or dpll4 */
|
345 | c3d2689d | balrog | .rate = 12000000,
|
346 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
347 | c3d2689d | balrog | }; |
348 | c3d2689d | balrog | |
349 | c3d2689d | balrog | static struct clk uart1_16xx = { |
350 | c3d2689d | balrog | .name = "uart1_ck",
|
351 | c3d2689d | balrog | /* Direct from ULPD, no real parent */
|
352 | c3d2689d | balrog | .parent = &armper_ck, |
353 | c3d2689d | balrog | .rate = 48000000,
|
354 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
355 | c3d2689d | balrog | }; |
356 | c3d2689d | balrog | |
357 | c3d2689d | balrog | static struct clk uart2_ck = { |
358 | c3d2689d | balrog | .name = "uart2_ck",
|
359 | c3d2689d | balrog | /* Direct from ULPD, no real parent */
|
360 | c3d2689d | balrog | .parent = &armper_ck, /* either armper_ck or dpll4 */
|
361 | c3d2689d | balrog | .rate = 12000000,
|
362 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
363 | c3d2689d | balrog | ALWAYS_ENABLED, |
364 | c3d2689d | balrog | }; |
365 | c3d2689d | balrog | |
366 | c3d2689d | balrog | static struct clk uart3_1510 = { |
367 | c3d2689d | balrog | .name = "uart3_ck",
|
368 | c3d2689d | balrog | /* Direct from ULPD, no real parent */
|
369 | d8f699cb | balrog | .parent = &armper_ck, /* either armper_ck or dpll4 */
|
370 | c3d2689d | balrog | .rate = 12000000,
|
371 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
372 | c3d2689d | balrog | }; |
373 | c3d2689d | balrog | |
374 | c3d2689d | balrog | static struct clk uart3_16xx = { |
375 | c3d2689d | balrog | .name = "uart3_ck",
|
376 | c3d2689d | balrog | /* Direct from ULPD, no real parent */
|
377 | c3d2689d | balrog | .parent = &armper_ck, |
378 | c3d2689d | balrog | .rate = 48000000,
|
379 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
380 | c3d2689d | balrog | }; |
381 | c3d2689d | balrog | |
382 | c3d2689d | balrog | static struct clk usb_clk0 = { /* 6 MHz output on W4_USB_CLK0 */ |
383 | c3d2689d | balrog | .name = "usb_clk0",
|
384 | c3d2689d | balrog | .alias = "usb.clko",
|
385 | c3d2689d | balrog | /* Direct from ULPD, no parent */
|
386 | c3d2689d | balrog | .rate = 6000000,
|
387 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
388 | c3d2689d | balrog | }; |
389 | c3d2689d | balrog | |
390 | c3d2689d | balrog | static struct clk usb_hhc_ck1510 = { |
391 | c3d2689d | balrog | .name = "usb_hhc_ck",
|
392 | c3d2689d | balrog | /* Direct from ULPD, no parent */
|
393 | c3d2689d | balrog | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ |
394 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
395 | c3d2689d | balrog | }; |
396 | c3d2689d | balrog | |
397 | c3d2689d | balrog | static struct clk usb_hhc_ck16xx = { |
398 | c3d2689d | balrog | .name = "usb_hhc_ck",
|
399 | c3d2689d | balrog | /* Direct from ULPD, no parent */
|
400 | c3d2689d | balrog | .rate = 48000000,
|
401 | c3d2689d | balrog | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
|
402 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
403 | c3d2689d | balrog | }; |
404 | c3d2689d | balrog | |
405 | d8f699cb | balrog | static struct clk usb_w2fc_mclk = { |
406 | d8f699cb | balrog | .name = "usb_w2fc_mclk",
|
407 | d8f699cb | balrog | .alias = "usb_w2fc_ck",
|
408 | d8f699cb | balrog | .parent = &ck_48m, |
409 | c3d2689d | balrog | .rate = 48000000,
|
410 | d8f699cb | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
411 | c3d2689d | balrog | }; |
412 | c3d2689d | balrog | |
413 | c3d2689d | balrog | static struct clk mclk_1510 = { |
414 | c3d2689d | balrog | .name = "mclk",
|
415 | c3d2689d | balrog | /* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
416 | c3d2689d | balrog | .rate = 12000000,
|
417 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510, |
418 | c3d2689d | balrog | }; |
419 | c3d2689d | balrog | |
420 | c3d2689d | balrog | static struct clk bclk_310 = { |
421 | c3d2689d | balrog | .name = "bt_mclk_out", /* Alias midi_mclk_out? */ |
422 | c3d2689d | balrog | .parent = &armper_ck, |
423 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310, |
424 | c3d2689d | balrog | }; |
425 | c3d2689d | balrog | |
426 | c3d2689d | balrog | static struct clk mclk_310 = { |
427 | c3d2689d | balrog | .name = "com_mclk_out",
|
428 | c3d2689d | balrog | .parent = &armper_ck, |
429 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310, |
430 | c3d2689d | balrog | }; |
431 | c3d2689d | balrog | |
432 | c3d2689d | balrog | static struct clk mclk_16xx = { |
433 | c3d2689d | balrog | .name = "mclk",
|
434 | c3d2689d | balrog | /* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
435 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
436 | c3d2689d | balrog | }; |
437 | c3d2689d | balrog | |
438 | c3d2689d | balrog | static struct clk bclk_1510 = { |
439 | c3d2689d | balrog | .name = "bclk",
|
440 | c3d2689d | balrog | /* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
441 | c3d2689d | balrog | .rate = 12000000,
|
442 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510, |
443 | c3d2689d | balrog | }; |
444 | c3d2689d | balrog | |
445 | c3d2689d | balrog | static struct clk bclk_16xx = { |
446 | c3d2689d | balrog | .name = "bclk",
|
447 | c3d2689d | balrog | /* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
448 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
449 | c3d2689d | balrog | }; |
450 | c3d2689d | balrog | |
451 | c3d2689d | balrog | static struct clk mmc1_ck = { |
452 | c3d2689d | balrog | .name = "mmc_ck",
|
453 | c3d2689d | balrog | .id = 1,
|
454 | c3d2689d | balrog | /* Functional clock is direct from ULPD, interface clock is ARMPER */
|
455 | c3d2689d | balrog | .parent = &armper_ck, /* either armper_ck or dpll4 */
|
456 | c3d2689d | balrog | .rate = 48000000,
|
457 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
458 | c3d2689d | balrog | }; |
459 | c3d2689d | balrog | |
460 | c3d2689d | balrog | static struct clk mmc2_ck = { |
461 | c3d2689d | balrog | .name = "mmc_ck",
|
462 | c3d2689d | balrog | .id = 2,
|
463 | c3d2689d | balrog | /* Functional clock is direct from ULPD, interface clock is ARMPER */
|
464 | c3d2689d | balrog | .parent = &armper_ck, |
465 | c3d2689d | balrog | .rate = 48000000,
|
466 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
467 | c3d2689d | balrog | }; |
468 | c3d2689d | balrog | |
469 | c3d2689d | balrog | static struct clk cam_mclk = { |
470 | c3d2689d | balrog | .name = "cam.mclk",
|
471 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
472 | c3d2689d | balrog | .rate = 12000000,
|
473 | c3d2689d | balrog | }; |
474 | c3d2689d | balrog | |
475 | c3d2689d | balrog | static struct clk cam_exclk = { |
476 | c3d2689d | balrog | .name = "cam.exclk",
|
477 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
478 | c3d2689d | balrog | /* Either 12M from cam.mclk or 48M from dpll4 */
|
479 | c3d2689d | balrog | .parent = &cam_mclk, |
480 | c3d2689d | balrog | }; |
481 | c3d2689d | balrog | |
482 | c3d2689d | balrog | static struct clk cam_lclk = { |
483 | c3d2689d | balrog | .name = "cam.lclk",
|
484 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
485 | c3d2689d | balrog | }; |
486 | c3d2689d | balrog | |
487 | c3d2689d | balrog | static struct clk i2c_fck = { |
488 | c3d2689d | balrog | .name = "i2c_fck",
|
489 | c3d2689d | balrog | .id = 1,
|
490 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
491 | c3d2689d | balrog | ALWAYS_ENABLED, |
492 | c3d2689d | balrog | .parent = &armxor_ck, |
493 | c3d2689d | balrog | }; |
494 | c3d2689d | balrog | |
495 | c3d2689d | balrog | static struct clk i2c_ick = { |
496 | c3d2689d | balrog | .name = "i2c_ick",
|
497 | c3d2689d | balrog | .id = 1,
|
498 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
499 | c3d2689d | balrog | .parent = &armper_ck, |
500 | c3d2689d | balrog | }; |
501 | c3d2689d | balrog | |
502 | c3d2689d | balrog | static struct clk clk32k = { |
503 | c3d2689d | balrog | .name = "clk32-kHz",
|
504 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
505 | c3d2689d | balrog | ALWAYS_ENABLED, |
506 | c3d2689d | balrog | .parent = &xtal_osc32k, |
507 | c3d2689d | balrog | }; |
508 | c3d2689d | balrog | |
509 | c3d2689d | balrog | static struct clk *onchip_clks[] = { |
510 | c3d2689d | balrog | /* non-ULPD clocks */
|
511 | c3d2689d | balrog | &xtal_osc12m, |
512 | c3d2689d | balrog | &xtal_osc32k, |
513 | c3d2689d | balrog | &ck_ref, |
514 | c3d2689d | balrog | &dpll1, |
515 | c3d2689d | balrog | &dpll2, |
516 | c3d2689d | balrog | &dpll3, |
517 | c3d2689d | balrog | &dpll4, |
518 | c3d2689d | balrog | &apll, |
519 | c3d2689d | balrog | &ck_48m, |
520 | c3d2689d | balrog | /* CK_GEN1 clocks */
|
521 | c3d2689d | balrog | &clkm1, |
522 | c3d2689d | balrog | &ck_dpll1out, |
523 | c3d2689d | balrog | &sossi_ck, |
524 | c3d2689d | balrog | &arm_ck, |
525 | c3d2689d | balrog | &armper_ck, |
526 | c3d2689d | balrog | &arm_gpio_ck, |
527 | c3d2689d | balrog | &armxor_ck, |
528 | c3d2689d | balrog | &armtim_ck, |
529 | c3d2689d | balrog | &armwdt_ck, |
530 | c3d2689d | balrog | &arminth_ck15xx, &arminth_ck16xx, |
531 | c3d2689d | balrog | /* CK_GEN2 clocks */
|
532 | c3d2689d | balrog | &clkm2, |
533 | c3d2689d | balrog | &dsp_ck, |
534 | c3d2689d | balrog | &dspmmu_ck, |
535 | c3d2689d | balrog | &dspper_ck, |
536 | c3d2689d | balrog | &dspxor_ck, |
537 | c3d2689d | balrog | &dsptim_ck, |
538 | c3d2689d | balrog | /* CK_GEN3 clocks */
|
539 | c3d2689d | balrog | &clkm3, |
540 | c3d2689d | balrog | &tc_ck, |
541 | c3d2689d | balrog | &tipb_ck, |
542 | c3d2689d | balrog | &l3_ocpi_ck, |
543 | c3d2689d | balrog | &tc1_ck, |
544 | c3d2689d | balrog | &tc2_ck, |
545 | c3d2689d | balrog | &dma_ck, |
546 | c3d2689d | balrog | &dma_lcdfree_ck, |
547 | c3d2689d | balrog | &api_ck, |
548 | c3d2689d | balrog | &lb_ck, |
549 | c3d2689d | balrog | &lbfree_ck, |
550 | d8f699cb | balrog | &hsab_ck, |
551 | c3d2689d | balrog | &rhea1_ck, |
552 | c3d2689d | balrog | &rhea2_ck, |
553 | c3d2689d | balrog | &lcd_ck_16xx, |
554 | c3d2689d | balrog | &lcd_ck_1510, |
555 | c3d2689d | balrog | /* ULPD clocks */
|
556 | c3d2689d | balrog | &uart1_1510, |
557 | c3d2689d | balrog | &uart1_16xx, |
558 | c3d2689d | balrog | &uart2_ck, |
559 | c3d2689d | balrog | &uart3_1510, |
560 | c3d2689d | balrog | &uart3_16xx, |
561 | c3d2689d | balrog | &usb_clk0, |
562 | c3d2689d | balrog | &usb_hhc_ck1510, &usb_hhc_ck16xx, |
563 | c3d2689d | balrog | &mclk_1510, &mclk_16xx, &mclk_310, |
564 | c3d2689d | balrog | &bclk_1510, &bclk_16xx, &bclk_310, |
565 | c3d2689d | balrog | &mmc1_ck, |
566 | c3d2689d | balrog | &mmc2_ck, |
567 | c3d2689d | balrog | &cam_mclk, |
568 | c3d2689d | balrog | &cam_exclk, |
569 | c3d2689d | balrog | &cam_lclk, |
570 | c3d2689d | balrog | &clk32k, |
571 | d8f699cb | balrog | &usb_w2fc_mclk, |
572 | c3d2689d | balrog | /* Virtual clocks */
|
573 | c3d2689d | balrog | &i2c_fck, |
574 | c3d2689d | balrog | &i2c_ick, |
575 | c3d2689d | balrog | 0
|
576 | c3d2689d | balrog | }; |
577 | c3d2689d | balrog | |
578 | c3d2689d | balrog | void omap_clk_adduser(struct clk *clk, qemu_irq user) |
579 | c3d2689d | balrog | { |
580 | c3d2689d | balrog | qemu_irq *i; |
581 | c3d2689d | balrog | |
582 | c3d2689d | balrog | for (i = clk->users; *i; i ++);
|
583 | c3d2689d | balrog | *i = user; |
584 | c3d2689d | balrog | } |
585 | c3d2689d | balrog | |
586 | c3d2689d | balrog | /* If a clock is allowed to idle, it is disabled automatically when
|
587 | c3d2689d | balrog | * all of clock domains using it are disabled. */
|
588 | c3d2689d | balrog | int omap_clk_is_idle(struct clk *clk) |
589 | c3d2689d | balrog | { |
590 | c3d2689d | balrog | struct clk *chld;
|
591 | c3d2689d | balrog | |
592 | c3d2689d | balrog | if (!clk->enabled && (!clk->usecount || !(clk->flags && ALWAYS_ENABLED)))
|
593 | c3d2689d | balrog | return 1; |
594 | c3d2689d | balrog | if (clk->usecount)
|
595 | c3d2689d | balrog | return 0; |
596 | c3d2689d | balrog | |
597 | c3d2689d | balrog | for (chld = clk->child1; chld; chld = chld->sibling)
|
598 | c3d2689d | balrog | if (!omap_clk_is_idle(chld))
|
599 | c3d2689d | balrog | return 0; |
600 | c3d2689d | balrog | return 1; |
601 | c3d2689d | balrog | } |
602 | c3d2689d | balrog | |
603 | c3d2689d | balrog | struct clk *omap_findclk(struct omap_mpu_state_s *mpu, const char *name) |
604 | c3d2689d | balrog | { |
605 | c3d2689d | balrog | struct clk *i;
|
606 | c3d2689d | balrog | |
607 | c3d2689d | balrog | for (i = mpu->clks; i->name; i ++)
|
608 | c3d2689d | balrog | if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name)))
|
609 | c3d2689d | balrog | return i;
|
610 | c3d2689d | balrog | cpu_abort(mpu->env, "%s: %s not found\n", __FUNCTION__, name);
|
611 | c3d2689d | balrog | } |
612 | c3d2689d | balrog | |
613 | c3d2689d | balrog | void omap_clk_get(struct clk *clk) |
614 | c3d2689d | balrog | { |
615 | c3d2689d | balrog | clk->usecount ++; |
616 | c3d2689d | balrog | } |
617 | c3d2689d | balrog | |
618 | c3d2689d | balrog | void omap_clk_put(struct clk *clk) |
619 | c3d2689d | balrog | { |
620 | c3d2689d | balrog | if (!(clk->usecount --))
|
621 | c3d2689d | balrog | cpu_abort(cpu_single_env, "%s: %s is not in use\n",
|
622 | c3d2689d | balrog | __FUNCTION__, clk->name); |
623 | c3d2689d | balrog | } |
624 | c3d2689d | balrog | |
625 | c3d2689d | balrog | static void omap_clk_update(struct clk *clk) |
626 | c3d2689d | balrog | { |
627 | c3d2689d | balrog | int parent, running;
|
628 | c3d2689d | balrog | qemu_irq *user; |
629 | c3d2689d | balrog | struct clk *i;
|
630 | c3d2689d | balrog | |
631 | c3d2689d | balrog | if (clk->parent)
|
632 | c3d2689d | balrog | parent = clk->parent->running; |
633 | c3d2689d | balrog | else
|
634 | c3d2689d | balrog | parent = 1;
|
635 | c3d2689d | balrog | |
636 | c3d2689d | balrog | running = parent && (clk->enabled || |
637 | c3d2689d | balrog | ((clk->flags & ALWAYS_ENABLED) && clk->usecount)); |
638 | c3d2689d | balrog | if (clk->running != running) {
|
639 | c3d2689d | balrog | clk->running = running; |
640 | c3d2689d | balrog | for (user = clk->users; *user; user ++)
|
641 | c3d2689d | balrog | qemu_set_irq(*user, running); |
642 | c3d2689d | balrog | for (i = clk->child1; i; i = i->sibling)
|
643 | c3d2689d | balrog | omap_clk_update(i); |
644 | c3d2689d | balrog | } |
645 | c3d2689d | balrog | } |
646 | c3d2689d | balrog | |
647 | c3d2689d | balrog | static void omap_clk_rate_update_full(struct clk *clk, unsigned long int rate, |
648 | c3d2689d | balrog | unsigned long int div, unsigned long int mult) |
649 | c3d2689d | balrog | { |
650 | c3d2689d | balrog | struct clk *i;
|
651 | c3d2689d | balrog | qemu_irq *user; |
652 | c3d2689d | balrog | |
653 | c3d2689d | balrog | clk->rate = muldiv64(rate, mult, div); |
654 | c3d2689d | balrog | if (clk->running)
|
655 | c3d2689d | balrog | for (user = clk->users; *user; user ++)
|
656 | c3d2689d | balrog | qemu_irq_raise(*user); |
657 | c3d2689d | balrog | for (i = clk->child1; i; i = i->sibling)
|
658 | c3d2689d | balrog | omap_clk_rate_update_full(i, rate, |
659 | c3d2689d | balrog | div * i->divisor, mult * i->multiplier); |
660 | c3d2689d | balrog | } |
661 | c3d2689d | balrog | |
662 | c3d2689d | balrog | static void omap_clk_rate_update(struct clk *clk) |
663 | c3d2689d | balrog | { |
664 | c3d2689d | balrog | struct clk *i;
|
665 | c3d2689d | balrog | unsigned long int div, mult = div = 1; |
666 | c3d2689d | balrog | |
667 | c3d2689d | balrog | for (i = clk; i->parent; i = i->parent) {
|
668 | c3d2689d | balrog | div *= i->divisor; |
669 | c3d2689d | balrog | mult *= i->multiplier; |
670 | c3d2689d | balrog | } |
671 | c3d2689d | balrog | |
672 | c3d2689d | balrog | omap_clk_rate_update_full(clk, i->rate, div, mult); |
673 | c3d2689d | balrog | } |
674 | c3d2689d | balrog | |
675 | c3d2689d | balrog | void omap_clk_reparent(struct clk *clk, struct clk *parent) |
676 | c3d2689d | balrog | { |
677 | c3d2689d | balrog | struct clk **p;
|
678 | c3d2689d | balrog | |
679 | c3d2689d | balrog | if (clk->parent) {
|
680 | c3d2689d | balrog | for (p = &clk->parent->child1; *p != clk; p = &(*p)->sibling);
|
681 | c3d2689d | balrog | *p = clk->sibling; |
682 | c3d2689d | balrog | } |
683 | c3d2689d | balrog | |
684 | c3d2689d | balrog | clk->parent = parent; |
685 | c3d2689d | balrog | if (parent) {
|
686 | c3d2689d | balrog | clk->sibling = parent->child1; |
687 | c3d2689d | balrog | parent->child1 = clk; |
688 | c3d2689d | balrog | omap_clk_update(clk); |
689 | c3d2689d | balrog | omap_clk_rate_update(clk); |
690 | c3d2689d | balrog | } else
|
691 | c3d2689d | balrog | clk->sibling = 0;
|
692 | c3d2689d | balrog | } |
693 | c3d2689d | balrog | |
694 | c3d2689d | balrog | void omap_clk_onoff(struct clk *clk, int on) |
695 | c3d2689d | balrog | { |
696 | c3d2689d | balrog | clk->enabled = on; |
697 | c3d2689d | balrog | omap_clk_update(clk); |
698 | c3d2689d | balrog | } |
699 | c3d2689d | balrog | |
700 | c3d2689d | balrog | void omap_clk_canidle(struct clk *clk, int can) |
701 | c3d2689d | balrog | { |
702 | c3d2689d | balrog | if (can)
|
703 | c3d2689d | balrog | omap_clk_put(clk); |
704 | c3d2689d | balrog | else
|
705 | c3d2689d | balrog | omap_clk_get(clk); |
706 | c3d2689d | balrog | } |
707 | c3d2689d | balrog | |
708 | c3d2689d | balrog | void omap_clk_setrate(struct clk *clk, int divide, int multiply) |
709 | c3d2689d | balrog | { |
710 | c3d2689d | balrog | clk->divisor = divide; |
711 | c3d2689d | balrog | clk->multiplier = multiply; |
712 | c3d2689d | balrog | omap_clk_rate_update(clk); |
713 | c3d2689d | balrog | } |
714 | c3d2689d | balrog | |
715 | c3d2689d | balrog | int64_t omap_clk_getrate(omap_clk clk) |
716 | c3d2689d | balrog | { |
717 | c3d2689d | balrog | return clk->rate;
|
718 | c3d2689d | balrog | } |
719 | c3d2689d | balrog | |
720 | c3d2689d | balrog | void omap_clk_init(struct omap_mpu_state_s *mpu) |
721 | c3d2689d | balrog | { |
722 | c3d2689d | balrog | struct clk **i, *j, *k;
|
723 | c3d2689d | balrog | int count;
|
724 | c3d2689d | balrog | int flag;
|
725 | c3d2689d | balrog | |
726 | c3d2689d | balrog | if (cpu_is_omap310(mpu))
|
727 | c3d2689d | balrog | flag = CLOCK_IN_OMAP310; |
728 | c3d2689d | balrog | else if (cpu_is_omap1510(mpu)) |
729 | c3d2689d | balrog | flag = CLOCK_IN_OMAP1510; |
730 | c3d2689d | balrog | else
|
731 | c3d2689d | balrog | return;
|
732 | c3d2689d | balrog | |
733 | c3d2689d | balrog | for (i = onchip_clks, count = 0; *i; i ++) |
734 | c3d2689d | balrog | if ((*i)->flags & flag)
|
735 | c3d2689d | balrog | count ++; |
736 | c3d2689d | balrog | mpu->clks = (struct clk *) qemu_mallocz(sizeof(struct clk) * (count + 1)); |
737 | c3d2689d | balrog | for (i = onchip_clks, j = mpu->clks; *i; i ++)
|
738 | c3d2689d | balrog | if ((*i)->flags & flag) {
|
739 | c3d2689d | balrog | memcpy(j, *i, sizeof(struct clk)); |
740 | c3d2689d | balrog | for (k = mpu->clks; k < j; k ++)
|
741 | c3d2689d | balrog | if (j->parent && !strcmp(j->parent->name, k->name)) {
|
742 | c3d2689d | balrog | j->parent = k; |
743 | c3d2689d | balrog | j->sibling = k->child1; |
744 | c3d2689d | balrog | k->child1 = j; |
745 | c3d2689d | balrog | } else if (k->parent && !strcmp(k->parent->name, j->name)) { |
746 | c3d2689d | balrog | k->parent = j; |
747 | c3d2689d | balrog | k->sibling = j->child1; |
748 | c3d2689d | balrog | j->child1 = k; |
749 | c3d2689d | balrog | } |
750 | c3d2689d | balrog | j->divisor = j->divisor ?: 1;
|
751 | c3d2689d | balrog | j->multiplier = j->multiplier ?: 1;
|
752 | c3d2689d | balrog | j ++; |
753 | c3d2689d | balrog | } |
754 | b854bc19 | balrog | for (j = mpu->clks; count --; j ++) {
|
755 | b854bc19 | balrog | omap_clk_update(j); |
756 | b854bc19 | balrog | omap_clk_rate_update(j); |
757 | b854bc19 | balrog | } |
758 | c3d2689d | balrog | } |