root / hw / cpu / a15mpcore.c @ 524a2d8e
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/*
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* Cortex-A15MPCore internal peripheral emulation.
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*
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* Copyright (c) 2012 Linaro Limited.
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* Written by Peter Maydell.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/sysbus.h" |
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#include "sysemu/kvm.h" |
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#include "hw/intc/arm_gic.h" |
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/* A15MP private memory region. */
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#define TYPE_A15MPCORE_PRIV "a15mpcore_priv" |
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#define A15MPCORE_PRIV(obj) \
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OBJECT_CHECK(A15MPPrivState, (obj), TYPE_A15MPCORE_PRIV) |
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typedef struct A15MPPrivState { |
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/*< private >*/
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SysBusDevice parent_obj; |
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/*< public >*/
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uint32_t num_cpu; |
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uint32_t num_irq; |
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MemoryRegion container; |
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GICState gic; |
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} A15MPPrivState; |
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static void a15mp_priv_set_irq(void *opaque, int irq, int level) |
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{ |
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A15MPPrivState *s = (A15MPPrivState *)opaque; |
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qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); |
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} |
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static void a15mp_priv_initfn(Object *obj) |
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{ |
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
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A15MPPrivState *s = A15MPCORE_PRIV(obj); |
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DeviceState *gicdev; |
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const char *gictype = "arm_gic"; |
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if (kvm_irqchip_in_kernel()) {
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gictype = "kvm-arm-gic";
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} |
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memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000); |
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sysbus_init_mmio(sbd, &s->container); |
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object_initialize(&s->gic, sizeof(s->gic), gictype);
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gicdev = DEVICE(&s->gic); |
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qdev_set_parent_bus(gicdev, sysbus_get_default()); |
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qdev_prop_set_uint32(gicdev, "revision", 2); |
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} |
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static int a15mp_priv_init(SysBusDevice *dev) |
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{ |
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A15MPPrivState *s = A15MPCORE_PRIV(dev); |
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DeviceState *gicdev; |
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SysBusDevice *busdev; |
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int i;
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gicdev = DEVICE(&s->gic); |
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qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
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qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
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qdev_init_nofail(gicdev); |
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busdev = SYS_BUS_DEVICE(&s->gic); |
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/* Pass through outbound IRQ lines from the GIC */
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sysbus_pass_irq(dev, busdev); |
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/* Pass through inbound GPIO lines to the GIC */
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qdev_init_gpio_in(DEVICE(dev), a15mp_priv_set_irq, s->num_irq - 32);
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/* Wire the outputs from each CPU's generic timer to the
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* appropriate GIC PPI inputs
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*/
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for (i = 0; i < s->num_cpu; i++) { |
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DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); |
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int ppibase = s->num_irq - 32 + i * 32; |
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/* physical timer; we wire it up to the non-secure timer's ID,
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* since a real A15 always has TrustZone but QEMU doesn't.
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*/
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qdev_connect_gpio_out(cpudev, 0,
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qdev_get_gpio_in(gicdev, ppibase + 30));
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/* virtual timer */
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qdev_connect_gpio_out(cpudev, 1,
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qdev_get_gpio_in(gicdev, ppibase + 27));
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} |
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/* Memory map (addresses are offsets from PERIPHBASE):
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* 0x0000-0x0fff -- reserved
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* 0x1000-0x1fff -- GIC Distributor
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* 0x2000-0x2fff -- GIC CPU interface
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* 0x4000-0x4fff -- GIC virtual interface control (not modelled)
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* 0x5000-0x5fff -- GIC virtual interface control (not modelled)
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* 0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
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*/
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memory_region_add_subregion(&s->container, 0x1000,
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sysbus_mmio_get_region(busdev, 0));
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memory_region_add_subregion(&s->container, 0x2000,
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sysbus_mmio_get_region(busdev, 1));
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return 0; |
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} |
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static Property a15mp_priv_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), |
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/* The Cortex-A15MP may have anything from 0 to 224 external interrupt
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* IRQ lines (with another 32 internal). We default to 128+32, which
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* is the number provided by the Cortex-A15MP test chip in the
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* Versatile Express A15 development board.
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* Other boards may differ and should set this property appropriately.
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*/
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DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160), |
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DEFINE_PROP_END_OF_LIST(), |
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}; |
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static void a15mp_priv_class_init(ObjectClass *klass, void *data) |
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{ |
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DeviceClass *dc = DEVICE_CLASS(klass); |
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
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k->init = a15mp_priv_init; |
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dc->props = a15mp_priv_properties; |
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/* We currently have no savable state */
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} |
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static const TypeInfo a15mp_priv_info = { |
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.name = TYPE_A15MPCORE_PRIV, |
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.parent = TYPE_SYS_BUS_DEVICE, |
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.instance_size = sizeof(A15MPPrivState),
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.instance_init = a15mp_priv_initfn, |
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.class_init = a15mp_priv_class_init, |
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}; |
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static void a15mp_register_types(void) |
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{ |
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type_register_static(&a15mp_priv_info); |
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} |
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type_init(a15mp_register_types) |