Revision 5251d196
| b/hw/pxa2xx_timer.c | ||
|---|---|---|
| 65 | 65 |
typedef struct {
|
| 66 | 66 |
uint32_t value; |
| 67 | 67 |
int level; |
| 68 |
qemu_irq irq; |
|
| 68 | 69 |
QEMUTimer *qtimer; |
| 69 | 70 |
int num; |
| 70 | 71 |
PXA2xxTimerInfo *info; |
| ... | ... | |
| 88 | 89 |
uint64_t lastload; |
| 89 | 90 |
uint32_t freq; |
| 90 | 91 |
PXA2xxTimer0 timer[4]; |
| 91 |
qemu_irq irqs[5]; |
|
| 92 | 92 |
uint32_t events; |
| 93 | 93 |
uint32_t irq_enabled; |
| 94 | 94 |
uint32_t reset3; |
| 95 | 95 |
uint32_t snapshot; |
| 96 | 96 |
|
| 97 | 97 |
PXA2xxTimer4 tm4[8]; |
| 98 |
qemu_irq irq4; |
|
| 99 | 98 |
}; |
| 100 | 99 |
|
| 101 | 100 |
#define PXA2XX_TIMER_HAVE_TM4 0 |
| ... | ... | |
| 282 | 281 |
for (i = 0; i < 4; i ++, value >>= 1) {
|
| 283 | 282 |
if (s->timer[i].level && (value & 1)) {
|
| 284 | 283 |
s->timer[i].level = 0; |
| 285 |
qemu_irq_lower(s->irqs[i]);
|
|
| 284 |
qemu_irq_lower(s->timer[i].irq);
|
|
| 286 | 285 |
} |
| 287 | 286 |
} |
| 288 | 287 |
if (pxa2xx_timer_has_tm4(s)) {
|
| ... | ... | |
| 290 | 289 |
if (s->tm4[i].tm.level && (value & 1)) |
| 291 | 290 |
s->tm4[i].tm.level = 0; |
| 292 | 291 |
if (!(s->events & 0xff0)) |
| 293 |
qemu_irq_lower(s->irq4);
|
|
| 292 |
qemu_irq_lower(s->tm4->tm.irq);
|
|
| 294 | 293 |
} |
| 295 | 294 |
break; |
| 296 | 295 |
case OWER: /* XXX: Reset on OSMR3 match? */ |
| ... | ... | |
| 353 | 352 |
if (i->irq_enabled & (1 << t->num)) {
|
| 354 | 353 |
t->level = 1; |
| 355 | 354 |
i->events |= 1 << t->num; |
| 356 |
qemu_irq_raise(t->num < 4 ? i->irqs[t->num] : i->irq4);
|
|
| 355 |
qemu_irq_raise(t->irq);
|
|
| 357 | 356 |
} |
| 358 | 357 |
|
| 359 | 358 |
if (t->num == 3) |
| ... | ... | |
| 396 | 395 |
int i; |
| 397 | 396 |
int iomemtype; |
| 398 | 397 |
PXA2xxTimerInfo *s; |
| 398 |
qemu_irq irq4; |
|
| 399 | 399 |
|
| 400 | 400 |
s = FROM_SYSBUS(PXA2xxTimerInfo, dev); |
| 401 | 401 |
s->irq_enabled = 0; |
| ... | ... | |
| 406 | 406 |
|
| 407 | 407 |
for (i = 0; i < 4; i ++) {
|
| 408 | 408 |
s->timer[i].value = 0; |
| 409 |
sysbus_init_irq(dev, &s->irqs[i]);
|
|
| 409 |
sysbus_init_irq(dev, &s->timer[i].irq);
|
|
| 410 | 410 |
s->timer[i].info = s; |
| 411 | 411 |
s->timer[i].num = i; |
| 412 | 412 |
s->timer[i].level = 0; |
| ... | ... | |
| 414 | 414 |
pxa2xx_timer_tick, &s->timer[i]); |
| 415 | 415 |
} |
| 416 | 416 |
if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
|
| 417 |
sysbus_init_irq(dev, &s->irq4);
|
|
| 417 |
sysbus_init_irq(dev, &irq4); |
|
| 418 | 418 |
|
| 419 | 419 |
for (i = 0; i < 8; i ++) {
|
| 420 | 420 |
s->tm4[i].tm.value = 0; |
| ... | ... | |
| 425 | 425 |
s->tm4[i].control = 0x0; |
| 426 | 426 |
s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock, |
| 427 | 427 |
pxa2xx_timer_tick4, &s->tm4[i]); |
| 428 |
s->tm4[i].tm.irq = irq4; |
|
| 428 | 429 |
} |
| 429 | 430 |
} |
| 430 | 431 |
|
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