root / target-arm / translate-a64.c @ 52c8b9af
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/*
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* AArch64 translation
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*
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* Copyright (c) 2013 Alexander Graf <agraf@suse.de>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include "cpu.h" |
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#include "tcg-op.h" |
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#include "qemu/log.h" |
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#include "translate.h" |
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#include "qemu/host-utils.h" |
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#include "exec/gen-icount.h" |
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#include "helper.h" |
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#define GEN_HELPER 1 |
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#include "helper.h" |
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static TCGv_i64 cpu_X[32]; |
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static TCGv_i64 cpu_pc;
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static TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
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static const char *regnames[] = { |
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"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", |
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"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", |
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"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", |
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"x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp" |
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}; |
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enum a64_shift_type {
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A64_SHIFT_TYPE_LSL = 0,
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A64_SHIFT_TYPE_LSR = 1,
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A64_SHIFT_TYPE_ASR = 2,
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A64_SHIFT_TYPE_ROR = 3
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}; |
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/* initialize TCG globals. */
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void a64_translate_init(void) |
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{ |
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int i;
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cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, |
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offsetof(CPUARMState, pc), |
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"pc");
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for (i = 0; i < 32; i++) { |
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cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0, |
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offsetof(CPUARMState, xregs[i]), |
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regnames[i]); |
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} |
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cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF), "NF");
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cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF), "ZF");
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cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF), "CF");
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cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF), "VF");
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} |
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void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
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fprintf_function cpu_fprintf, int flags)
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{ |
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ARMCPU *cpu = ARM_CPU(cs); |
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CPUARMState *env = &cpu->env; |
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uint32_t psr = pstate_read(env); |
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int i;
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cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", |
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env->pc, env->xregs[31]);
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for (i = 0; i < 31; i++) { |
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cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
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if ((i % 4) == 3) { |
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cpu_fprintf(f, "\n");
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} else {
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cpu_fprintf(f, " ");
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} |
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} |
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cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n",
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psr, |
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psr & PSTATE_N ? 'N' : '-', |
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psr & PSTATE_Z ? 'Z' : '-', |
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psr & PSTATE_C ? 'C' : '-', |
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psr & PSTATE_V ? 'V' : '-'); |
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cpu_fprintf(f, "\n");
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} |
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static int get_mem_index(DisasContext *s) |
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{ |
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#ifdef CONFIG_USER_ONLY
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return 1; |
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#else
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return s->user;
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#endif
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} |
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void gen_a64_set_pc_im(uint64_t val)
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{ |
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tcg_gen_movi_i64(cpu_pc, val); |
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} |
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static void gen_exception(int excp) |
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{ |
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TCGv_i32 tmp = tcg_temp_new_i32(); |
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tcg_gen_movi_i32(tmp, excp); |
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gen_helper_exception(cpu_env, tmp); |
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tcg_temp_free_i32(tmp); |
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} |
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static void gen_exception_insn(DisasContext *s, int offset, int excp) |
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{ |
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gen_a64_set_pc_im(s->pc - offset); |
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gen_exception(excp); |
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s->is_jmp = DISAS_EXC; |
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} |
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static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) |
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{ |
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/* No direct tb linking with singlestep or deterministic io */
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if (s->singlestep_enabled || (s->tb->cflags & CF_LAST_IO)) {
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return false; |
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} |
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/* Only link tbs from inside the same guest page */
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if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
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return false; |
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} |
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return true; |
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} |
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static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) |
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{ |
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TranslationBlock *tb; |
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tb = s->tb; |
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if (use_goto_tb(s, n, dest)) {
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tcg_gen_goto_tb(n); |
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gen_a64_set_pc_im(dest); |
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tcg_gen_exit_tb((tcg_target_long)tb + n); |
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s->is_jmp = DISAS_TB_JUMP; |
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} else {
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gen_a64_set_pc_im(dest); |
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if (s->singlestep_enabled) {
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gen_exception(EXCP_DEBUG); |
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} |
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tcg_gen_exit_tb(0);
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s->is_jmp = DISAS_JUMP; |
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} |
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} |
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static void unallocated_encoding(DisasContext *s) |
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{ |
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gen_exception_insn(s, 4, EXCP_UDEF);
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} |
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#define unsupported_encoding(s, insn) \
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do { \
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qemu_log_mask(LOG_UNIMP, \ |
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"%s:%d: unsupported instruction encoding 0x%08x " \
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"at pc=%016" PRIx64 "\n", \ |
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__FILE__, __LINE__, insn, s->pc - 4); \
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unallocated_encoding(s); \ |
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} while (0); |
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static void init_tmp_a64_array(DisasContext *s) |
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{ |
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#ifdef CONFIG_DEBUG_TCG
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int i;
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for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) { |
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TCGV_UNUSED_I64(s->tmp_a64[i]); |
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} |
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#endif
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s->tmp_a64_count = 0;
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} |
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static void free_tmp_a64(DisasContext *s) |
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{ |
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int i;
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for (i = 0; i < s->tmp_a64_count; i++) { |
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tcg_temp_free_i64(s->tmp_a64[i]); |
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} |
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init_tmp_a64_array(s); |
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} |
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static TCGv_i64 new_tmp_a64(DisasContext *s)
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{ |
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assert(s->tmp_a64_count < TMP_A64_MAX); |
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return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
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} |
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static TCGv_i64 new_tmp_a64_zero(DisasContext *s)
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{ |
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TCGv_i64 t = new_tmp_a64(s); |
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tcg_gen_movi_i64(t, 0);
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return t;
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} |
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/*
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* Register access functions
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*
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* These functions are used for directly accessing a register in where
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* changes to the final register value are likely to be made. If you
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* need to use a register for temporary calculation (e.g. index type
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* operations) use the read_* form.
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*
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* B1.2.1 Register mappings
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*
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* In instruction register encoding 31 can refer to ZR (zero register) or
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* the SP (stack pointer) depending on context. In QEMU's case we map SP
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* to cpu_X[31] and ZR accesses to a temporary which can be discarded.
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* This is the point of the _sp forms.
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*/
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static TCGv_i64 cpu_reg(DisasContext *s, int reg) |
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{ |
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if (reg == 31) { |
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return new_tmp_a64_zero(s);
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} else {
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return cpu_X[reg];
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} |
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} |
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/* register access for when 31 == SP */
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static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) |
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{ |
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return cpu_X[reg];
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} |
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/* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
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* representing the register contents. This TCGv is an auto-freed
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* temporary so it need not be explicitly freed, and may be modified.
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*/
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static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) |
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{ |
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TCGv_i64 v = new_tmp_a64(s); |
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if (reg != 31) { |
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if (sf) {
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tcg_gen_mov_i64(v, cpu_X[reg]); |
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} else {
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tcg_gen_ext32u_i64(v, cpu_X[reg]); |
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} |
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} else {
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tcg_gen_movi_i64(v, 0);
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} |
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return v;
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} |
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static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf) |
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{ |
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TCGv_i64 v = new_tmp_a64(s); |
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if (sf) {
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tcg_gen_mov_i64(v, cpu_X[reg]); |
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} else {
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tcg_gen_ext32u_i64(v, cpu_X[reg]); |
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} |
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return v;
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} |
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/* Set ZF and NF based on a 64 bit result. This is alas fiddlier
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* than the 32 bit equivalent.
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*/
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static inline void gen_set_NZ64(TCGv_i64 result) |
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{ |
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TCGv_i64 flag = tcg_temp_new_i64(); |
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tcg_gen_setcondi_i64(TCG_COND_NE, flag, result, 0);
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tcg_gen_trunc_i64_i32(cpu_ZF, flag); |
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tcg_gen_shri_i64(flag, result, 32);
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tcg_gen_trunc_i64_i32(cpu_NF, flag); |
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tcg_temp_free_i64(flag); |
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} |
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/* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
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static inline void gen_logic_CC(int sf, TCGv_i64 result) |
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{ |
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if (sf) {
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gen_set_NZ64(result); |
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} else {
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tcg_gen_trunc_i64_i32(cpu_ZF, result); |
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tcg_gen_trunc_i64_i32(cpu_NF, result); |
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} |
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tcg_gen_movi_i32(cpu_CF, 0);
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tcg_gen_movi_i32(cpu_VF, 0);
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} |
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/* dest = T0 + T1; compute C, N, V and Z flags */
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static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) |
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{ |
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if (sf) {
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TCGv_i64 result, flag, tmp; |
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result = tcg_temp_new_i64(); |
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flag = tcg_temp_new_i64(); |
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tmp = tcg_temp_new_i64(); |
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tcg_gen_movi_i64(tmp, 0);
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tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp); |
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tcg_gen_trunc_i64_i32(cpu_CF, flag); |
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gen_set_NZ64(result); |
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tcg_gen_xor_i64(flag, result, t0); |
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tcg_gen_xor_i64(tmp, t0, t1); |
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tcg_gen_andc_i64(flag, flag, tmp); |
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tcg_temp_free_i64(tmp); |
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tcg_gen_shri_i64(flag, flag, 32);
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tcg_gen_trunc_i64_i32(cpu_VF, flag); |
322 |
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tcg_gen_mov_i64(dest, result); |
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tcg_temp_free_i64(result); |
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tcg_temp_free_i64(flag); |
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} else {
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/* 32 bit arithmetic */
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TCGv_i32 t0_32 = tcg_temp_new_i32(); |
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TCGv_i32 t1_32 = tcg_temp_new_i32(); |
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TCGv_i32 tmp = tcg_temp_new_i32(); |
331 |
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tcg_gen_movi_i32(tmp, 0);
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tcg_gen_trunc_i64_i32(t0_32, t0); |
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tcg_gen_trunc_i64_i32(t1_32, t1); |
335 |
tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); |
336 |
tcg_gen_mov_i32(cpu_ZF, cpu_NF); |
337 |
tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); |
338 |
tcg_gen_xor_i32(tmp, t0_32, t1_32); |
339 |
tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); |
340 |
tcg_gen_extu_i32_i64(dest, cpu_NF); |
341 |
|
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tcg_temp_free_i32(tmp); |
343 |
tcg_temp_free_i32(t0_32); |
344 |
tcg_temp_free_i32(t1_32); |
345 |
} |
346 |
} |
347 |
|
348 |
/* dest = T0 - T1; compute C, N, V and Z flags */
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static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) |
350 |
{ |
351 |
if (sf) {
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/* 64 bit arithmetic */
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TCGv_i64 result, flag, tmp; |
354 |
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result = tcg_temp_new_i64(); |
356 |
flag = tcg_temp_new_i64(); |
357 |
tcg_gen_sub_i64(result, t0, t1); |
358 |
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359 |
gen_set_NZ64(result); |
360 |
|
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tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1); |
362 |
tcg_gen_trunc_i64_i32(cpu_CF, flag); |
363 |
|
364 |
tcg_gen_xor_i64(flag, result, t0); |
365 |
tmp = tcg_temp_new_i64(); |
366 |
tcg_gen_xor_i64(tmp, t0, t1); |
367 |
tcg_gen_and_i64(flag, flag, tmp); |
368 |
tcg_temp_free_i64(tmp); |
369 |
tcg_gen_shri_i64(flag, flag, 32);
|
370 |
tcg_gen_trunc_i64_i32(cpu_VF, flag); |
371 |
tcg_gen_mov_i64(dest, result); |
372 |
tcg_temp_free_i64(flag); |
373 |
tcg_temp_free_i64(result); |
374 |
} else {
|
375 |
/* 32 bit arithmetic */
|
376 |
TCGv_i32 t0_32 = tcg_temp_new_i32(); |
377 |
TCGv_i32 t1_32 = tcg_temp_new_i32(); |
378 |
TCGv_i32 tmp; |
379 |
|
380 |
tcg_gen_trunc_i64_i32(t0_32, t0); |
381 |
tcg_gen_trunc_i64_i32(t1_32, t1); |
382 |
tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); |
383 |
tcg_gen_mov_i32(cpu_ZF, cpu_NF); |
384 |
tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); |
385 |
tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); |
386 |
tmp = tcg_temp_new_i32(); |
387 |
tcg_gen_xor_i32(tmp, t0_32, t1_32); |
388 |
tcg_temp_free_i32(t0_32); |
389 |
tcg_temp_free_i32(t1_32); |
390 |
tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); |
391 |
tcg_temp_free_i32(tmp); |
392 |
tcg_gen_extu_i32_i64(dest, cpu_NF); |
393 |
} |
394 |
} |
395 |
|
396 |
/*
|
397 |
* Load/Store generators
|
398 |
*/
|
399 |
|
400 |
/*
|
401 |
* Store from GPR register to memory
|
402 |
*/
|
403 |
static void do_gpr_st(DisasContext *s, TCGv_i64 source, |
404 |
TCGv_i64 tcg_addr, int size)
|
405 |
{ |
406 |
g_assert(size <= 3);
|
407 |
tcg_gen_qemu_st_i64(source, tcg_addr, get_mem_index(s), MO_TE + size); |
408 |
} |
409 |
|
410 |
/*
|
411 |
* Load from memory to GPR register
|
412 |
*/
|
413 |
static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr, |
414 |
int size, bool is_signed, bool extend) |
415 |
{ |
416 |
TCGMemOp memop = MO_TE + size; |
417 |
|
418 |
g_assert(size <= 3);
|
419 |
|
420 |
if (is_signed) {
|
421 |
memop += MO_SIGN; |
422 |
} |
423 |
|
424 |
tcg_gen_qemu_ld_i64(dest, tcg_addr, get_mem_index(s), memop); |
425 |
|
426 |
if (extend && is_signed) {
|
427 |
g_assert(size < 3);
|
428 |
tcg_gen_ext32u_i64(dest, dest); |
429 |
} |
430 |
} |
431 |
|
432 |
/*
|
433 |
* Store from FP register to memory
|
434 |
*/
|
435 |
static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size) |
436 |
{ |
437 |
/* This writes the bottom N bits of a 128 bit wide vector to memory */
|
438 |
int freg_offs = offsetof(CPUARMState, vfp.regs[srcidx * 2]); |
439 |
TCGv_i64 tmp = tcg_temp_new_i64(); |
440 |
|
441 |
if (size < 4) { |
442 |
switch (size) {
|
443 |
case 0: |
444 |
tcg_gen_ld8u_i64(tmp, cpu_env, freg_offs); |
445 |
break;
|
446 |
case 1: |
447 |
tcg_gen_ld16u_i64(tmp, cpu_env, freg_offs); |
448 |
break;
|
449 |
case 2: |
450 |
tcg_gen_ld32u_i64(tmp, cpu_env, freg_offs); |
451 |
break;
|
452 |
case 3: |
453 |
tcg_gen_ld_i64(tmp, cpu_env, freg_offs); |
454 |
break;
|
455 |
} |
456 |
tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TE + size); |
457 |
} else {
|
458 |
TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(); |
459 |
tcg_gen_ld_i64(tmp, cpu_env, freg_offs); |
460 |
tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TEQ); |
461 |
tcg_gen_qemu_st64(tmp, tcg_addr, get_mem_index(s)); |
462 |
tcg_gen_ld_i64(tmp, cpu_env, freg_offs + sizeof(float64));
|
463 |
tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
|
464 |
tcg_gen_qemu_st_i64(tmp, tcg_hiaddr, get_mem_index(s), MO_TEQ); |
465 |
tcg_temp_free_i64(tcg_hiaddr); |
466 |
} |
467 |
|
468 |
tcg_temp_free_i64(tmp); |
469 |
} |
470 |
|
471 |
/*
|
472 |
* Load from memory to FP register
|
473 |
*/
|
474 |
static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) |
475 |
{ |
476 |
/* This always zero-extends and writes to a full 128 bit wide vector */
|
477 |
int freg_offs = offsetof(CPUARMState, vfp.regs[destidx * 2]); |
478 |
TCGv_i64 tmplo = tcg_temp_new_i64(); |
479 |
TCGv_i64 tmphi; |
480 |
|
481 |
if (size < 4) { |
482 |
TCGMemOp memop = MO_TE + size; |
483 |
tmphi = tcg_const_i64(0);
|
484 |
tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); |
485 |
} else {
|
486 |
TCGv_i64 tcg_hiaddr; |
487 |
tmphi = tcg_temp_new_i64(); |
488 |
tcg_hiaddr = tcg_temp_new_i64(); |
489 |
|
490 |
tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), MO_TEQ); |
491 |
tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
|
492 |
tcg_gen_qemu_ld_i64(tmphi, tcg_hiaddr, get_mem_index(s), MO_TEQ); |
493 |
tcg_temp_free_i64(tcg_hiaddr); |
494 |
} |
495 |
|
496 |
tcg_gen_st_i64(tmplo, cpu_env, freg_offs); |
497 |
tcg_gen_st_i64(tmphi, cpu_env, freg_offs + sizeof(float64));
|
498 |
|
499 |
tcg_temp_free_i64(tmplo); |
500 |
tcg_temp_free_i64(tmphi); |
501 |
} |
502 |
|
503 |
/*
|
504 |
* This utility function is for doing register extension with an
|
505 |
* optional shift. You will likely want to pass a temporary for the
|
506 |
* destination register. See DecodeRegExtend() in the ARM ARM.
|
507 |
*/
|
508 |
static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in, |
509 |
int option, unsigned int shift) |
510 |
{ |
511 |
int extsize = extract32(option, 0, 2); |
512 |
bool is_signed = extract32(option, 2, 1); |
513 |
|
514 |
if (is_signed) {
|
515 |
switch (extsize) {
|
516 |
case 0: |
517 |
tcg_gen_ext8s_i64(tcg_out, tcg_in); |
518 |
break;
|
519 |
case 1: |
520 |
tcg_gen_ext16s_i64(tcg_out, tcg_in); |
521 |
break;
|
522 |
case 2: |
523 |
tcg_gen_ext32s_i64(tcg_out, tcg_in); |
524 |
break;
|
525 |
case 3: |
526 |
tcg_gen_mov_i64(tcg_out, tcg_in); |
527 |
break;
|
528 |
} |
529 |
} else {
|
530 |
switch (extsize) {
|
531 |
case 0: |
532 |
tcg_gen_ext8u_i64(tcg_out, tcg_in); |
533 |
break;
|
534 |
case 1: |
535 |
tcg_gen_ext16u_i64(tcg_out, tcg_in); |
536 |
break;
|
537 |
case 2: |
538 |
tcg_gen_ext32u_i64(tcg_out, tcg_in); |
539 |
break;
|
540 |
case 3: |
541 |
tcg_gen_mov_i64(tcg_out, tcg_in); |
542 |
break;
|
543 |
} |
544 |
} |
545 |
|
546 |
if (shift) {
|
547 |
tcg_gen_shli_i64(tcg_out, tcg_out, shift); |
548 |
} |
549 |
} |
550 |
|
551 |
static inline void gen_check_sp_alignment(DisasContext *s) |
552 |
{ |
553 |
/* The AArch64 architecture mandates that (if enabled via PSTATE
|
554 |
* or SCTLR bits) there is a check that SP is 16-aligned on every
|
555 |
* SP-relative load or store (with an exception generated if it is not).
|
556 |
* In line with general QEMU practice regarding misaligned accesses,
|
557 |
* we omit these checks for the sake of guest program performance.
|
558 |
* This function is provided as a hook so we can more easily add these
|
559 |
* checks in future (possibly as a "favour catching guest program bugs
|
560 |
* over speed" user selectable option).
|
561 |
*/
|
562 |
} |
563 |
|
564 |
/*
|
565 |
* the instruction disassembly implemented here matches
|
566 |
* the instruction encoding classifications in chapter 3 (C3)
|
567 |
* of the ARM Architecture Reference Manual (DDI0487A_a)
|
568 |
*/
|
569 |
|
570 |
/* C3.2.7 Unconditional branch (immediate)
|
571 |
* 31 30 26 25 0
|
572 |
* +----+-----------+-------------------------------------+
|
573 |
* | op | 0 0 1 0 1 | imm26 |
|
574 |
* +----+-----------+-------------------------------------+
|
575 |
*/
|
576 |
static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) |
577 |
{ |
578 |
uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4; |
579 |
|
580 |
if (insn & (1 << 31)) { |
581 |
/* C5.6.26 BL Branch with link */
|
582 |
tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
|
583 |
} |
584 |
|
585 |
/* C5.6.20 B Branch / C5.6.26 BL Branch with link */
|
586 |
gen_goto_tb(s, 0, addr);
|
587 |
} |
588 |
|
589 |
/* C3.2.1 Compare & branch (immediate)
|
590 |
* 31 30 25 24 23 5 4 0
|
591 |
* +----+-------------+----+---------------------+--------+
|
592 |
* | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
|
593 |
* +----+-------------+----+---------------------+--------+
|
594 |
*/
|
595 |
static void disas_comp_b_imm(DisasContext *s, uint32_t insn) |
596 |
{ |
597 |
unsigned int sf, op, rt; |
598 |
uint64_t addr; |
599 |
int label_match;
|
600 |
TCGv_i64 tcg_cmp; |
601 |
|
602 |
sf = extract32(insn, 31, 1); |
603 |
op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ |
604 |
rt = extract32(insn, 0, 5); |
605 |
addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; |
606 |
|
607 |
tcg_cmp = read_cpu_reg(s, rt, sf); |
608 |
label_match = gen_new_label(); |
609 |
|
610 |
tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, |
611 |
tcg_cmp, 0, label_match);
|
612 |
|
613 |
gen_goto_tb(s, 0, s->pc);
|
614 |
gen_set_label(label_match); |
615 |
gen_goto_tb(s, 1, addr);
|
616 |
} |
617 |
|
618 |
/* C3.2.5 Test & branch (immediate)
|
619 |
* 31 30 25 24 23 19 18 5 4 0
|
620 |
* +----+-------------+----+-------+-------------+------+
|
621 |
* | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
|
622 |
* +----+-------------+----+-------+-------------+------+
|
623 |
*/
|
624 |
static void disas_test_b_imm(DisasContext *s, uint32_t insn) |
625 |
{ |
626 |
unsigned int bit_pos, op, rt; |
627 |
uint64_t addr; |
628 |
int label_match;
|
629 |
TCGv_i64 tcg_cmp; |
630 |
|
631 |
bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); |
632 |
op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ |
633 |
addr = s->pc + sextract32(insn, 5, 14) * 4 - 4; |
634 |
rt = extract32(insn, 0, 5); |
635 |
|
636 |
tcg_cmp = tcg_temp_new_i64(); |
637 |
tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos));
|
638 |
label_match = gen_new_label(); |
639 |
tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, |
640 |
tcg_cmp, 0, label_match);
|
641 |
tcg_temp_free_i64(tcg_cmp); |
642 |
gen_goto_tb(s, 0, s->pc);
|
643 |
gen_set_label(label_match); |
644 |
gen_goto_tb(s, 1, addr);
|
645 |
} |
646 |
|
647 |
/* C3.2.2 / C5.6.19 Conditional branch (immediate)
|
648 |
* 31 25 24 23 5 4 3 0
|
649 |
* +---------------+----+---------------------+----+------+
|
650 |
* | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
|
651 |
* +---------------+----+---------------------+----+------+
|
652 |
*/
|
653 |
static void disas_cond_b_imm(DisasContext *s, uint32_t insn) |
654 |
{ |
655 |
unsigned int cond; |
656 |
uint64_t addr; |
657 |
|
658 |
if ((insn & (1 << 4)) || (insn & (1 << 24))) { |
659 |
unallocated_encoding(s); |
660 |
return;
|
661 |
} |
662 |
addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; |
663 |
cond = extract32(insn, 0, 4); |
664 |
|
665 |
if (cond < 0x0e) { |
666 |
/* genuinely conditional branches */
|
667 |
int label_match = gen_new_label();
|
668 |
arm_gen_test_cc(cond, label_match); |
669 |
gen_goto_tb(s, 0, s->pc);
|
670 |
gen_set_label(label_match); |
671 |
gen_goto_tb(s, 1, addr);
|
672 |
} else {
|
673 |
/* 0xe and 0xf are both "always" conditions */
|
674 |
gen_goto_tb(s, 0, addr);
|
675 |
} |
676 |
} |
677 |
|
678 |
/* C5.6.68 HINT */
|
679 |
static void handle_hint(DisasContext *s, uint32_t insn, |
680 |
unsigned int op1, unsigned int op2, unsigned int crm) |
681 |
{ |
682 |
unsigned int selector = crm << 3 | op2; |
683 |
|
684 |
if (op1 != 3) { |
685 |
unallocated_encoding(s); |
686 |
return;
|
687 |
} |
688 |
|
689 |
switch (selector) {
|
690 |
case 0: /* NOP */ |
691 |
return;
|
692 |
case 1: /* YIELD */ |
693 |
case 2: /* WFE */ |
694 |
case 3: /* WFI */ |
695 |
case 4: /* SEV */ |
696 |
case 5: /* SEVL */ |
697 |
/* we treat all as NOP at least for now */
|
698 |
return;
|
699 |
default:
|
700 |
/* default specified as NOP equivalent */
|
701 |
return;
|
702 |
} |
703 |
} |
704 |
|
705 |
/* CLREX, DSB, DMB, ISB */
|
706 |
static void handle_sync(DisasContext *s, uint32_t insn, |
707 |
unsigned int op1, unsigned int op2, unsigned int crm) |
708 |
{ |
709 |
if (op1 != 3) { |
710 |
unallocated_encoding(s); |
711 |
return;
|
712 |
} |
713 |
|
714 |
switch (op2) {
|
715 |
case 2: /* CLREX */ |
716 |
unsupported_encoding(s, insn); |
717 |
return;
|
718 |
case 4: /* DSB */ |
719 |
case 5: /* DMB */ |
720 |
case 6: /* ISB */ |
721 |
/* We don't emulate caches so barriers are no-ops */
|
722 |
return;
|
723 |
default:
|
724 |
unallocated_encoding(s); |
725 |
return;
|
726 |
} |
727 |
} |
728 |
|
729 |
/* C5.6.130 MSR (immediate) - move immediate to processor state field */
|
730 |
static void handle_msr_i(DisasContext *s, uint32_t insn, |
731 |
unsigned int op1, unsigned int op2, unsigned int crm) |
732 |
{ |
733 |
unsupported_encoding(s, insn); |
734 |
} |
735 |
|
736 |
/* C5.6.204 SYS */
|
737 |
static void handle_sys(DisasContext *s, uint32_t insn, unsigned int l, |
738 |
unsigned int op1, unsigned int op2, |
739 |
unsigned int crn, unsigned int crm, unsigned int rt) |
740 |
{ |
741 |
unsupported_encoding(s, insn); |
742 |
} |
743 |
|
744 |
/* C5.6.129 MRS - move from system register */
|
745 |
static void handle_mrs(DisasContext *s, uint32_t insn, unsigned int op0, |
746 |
unsigned int op1, unsigned int op2, |
747 |
unsigned int crn, unsigned int crm, unsigned int rt) |
748 |
{ |
749 |
unsupported_encoding(s, insn); |
750 |
} |
751 |
|
752 |
/* C5.6.131 MSR (register) - move to system register */
|
753 |
static void handle_msr(DisasContext *s, uint32_t insn, unsigned int op0, |
754 |
unsigned int op1, unsigned int op2, |
755 |
unsigned int crn, unsigned int crm, unsigned int rt) |
756 |
{ |
757 |
unsupported_encoding(s, insn); |
758 |
} |
759 |
|
760 |
/* C3.2.4 System
|
761 |
* 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
|
762 |
* +---------------------+---+-----+-----+-------+-------+-----+------+
|
763 |
* | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
|
764 |
* +---------------------+---+-----+-----+-------+-------+-----+------+
|
765 |
*/
|
766 |
static void disas_system(DisasContext *s, uint32_t insn) |
767 |
{ |
768 |
unsigned int l, op0, op1, crn, crm, op2, rt; |
769 |
l = extract32(insn, 21, 1); |
770 |
op0 = extract32(insn, 19, 2); |
771 |
op1 = extract32(insn, 16, 3); |
772 |
crn = extract32(insn, 12, 4); |
773 |
crm = extract32(insn, 8, 4); |
774 |
op2 = extract32(insn, 5, 3); |
775 |
rt = extract32(insn, 0, 5); |
776 |
|
777 |
if (op0 == 0) { |
778 |
if (l || rt != 31) { |
779 |
unallocated_encoding(s); |
780 |
return;
|
781 |
} |
782 |
switch (crn) {
|
783 |
case 2: /* C5.6.68 HINT */ |
784 |
handle_hint(s, insn, op1, op2, crm); |
785 |
break;
|
786 |
case 3: /* CLREX, DSB, DMB, ISB */ |
787 |
handle_sync(s, insn, op1, op2, crm); |
788 |
break;
|
789 |
case 4: /* C5.6.130 MSR (immediate) */ |
790 |
handle_msr_i(s, insn, op1, op2, crm); |
791 |
break;
|
792 |
default:
|
793 |
unallocated_encoding(s); |
794 |
break;
|
795 |
} |
796 |
return;
|
797 |
} |
798 |
|
799 |
if (op0 == 1) { |
800 |
/* C5.6.204 SYS */
|
801 |
handle_sys(s, insn, l, op1, op2, crn, crm, rt); |
802 |
} else if (l) { /* op0 > 1 */ |
803 |
/* C5.6.129 MRS - move from system register */
|
804 |
handle_mrs(s, insn, op0, op1, op2, crn, crm, rt); |
805 |
} else {
|
806 |
/* C5.6.131 MSR (register) - move to system register */
|
807 |
handle_msr(s, insn, op0, op1, op2, crn, crm, rt); |
808 |
} |
809 |
} |
810 |
|
811 |
/* Exception generation */
|
812 |
static void disas_exc(DisasContext *s, uint32_t insn) |
813 |
{ |
814 |
unsupported_encoding(s, insn); |
815 |
} |
816 |
|
817 |
/* C3.2.7 Unconditional branch (register)
|
818 |
* 31 25 24 21 20 16 15 10 9 5 4 0
|
819 |
* +---------------+-------+-------+-------+------+-------+
|
820 |
* | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
|
821 |
* +---------------+-------+-------+-------+------+-------+
|
822 |
*/
|
823 |
static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) |
824 |
{ |
825 |
unsigned int opc, op2, op3, rn, op4; |
826 |
|
827 |
opc = extract32(insn, 21, 4); |
828 |
op2 = extract32(insn, 16, 5); |
829 |
op3 = extract32(insn, 10, 6); |
830 |
rn = extract32(insn, 5, 5); |
831 |
op4 = extract32(insn, 0, 5); |
832 |
|
833 |
if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) { |
834 |
unallocated_encoding(s); |
835 |
return;
|
836 |
} |
837 |
|
838 |
switch (opc) {
|
839 |
case 0: /* BR */ |
840 |
case 2: /* RET */ |
841 |
break;
|
842 |
case 1: /* BLR */ |
843 |
tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
|
844 |
break;
|
845 |
case 4: /* ERET */ |
846 |
case 5: /* DRPS */ |
847 |
if (rn != 0x1f) { |
848 |
unallocated_encoding(s); |
849 |
} else {
|
850 |
unsupported_encoding(s, insn); |
851 |
} |
852 |
return;
|
853 |
default:
|
854 |
unallocated_encoding(s); |
855 |
return;
|
856 |
} |
857 |
|
858 |
tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn)); |
859 |
s->is_jmp = DISAS_JUMP; |
860 |
} |
861 |
|
862 |
/* C3.2 Branches, exception generating and system instructions */
|
863 |
static void disas_b_exc_sys(DisasContext *s, uint32_t insn) |
864 |
{ |
865 |
switch (extract32(insn, 25, 7)) { |
866 |
case 0x0a: case 0x0b: |
867 |
case 0x4a: case 0x4b: /* Unconditional branch (immediate) */ |
868 |
disas_uncond_b_imm(s, insn); |
869 |
break;
|
870 |
case 0x1a: case 0x5a: /* Compare & branch (immediate) */ |
871 |
disas_comp_b_imm(s, insn); |
872 |
break;
|
873 |
case 0x1b: case 0x5b: /* Test & branch (immediate) */ |
874 |
disas_test_b_imm(s, insn); |
875 |
break;
|
876 |
case 0x2a: /* Conditional branch (immediate) */ |
877 |
disas_cond_b_imm(s, insn); |
878 |
break;
|
879 |
case 0x6a: /* Exception generation / System */ |
880 |
if (insn & (1 << 24)) { |
881 |
disas_system(s, insn); |
882 |
} else {
|
883 |
disas_exc(s, insn); |
884 |
} |
885 |
break;
|
886 |
case 0x6b: /* Unconditional branch (register) */ |
887 |
disas_uncond_b_reg(s, insn); |
888 |
break;
|
889 |
default:
|
890 |
unallocated_encoding(s); |
891 |
break;
|
892 |
} |
893 |
} |
894 |
|
895 |
/* Load/store exclusive */
|
896 |
static void disas_ldst_excl(DisasContext *s, uint32_t insn) |
897 |
{ |
898 |
unsupported_encoding(s, insn); |
899 |
} |
900 |
|
901 |
/* Load register (literal) */
|
902 |
static void disas_ld_lit(DisasContext *s, uint32_t insn) |
903 |
{ |
904 |
unsupported_encoding(s, insn); |
905 |
} |
906 |
|
907 |
/*
|
908 |
* C5.6.80 LDNP (Load Pair - non-temporal hint)
|
909 |
* C5.6.81 LDP (Load Pair - non vector)
|
910 |
* C5.6.82 LDPSW (Load Pair Signed Word - non vector)
|
911 |
* C5.6.176 STNP (Store Pair - non-temporal hint)
|
912 |
* C5.6.177 STP (Store Pair - non vector)
|
913 |
* C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
|
914 |
* C6.3.165 LDP (Load Pair of SIMD&FP)
|
915 |
* C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
|
916 |
* C6.3.284 STP (Store Pair of SIMD&FP)
|
917 |
*
|
918 |
* 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
|
919 |
* +-----+-------+---+---+-------+---+-----------------------------+
|
920 |
* | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
|
921 |
* +-----+-------+---+---+-------+---+-------+-------+------+------+
|
922 |
*
|
923 |
* opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
|
924 |
* LDPSW 01
|
925 |
* LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
|
926 |
* V: 0 -> GPR, 1 -> Vector
|
927 |
* idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
|
928 |
* 10 -> signed offset, 11 -> pre-index
|
929 |
* L: 0 -> Store 1 -> Load
|
930 |
*
|
931 |
* Rt, Rt2 = GPR or SIMD registers to be stored
|
932 |
* Rn = general purpose register containing address
|
933 |
* imm7 = signed offset (multiple of 4 or 8 depending on size)
|
934 |
*/
|
935 |
static void disas_ldst_pair(DisasContext *s, uint32_t insn) |
936 |
{ |
937 |
int rt = extract32(insn, 0, 5); |
938 |
int rn = extract32(insn, 5, 5); |
939 |
int rt2 = extract32(insn, 10, 5); |
940 |
int64_t offset = sextract32(insn, 15, 7); |
941 |
int index = extract32(insn, 23, 2); |
942 |
bool is_vector = extract32(insn, 26, 1); |
943 |
bool is_load = extract32(insn, 22, 1); |
944 |
int opc = extract32(insn, 30, 2); |
945 |
|
946 |
bool is_signed = false; |
947 |
bool postindex = false; |
948 |
bool wback = false; |
949 |
|
950 |
TCGv_i64 tcg_addr; /* calculated address */
|
951 |
int size;
|
952 |
|
953 |
if (opc == 3) { |
954 |
unallocated_encoding(s); |
955 |
return;
|
956 |
} |
957 |
|
958 |
if (is_vector) {
|
959 |
size = 2 + opc;
|
960 |
} else {
|
961 |
size = 2 + extract32(opc, 1, 1); |
962 |
is_signed = extract32(opc, 0, 1); |
963 |
if (!is_load && is_signed) {
|
964 |
unallocated_encoding(s); |
965 |
return;
|
966 |
} |
967 |
} |
968 |
|
969 |
switch (index) {
|
970 |
case 1: /* post-index */ |
971 |
postindex = true;
|
972 |
wback = true;
|
973 |
break;
|
974 |
case 0: |
975 |
/* signed offset with "non-temporal" hint. Since we don't emulate
|
976 |
* caches we don't care about hints to the cache system about
|
977 |
* data access patterns, and handle this identically to plain
|
978 |
* signed offset.
|
979 |
*/
|
980 |
if (is_signed) {
|
981 |
/* There is no non-temporal-hint version of LDPSW */
|
982 |
unallocated_encoding(s); |
983 |
return;
|
984 |
} |
985 |
postindex = false;
|
986 |
break;
|
987 |
case 2: /* signed offset, rn not updated */ |
988 |
postindex = false;
|
989 |
break;
|
990 |
case 3: /* pre-index */ |
991 |
postindex = false;
|
992 |
wback = true;
|
993 |
break;
|
994 |
} |
995 |
|
996 |
offset <<= size; |
997 |
|
998 |
if (rn == 31) { |
999 |
gen_check_sp_alignment(s); |
1000 |
} |
1001 |
|
1002 |
tcg_addr = read_cpu_reg_sp(s, rn, 1);
|
1003 |
|
1004 |
if (!postindex) {
|
1005 |
tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); |
1006 |
} |
1007 |
|
1008 |
if (is_vector) {
|
1009 |
if (is_load) {
|
1010 |
do_fp_ld(s, rt, tcg_addr, size); |
1011 |
} else {
|
1012 |
do_fp_st(s, rt, tcg_addr, size); |
1013 |
} |
1014 |
} else {
|
1015 |
TCGv_i64 tcg_rt = cpu_reg(s, rt); |
1016 |
if (is_load) {
|
1017 |
do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false);
|
1018 |
} else {
|
1019 |
do_gpr_st(s, tcg_rt, tcg_addr, size); |
1020 |
} |
1021 |
} |
1022 |
tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
|
1023 |
if (is_vector) {
|
1024 |
if (is_load) {
|
1025 |
do_fp_ld(s, rt2, tcg_addr, size); |
1026 |
} else {
|
1027 |
do_fp_st(s, rt2, tcg_addr, size); |
1028 |
} |
1029 |
} else {
|
1030 |
TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); |
1031 |
if (is_load) {
|
1032 |
do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false);
|
1033 |
} else {
|
1034 |
do_gpr_st(s, tcg_rt2, tcg_addr, size); |
1035 |
} |
1036 |
} |
1037 |
|
1038 |
if (wback) {
|
1039 |
if (postindex) {
|
1040 |
tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size));
|
1041 |
} else {
|
1042 |
tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size);
|
1043 |
} |
1044 |
tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); |
1045 |
} |
1046 |
} |
1047 |
|
1048 |
/*
|
1049 |
* C3.3.8 Load/store (immediate post-indexed)
|
1050 |
* C3.3.9 Load/store (immediate pre-indexed)
|
1051 |
* C3.3.12 Load/store (unscaled immediate)
|
1052 |
*
|
1053 |
* 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
|
1054 |
* +----+-------+---+-----+-----+---+--------+-----+------+------+
|
1055 |
* |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
|
1056 |
* +----+-------+---+-----+-----+---+--------+-----+------+------+
|
1057 |
*
|
1058 |
* idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
|
1059 |
* V = 0 -> non-vector
|
1060 |
* size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
|
1061 |
* opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
|
1062 |
*/
|
1063 |
static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn) |
1064 |
{ |
1065 |
int rt = extract32(insn, 0, 5); |
1066 |
int rn = extract32(insn, 5, 5); |
1067 |
int imm9 = sextract32(insn, 12, 9); |
1068 |
int opc = extract32(insn, 22, 2); |
1069 |
int size = extract32(insn, 30, 2); |
1070 |
int idx = extract32(insn, 10, 2); |
1071 |
bool is_signed = false; |
1072 |
bool is_store = false; |
1073 |
bool is_extended = false; |
1074 |
bool is_vector = extract32(insn, 26, 1); |
1075 |
bool post_index;
|
1076 |
bool writeback;
|
1077 |
|
1078 |
TCGv_i64 tcg_addr; |
1079 |
|
1080 |
if (is_vector) {
|
1081 |
size |= (opc & 2) << 1; |
1082 |
if (size > 4) { |
1083 |
unallocated_encoding(s); |
1084 |
return;
|
1085 |
} |
1086 |
is_store = ((opc & 1) == 0); |
1087 |
} else {
|
1088 |
if (size == 3 && opc == 2) { |
1089 |
/* PRFM - prefetch */
|
1090 |
return;
|
1091 |
} |
1092 |
if (opc == 3 && size > 1) { |
1093 |
unallocated_encoding(s); |
1094 |
return;
|
1095 |
} |
1096 |
is_store = (opc == 0);
|
1097 |
is_signed = opc & (1<<1); |
1098 |
is_extended = (size < 3) && (opc & 1); |
1099 |
} |
1100 |
|
1101 |
switch (idx) {
|
1102 |
case 0: |
1103 |
post_index = false;
|
1104 |
writeback = false;
|
1105 |
break;
|
1106 |
case 1: |
1107 |
post_index = true;
|
1108 |
writeback = true;
|
1109 |
break;
|
1110 |
case 3: |
1111 |
post_index = false;
|
1112 |
writeback = true;
|
1113 |
break;
|
1114 |
case 2: |
1115 |
g_assert(false);
|
1116 |
break;
|
1117 |
} |
1118 |
|
1119 |
if (rn == 31) { |
1120 |
gen_check_sp_alignment(s); |
1121 |
} |
1122 |
tcg_addr = read_cpu_reg_sp(s, rn, 1);
|
1123 |
|
1124 |
if (!post_index) {
|
1125 |
tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); |
1126 |
} |
1127 |
|
1128 |
if (is_vector) {
|
1129 |
if (is_store) {
|
1130 |
do_fp_st(s, rt, tcg_addr, size); |
1131 |
} else {
|
1132 |
do_fp_ld(s, rt, tcg_addr, size); |
1133 |
} |
1134 |
} else {
|
1135 |
TCGv_i64 tcg_rt = cpu_reg(s, rt); |
1136 |
if (is_store) {
|
1137 |
do_gpr_st(s, tcg_rt, tcg_addr, size); |
1138 |
} else {
|
1139 |
do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended); |
1140 |
} |
1141 |
} |
1142 |
|
1143 |
if (writeback) {
|
1144 |
TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); |
1145 |
if (post_index) {
|
1146 |
tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); |
1147 |
} |
1148 |
tcg_gen_mov_i64(tcg_rn, tcg_addr); |
1149 |
} |
1150 |
} |
1151 |
|
1152 |
/*
|
1153 |
* C3.3.10 Load/store (register offset)
|
1154 |
*
|
1155 |
* 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
|
1156 |
* +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
|
1157 |
* |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
|
1158 |
* +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
|
1159 |
*
|
1160 |
* For non-vector:
|
1161 |
* size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
|
1162 |
* opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
|
1163 |
* For vector:
|
1164 |
* size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
|
1165 |
* opc<0>: 0 -> store, 1 -> load
|
1166 |
* V: 1 -> vector/simd
|
1167 |
* opt: extend encoding (see DecodeRegExtend)
|
1168 |
* S: if S=1 then scale (essentially index by sizeof(size))
|
1169 |
* Rt: register to transfer into/out of
|
1170 |
* Rn: address register or SP for base
|
1171 |
* Rm: offset register or ZR for offset
|
1172 |
*/
|
1173 |
static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn) |
1174 |
{ |
1175 |
int rt = extract32(insn, 0, 5); |
1176 |
int rn = extract32(insn, 5, 5); |
1177 |
int shift = extract32(insn, 12, 1); |
1178 |
int rm = extract32(insn, 16, 5); |
1179 |
int opc = extract32(insn, 22, 2); |
1180 |
int opt = extract32(insn, 13, 3); |
1181 |
int size = extract32(insn, 30, 2); |
1182 |
bool is_signed = false; |
1183 |
bool is_store = false; |
1184 |
bool is_extended = false; |
1185 |
bool is_vector = extract32(insn, 26, 1); |
1186 |
|
1187 |
TCGv_i64 tcg_rm; |
1188 |
TCGv_i64 tcg_addr; |
1189 |
|
1190 |
if (extract32(opt, 1, 1) == 0) { |
1191 |
unallocated_encoding(s); |
1192 |
return;
|
1193 |
} |
1194 |
|
1195 |
if (is_vector) {
|
1196 |
size |= (opc & 2) << 1; |
1197 |
if (size > 4) { |
1198 |
unallocated_encoding(s); |
1199 |
return;
|
1200 |
} |
1201 |
is_store = !extract32(opc, 0, 1); |
1202 |
} else {
|
1203 |
if (size == 3 && opc == 2) { |
1204 |
/* PRFM - prefetch */
|
1205 |
return;
|
1206 |
} |
1207 |
if (opc == 3 && size > 1) { |
1208 |
unallocated_encoding(s); |
1209 |
return;
|
1210 |
} |
1211 |
is_store = (opc == 0);
|
1212 |
is_signed = extract32(opc, 1, 1); |
1213 |
is_extended = (size < 3) && extract32(opc, 0, 1); |
1214 |
} |
1215 |
|
1216 |
if (rn == 31) { |
1217 |
gen_check_sp_alignment(s); |
1218 |
} |
1219 |
tcg_addr = read_cpu_reg_sp(s, rn, 1);
|
1220 |
|
1221 |
tcg_rm = read_cpu_reg(s, rm, 1);
|
1222 |
ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0);
|
1223 |
|
1224 |
tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm); |
1225 |
|
1226 |
if (is_vector) {
|
1227 |
if (is_store) {
|
1228 |
do_fp_st(s, rt, tcg_addr, size); |
1229 |
} else {
|
1230 |
do_fp_ld(s, rt, tcg_addr, size); |
1231 |
} |
1232 |
} else {
|
1233 |
TCGv_i64 tcg_rt = cpu_reg(s, rt); |
1234 |
if (is_store) {
|
1235 |
do_gpr_st(s, tcg_rt, tcg_addr, size); |
1236 |
} else {
|
1237 |
do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended); |
1238 |
} |
1239 |
} |
1240 |
} |
1241 |
|
1242 |
/*
|
1243 |
* C3.3.13 Load/store (unsigned immediate)
|
1244 |
*
|
1245 |
* 31 30 29 27 26 25 24 23 22 21 10 9 5
|
1246 |
* +----+-------+---+-----+-----+------------+-------+------+
|
1247 |
* |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
|
1248 |
* +----+-------+---+-----+-----+------------+-------+------+
|
1249 |
*
|
1250 |
* For non-vector:
|
1251 |
* size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
|
1252 |
* opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
|
1253 |
* For vector:
|
1254 |
* size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
|
1255 |
* opc<0>: 0 -> store, 1 -> load
|
1256 |
* Rn: base address register (inc SP)
|
1257 |
* Rt: target register
|
1258 |
*/
|
1259 |
static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn) |
1260 |
{ |
1261 |
int rt = extract32(insn, 0, 5); |
1262 |
int rn = extract32(insn, 5, 5); |
1263 |
unsigned int imm12 = extract32(insn, 10, 12); |
1264 |
bool is_vector = extract32(insn, 26, 1); |
1265 |
int size = extract32(insn, 30, 2); |
1266 |
int opc = extract32(insn, 22, 2); |
1267 |
unsigned int offset; |
1268 |
|
1269 |
TCGv_i64 tcg_addr; |
1270 |
|
1271 |
bool is_store;
|
1272 |
bool is_signed = false; |
1273 |
bool is_extended = false; |
1274 |
|
1275 |
if (is_vector) {
|
1276 |
size |= (opc & 2) << 1; |
1277 |
if (size > 4) { |
1278 |
unallocated_encoding(s); |
1279 |
return;
|
1280 |
} |
1281 |
is_store = !extract32(opc, 0, 1); |
1282 |
} else {
|
1283 |
if (size == 3 && opc == 2) { |
1284 |
/* PRFM - prefetch */
|
1285 |
return;
|
1286 |
} |
1287 |
if (opc == 3 && size > 1) { |
1288 |
unallocated_encoding(s); |
1289 |
return;
|
1290 |
} |
1291 |
is_store = (opc == 0);
|
1292 |
is_signed = extract32(opc, 1, 1); |
1293 |
is_extended = (size < 3) && extract32(opc, 0, 1); |
1294 |
} |
1295 |
|
1296 |
if (rn == 31) { |
1297 |
gen_check_sp_alignment(s); |
1298 |
} |
1299 |
tcg_addr = read_cpu_reg_sp(s, rn, 1);
|
1300 |
offset = imm12 << size; |
1301 |
tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); |
1302 |
|
1303 |
if (is_vector) {
|
1304 |
if (is_store) {
|
1305 |
do_fp_st(s, rt, tcg_addr, size); |
1306 |
} else {
|
1307 |
do_fp_ld(s, rt, tcg_addr, size); |
1308 |
} |
1309 |
} else {
|
1310 |
TCGv_i64 tcg_rt = cpu_reg(s, rt); |
1311 |
if (is_store) {
|
1312 |
do_gpr_st(s, tcg_rt, tcg_addr, size); |
1313 |
} else {
|
1314 |
do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended); |
1315 |
} |
1316 |
} |
1317 |
} |
1318 |
|
1319 |
/* Load/store register (immediate forms) */
|
1320 |
static void disas_ldst_reg_imm(DisasContext *s, uint32_t insn) |
1321 |
{ |
1322 |
switch (extract32(insn, 10, 2)) { |
1323 |
case 0: case 1: case 3: |
1324 |
/* Load/store register (unscaled immediate) */
|
1325 |
/* Load/store immediate pre/post-indexed */
|
1326 |
disas_ldst_reg_imm9(s, insn); |
1327 |
break;
|
1328 |
case 2: |
1329 |
/* Load/store register unprivileged */
|
1330 |
unsupported_encoding(s, insn); |
1331 |
break;
|
1332 |
default:
|
1333 |
unallocated_encoding(s); |
1334 |
break;
|
1335 |
} |
1336 |
} |
1337 |
|
1338 |
/* Load/store register (all forms) */
|
1339 |
static void disas_ldst_reg(DisasContext *s, uint32_t insn) |
1340 |
{ |
1341 |
switch (extract32(insn, 24, 2)) { |
1342 |
case 0: |
1343 |
if (extract32(insn, 21, 1) == 1 && extract32(insn, 10, 2) == 2) { |
1344 |
disas_ldst_reg_roffset(s, insn); |
1345 |
} else {
|
1346 |
disas_ldst_reg_imm(s, insn); |
1347 |
} |
1348 |
break;
|
1349 |
case 1: |
1350 |
disas_ldst_reg_unsigned_imm(s, insn); |
1351 |
break;
|
1352 |
default:
|
1353 |
unallocated_encoding(s); |
1354 |
break;
|
1355 |
} |
1356 |
} |
1357 |
|
1358 |
/* AdvSIMD load/store multiple structures */
|
1359 |
static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) |
1360 |
{ |
1361 |
unsupported_encoding(s, insn); |
1362 |
} |
1363 |
|
1364 |
/* AdvSIMD load/store single structure */
|
1365 |
static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
1366 |
{ |
1367 |
unsupported_encoding(s, insn); |
1368 |
} |
1369 |
|
1370 |
/* C3.3 Loads and stores */
|
1371 |
static void disas_ldst(DisasContext *s, uint32_t insn) |
1372 |
{ |
1373 |
switch (extract32(insn, 24, 6)) { |
1374 |
case 0x08: /* Load/store exclusive */ |
1375 |
disas_ldst_excl(s, insn); |
1376 |
break;
|
1377 |
case 0x18: case 0x1c: /* Load register (literal) */ |
1378 |
disas_ld_lit(s, insn); |
1379 |
break;
|
1380 |
case 0x28: case 0x29: |
1381 |
case 0x2c: case 0x2d: /* Load/store pair (all forms) */ |
1382 |
disas_ldst_pair(s, insn); |
1383 |
break;
|
1384 |
case 0x38: case 0x39: |
1385 |
case 0x3c: case 0x3d: /* Load/store register (all forms) */ |
1386 |
disas_ldst_reg(s, insn); |
1387 |
break;
|
1388 |
case 0x0c: /* AdvSIMD load/store multiple structures */ |
1389 |
disas_ldst_multiple_struct(s, insn); |
1390 |
break;
|
1391 |
case 0x0d: /* AdvSIMD load/store single structure */ |
1392 |
disas_ldst_single_struct(s, insn); |
1393 |
break;
|
1394 |
default:
|
1395 |
unallocated_encoding(s); |
1396 |
break;
|
1397 |
} |
1398 |
} |
1399 |
|
1400 |
/* C3.4.6 PC-rel. addressing
|
1401 |
* 31 30 29 28 24 23 5 4 0
|
1402 |
* +----+-------+-----------+-------------------+------+
|
1403 |
* | op | immlo | 1 0 0 0 0 | immhi | Rd |
|
1404 |
* +----+-------+-----------+-------------------+------+
|
1405 |
*/
|
1406 |
static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) |
1407 |
{ |
1408 |
unsigned int page, rd; |
1409 |
uint64_t base; |
1410 |
int64_t offset; |
1411 |
|
1412 |
page = extract32(insn, 31, 1); |
1413 |
/* SignExtend(immhi:immlo) -> offset */
|
1414 |
offset = ((int64_t)sextract32(insn, 5, 19) << 2) | extract32(insn, 29, 2); |
1415 |
rd = extract32(insn, 0, 5); |
1416 |
base = s->pc - 4;
|
1417 |
|
1418 |
if (page) {
|
1419 |
/* ADRP (page based) */
|
1420 |
base &= ~0xfff;
|
1421 |
offset <<= 12;
|
1422 |
} |
1423 |
|
1424 |
tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); |
1425 |
} |
1426 |
|
1427 |
/*
|
1428 |
* C3.4.1 Add/subtract (immediate)
|
1429 |
*
|
1430 |
* 31 30 29 28 24 23 22 21 10 9 5 4 0
|
1431 |
* +--+--+--+-----------+-----+-------------+-----+-----+
|
1432 |
* |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
|
1433 |
* +--+--+--+-----------+-----+-------------+-----+-----+
|
1434 |
*
|
1435 |
* sf: 0 -> 32bit, 1 -> 64bit
|
1436 |
* op: 0 -> add , 1 -> sub
|
1437 |
* S: 1 -> set flags
|
1438 |
* shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
|
1439 |
*/
|
1440 |
static void disas_add_sub_imm(DisasContext *s, uint32_t insn) |
1441 |
{ |
1442 |
int rd = extract32(insn, 0, 5); |
1443 |
int rn = extract32(insn, 5, 5); |
1444 |
uint64_t imm = extract32(insn, 10, 12); |
1445 |
int shift = extract32(insn, 22, 2); |
1446 |
bool setflags = extract32(insn, 29, 1); |
1447 |
bool sub_op = extract32(insn, 30, 1); |
1448 |
bool is_64bit = extract32(insn, 31, 1); |
1449 |
|
1450 |
TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); |
1451 |
TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); |
1452 |
TCGv_i64 tcg_result; |
1453 |
|
1454 |
switch (shift) {
|
1455 |
case 0x0: |
1456 |
break;
|
1457 |
case 0x1: |
1458 |
imm <<= 12;
|
1459 |
break;
|
1460 |
default:
|
1461 |
unallocated_encoding(s); |
1462 |
return;
|
1463 |
} |
1464 |
|
1465 |
tcg_result = tcg_temp_new_i64(); |
1466 |
if (!setflags) {
|
1467 |
if (sub_op) {
|
1468 |
tcg_gen_subi_i64(tcg_result, tcg_rn, imm); |
1469 |
} else {
|
1470 |
tcg_gen_addi_i64(tcg_result, tcg_rn, imm); |
1471 |
} |
1472 |
} else {
|
1473 |
TCGv_i64 tcg_imm = tcg_const_i64(imm); |
1474 |
if (sub_op) {
|
1475 |
gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); |
1476 |
} else {
|
1477 |
gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); |
1478 |
} |
1479 |
tcg_temp_free_i64(tcg_imm); |
1480 |
} |
1481 |
|
1482 |
if (is_64bit) {
|
1483 |
tcg_gen_mov_i64(tcg_rd, tcg_result); |
1484 |
} else {
|
1485 |
tcg_gen_ext32u_i64(tcg_rd, tcg_result); |
1486 |
} |
1487 |
|
1488 |
tcg_temp_free_i64(tcg_result); |
1489 |
} |
1490 |
|
1491 |
/* The input should be a value in the bottom e bits (with higher
|
1492 |
* bits zero); returns that value replicated into every element
|
1493 |
* of size e in a 64 bit integer.
|
1494 |
*/
|
1495 |
static uint64_t bitfield_replicate(uint64_t mask, unsigned int e) |
1496 |
{ |
1497 |
assert(e != 0);
|
1498 |
while (e < 64) { |
1499 |
mask |= mask << e; |
1500 |
e *= 2;
|
1501 |
} |
1502 |
return mask;
|
1503 |
} |
1504 |
|
1505 |
/* Return a value with the bottom len bits set (where 0 < len <= 64) */
|
1506 |
static inline uint64_t bitmask64(unsigned int length) |
1507 |
{ |
1508 |
assert(length > 0 && length <= 64); |
1509 |
return ~0ULL >> (64 - length); |
1510 |
} |
1511 |
|
1512 |
/* Simplified variant of pseudocode DecodeBitMasks() for the case where we
|
1513 |
* only require the wmask. Returns false if the imms/immr/immn are a reserved
|
1514 |
* value (ie should cause a guest UNDEF exception), and true if they are
|
1515 |
* valid, in which case the decoded bit pattern is written to result.
|
1516 |
*/
|
1517 |
static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, |
1518 |
unsigned int imms, unsigned int immr) |
1519 |
{ |
1520 |
uint64_t mask; |
1521 |
unsigned e, levels, s, r;
|
1522 |
int len;
|
1523 |
|
1524 |
assert(immn < 2 && imms < 64 && immr < 64); |
1525 |
|
1526 |
/* The bit patterns we create here are 64 bit patterns which
|
1527 |
* are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
|
1528 |
* 64 bits each. Each element contains the same value: a run
|
1529 |
* of between 1 and e-1 non-zero bits, rotated within the
|
1530 |
* element by between 0 and e-1 bits.
|
1531 |
*
|
1532 |
* The element size and run length are encoded into immn (1 bit)
|
1533 |
* and imms (6 bits) as follows:
|
1534 |
* 64 bit elements: immn = 1, imms = <length of run - 1>
|
1535 |
* 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
|
1536 |
* 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
|
1537 |
* 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
|
1538 |
* 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
|
1539 |
* 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
|
1540 |
* Notice that immn = 0, imms = 11111x is the only combination
|
1541 |
* not covered by one of the above options; this is reserved.
|
1542 |
* Further, <length of run - 1> all-ones is a reserved pattern.
|
1543 |
*
|
1544 |
* In all cases the rotation is by immr % e (and immr is 6 bits).
|
1545 |
*/
|
1546 |
|
1547 |
/* First determine the element size */
|
1548 |
len = 31 - clz32((immn << 6) | (~imms & 0x3f)); |
1549 |
if (len < 1) { |
1550 |
/* This is the immn == 0, imms == 0x11111x case */
|
1551 |
return false; |
1552 |
} |
1553 |
e = 1 << len;
|
1554 |
|
1555 |
levels = e - 1;
|
1556 |
s = imms & levels; |
1557 |
r = immr & levels; |
1558 |
|
1559 |
if (s == levels) {
|
1560 |
/* <length of run - 1> mustn't be all-ones. */
|
1561 |
return false; |
1562 |
} |
1563 |
|
1564 |
/* Create the value of one element: s+1 set bits rotated
|
1565 |
* by r within the element (which is e bits wide)...
|
1566 |
*/
|
1567 |
mask = bitmask64(s + 1);
|
1568 |
mask = (mask >> r) | (mask << (e - r)); |
1569 |
/* ...then replicate the element over the whole 64 bit value */
|
1570 |
mask = bitfield_replicate(mask, e); |
1571 |
*result = mask; |
1572 |
return true; |
1573 |
} |
1574 |
|
1575 |
/* C3.4.4 Logical (immediate)
|
1576 |
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
|
1577 |
* +----+-----+-------------+---+------+------+------+------+
|
1578 |
* | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
|
1579 |
* +----+-----+-------------+---+------+------+------+------+
|
1580 |
*/
|
1581 |
static void disas_logic_imm(DisasContext *s, uint32_t insn) |
1582 |
{ |
1583 |
unsigned int sf, opc, is_n, immr, imms, rn, rd; |
1584 |
TCGv_i64 tcg_rd, tcg_rn; |
1585 |
uint64_t wmask; |
1586 |
bool is_and = false; |
1587 |
|
1588 |
sf = extract32(insn, 31, 1); |
1589 |
opc = extract32(insn, 29, 2); |
1590 |
is_n = extract32(insn, 22, 1); |
1591 |
immr = extract32(insn, 16, 6); |
1592 |
imms = extract32(insn, 10, 6); |
1593 |
rn = extract32(insn, 5, 5); |
1594 |
rd = extract32(insn, 0, 5); |
1595 |
|
1596 |
if (!sf && is_n) {
|
1597 |
unallocated_encoding(s); |
1598 |
return;
|
1599 |
} |
1600 |
|
1601 |
if (opc == 0x3) { /* ANDS */ |
1602 |
tcg_rd = cpu_reg(s, rd); |
1603 |
} else {
|
1604 |
tcg_rd = cpu_reg_sp(s, rd); |
1605 |
} |
1606 |
tcg_rn = cpu_reg(s, rn); |
1607 |
|
1608 |
if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) {
|
1609 |
/* some immediate field values are reserved */
|
1610 |
unallocated_encoding(s); |
1611 |
return;
|
1612 |
} |
1613 |
|
1614 |
if (!sf) {
|
1615 |
wmask &= 0xffffffff;
|
1616 |
} |
1617 |
|
1618 |
switch (opc) {
|
1619 |
case 0x3: /* ANDS */ |
1620 |
case 0x0: /* AND */ |
1621 |
tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask); |
1622 |
is_and = true;
|
1623 |
break;
|
1624 |
case 0x1: /* ORR */ |
1625 |
tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask); |
1626 |
break;
|
1627 |
case 0x2: /* EOR */ |
1628 |
tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask); |
1629 |
break;
|
1630 |
default:
|
1631 |
assert(FALSE); /* must handle all above */
|
1632 |
break;
|
1633 |
} |
1634 |
|
1635 |
if (!sf && !is_and) {
|
1636 |
/* zero extend final result; we know we can skip this for AND
|
1637 |
* since the immediate had the high 32 bits clear.
|
1638 |
*/
|
1639 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
1640 |
} |
1641 |
|
1642 |
if (opc == 3) { /* ANDS */ |
1643 |
gen_logic_CC(sf, tcg_rd); |
1644 |
} |
1645 |
} |
1646 |
|
1647 |
/*
|
1648 |
* C3.4.5 Move wide (immediate)
|
1649 |
*
|
1650 |
* 31 30 29 28 23 22 21 20 5 4 0
|
1651 |
* +--+-----+-------------+-----+----------------+------+
|
1652 |
* |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
|
1653 |
* +--+-----+-------------+-----+----------------+------+
|
1654 |
*
|
1655 |
* sf: 0 -> 32 bit, 1 -> 64 bit
|
1656 |
* opc: 00 -> N, 10 -> Z, 11 -> K
|
1657 |
* hw: shift/16 (0,16, and sf only 32, 48)
|
1658 |
*/
|
1659 |
static void disas_movw_imm(DisasContext *s, uint32_t insn) |
1660 |
{ |
1661 |
int rd = extract32(insn, 0, 5); |
1662 |
uint64_t imm = extract32(insn, 5, 16); |
1663 |
int sf = extract32(insn, 31, 1); |
1664 |
int opc = extract32(insn, 29, 2); |
1665 |
int pos = extract32(insn, 21, 2) << 4; |
1666 |
TCGv_i64 tcg_rd = cpu_reg(s, rd); |
1667 |
TCGv_i64 tcg_imm; |
1668 |
|
1669 |
if (!sf && (pos >= 32)) { |
1670 |
unallocated_encoding(s); |
1671 |
return;
|
1672 |
} |
1673 |
|
1674 |
switch (opc) {
|
1675 |
case 0: /* MOVN */ |
1676 |
case 2: /* MOVZ */ |
1677 |
imm <<= pos; |
1678 |
if (opc == 0) { |
1679 |
imm = ~imm; |
1680 |
} |
1681 |
if (!sf) {
|
1682 |
imm &= 0xffffffffu;
|
1683 |
} |
1684 |
tcg_gen_movi_i64(tcg_rd, imm); |
1685 |
break;
|
1686 |
case 3: /* MOVK */ |
1687 |
tcg_imm = tcg_const_i64(imm); |
1688 |
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16);
|
1689 |
tcg_temp_free_i64(tcg_imm); |
1690 |
if (!sf) {
|
1691 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
1692 |
} |
1693 |
break;
|
1694 |
default:
|
1695 |
unallocated_encoding(s); |
1696 |
break;
|
1697 |
} |
1698 |
} |
1699 |
|
1700 |
/* C3.4.2 Bitfield
|
1701 |
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
|
1702 |
* +----+-----+-------------+---+------+------+------+------+
|
1703 |
* | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
|
1704 |
* +----+-----+-------------+---+------+------+------+------+
|
1705 |
*/
|
1706 |
static void disas_bitfield(DisasContext *s, uint32_t insn) |
1707 |
{ |
1708 |
unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len; |
1709 |
TCGv_i64 tcg_rd, tcg_tmp; |
1710 |
|
1711 |
sf = extract32(insn, 31, 1); |
1712 |
opc = extract32(insn, 29, 2); |
1713 |
n = extract32(insn, 22, 1); |
1714 |
ri = extract32(insn, 16, 6); |
1715 |
si = extract32(insn, 10, 6); |
1716 |
rn = extract32(insn, 5, 5); |
1717 |
rd = extract32(insn, 0, 5); |
1718 |
bitsize = sf ? 64 : 32; |
1719 |
|
1720 |
if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) { |
1721 |
unallocated_encoding(s); |
1722 |
return;
|
1723 |
} |
1724 |
|
1725 |
tcg_rd = cpu_reg(s, rd); |
1726 |
tcg_tmp = read_cpu_reg(s, rn, sf); |
1727 |
|
1728 |
/* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
|
1729 |
|
1730 |
if (opc != 1) { /* SBFM or UBFM */ |
1731 |
tcg_gen_movi_i64(tcg_rd, 0);
|
1732 |
} |
1733 |
|
1734 |
/* do the bit move operation */
|
1735 |
if (si >= ri) {
|
1736 |
/* Wd<s-r:0> = Wn<s:r> */
|
1737 |
tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri); |
1738 |
pos = 0;
|
1739 |
len = (si - ri) + 1;
|
1740 |
} else {
|
1741 |
/* Wd<32+s-r,32-r> = Wn<s:0> */
|
1742 |
pos = bitsize - ri; |
1743 |
len = si + 1;
|
1744 |
} |
1745 |
|
1746 |
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); |
1747 |
|
1748 |
if (opc == 0) { /* SBFM - sign extend the destination field */ |
1749 |
tcg_gen_shli_i64(tcg_rd, tcg_rd, 64 - (pos + len));
|
1750 |
tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len));
|
1751 |
} |
1752 |
|
1753 |
if (!sf) { /* zero extend final result */ |
1754 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
1755 |
} |
1756 |
} |
1757 |
|
1758 |
/* C3.4.3 Extract
|
1759 |
* 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
|
1760 |
* +----+------+-------------+---+----+------+--------+------+------+
|
1761 |
* | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
|
1762 |
* +----+------+-------------+---+----+------+--------+------+------+
|
1763 |
*/
|
1764 |
static void disas_extract(DisasContext *s, uint32_t insn) |
1765 |
{ |
1766 |
unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0; |
1767 |
|
1768 |
sf = extract32(insn, 31, 1); |
1769 |
n = extract32(insn, 22, 1); |
1770 |
rm = extract32(insn, 16, 5); |
1771 |
imm = extract32(insn, 10, 6); |
1772 |
rn = extract32(insn, 5, 5); |
1773 |
rd = extract32(insn, 0, 5); |
1774 |
op21 = extract32(insn, 29, 2); |
1775 |
op0 = extract32(insn, 21, 1); |
1776 |
bitsize = sf ? 64 : 32; |
1777 |
|
1778 |
if (sf != n || op21 || op0 || imm >= bitsize) {
|
1779 |
unallocated_encoding(s); |
1780 |
} else {
|
1781 |
TCGv_i64 tcg_rd, tcg_rm, tcg_rn; |
1782 |
|
1783 |
tcg_rd = cpu_reg(s, rd); |
1784 |
|
1785 |
if (imm) {
|
1786 |
/* OPTME: we can special case rm==rn as a rotate */
|
1787 |
tcg_rm = read_cpu_reg(s, rm, sf); |
1788 |
tcg_rn = read_cpu_reg(s, rn, sf); |
1789 |
tcg_gen_shri_i64(tcg_rm, tcg_rm, imm); |
1790 |
tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm); |
1791 |
tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn); |
1792 |
if (!sf) {
|
1793 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
1794 |
} |
1795 |
} else {
|
1796 |
/* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
|
1797 |
* so an extract from bit 0 is a special case.
|
1798 |
*/
|
1799 |
if (sf) {
|
1800 |
tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm)); |
1801 |
} else {
|
1802 |
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); |
1803 |
} |
1804 |
} |
1805 |
|
1806 |
} |
1807 |
} |
1808 |
|
1809 |
/* C3.4 Data processing - immediate */
|
1810 |
static void disas_data_proc_imm(DisasContext *s, uint32_t insn) |
1811 |
{ |
1812 |
switch (extract32(insn, 23, 6)) { |
1813 |
case 0x20: case 0x21: /* PC-rel. addressing */ |
1814 |
disas_pc_rel_adr(s, insn); |
1815 |
break;
|
1816 |
case 0x22: case 0x23: /* Add/subtract (immediate) */ |
1817 |
disas_add_sub_imm(s, insn); |
1818 |
break;
|
1819 |
case 0x24: /* Logical (immediate) */ |
1820 |
disas_logic_imm(s, insn); |
1821 |
break;
|
1822 |
case 0x25: /* Move wide (immediate) */ |
1823 |
disas_movw_imm(s, insn); |
1824 |
break;
|
1825 |
case 0x26: /* Bitfield */ |
1826 |
disas_bitfield(s, insn); |
1827 |
break;
|
1828 |
case 0x27: /* Extract */ |
1829 |
disas_extract(s, insn); |
1830 |
break;
|
1831 |
default:
|
1832 |
unallocated_encoding(s); |
1833 |
break;
|
1834 |
} |
1835 |
} |
1836 |
|
1837 |
/* Shift a TCGv src by TCGv shift_amount, put result in dst.
|
1838 |
* Note that it is the caller's responsibility to ensure that the
|
1839 |
* shift amount is in range (ie 0..31 or 0..63) and provide the ARM
|
1840 |
* mandated semantics for out of range shifts.
|
1841 |
*/
|
1842 |
static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf, |
1843 |
enum a64_shift_type shift_type, TCGv_i64 shift_amount)
|
1844 |
{ |
1845 |
switch (shift_type) {
|
1846 |
case A64_SHIFT_TYPE_LSL:
|
1847 |
tcg_gen_shl_i64(dst, src, shift_amount); |
1848 |
break;
|
1849 |
case A64_SHIFT_TYPE_LSR:
|
1850 |
tcg_gen_shr_i64(dst, src, shift_amount); |
1851 |
break;
|
1852 |
case A64_SHIFT_TYPE_ASR:
|
1853 |
if (!sf) {
|
1854 |
tcg_gen_ext32s_i64(dst, src); |
1855 |
} |
1856 |
tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount); |
1857 |
break;
|
1858 |
case A64_SHIFT_TYPE_ROR:
|
1859 |
if (sf) {
|
1860 |
tcg_gen_rotr_i64(dst, src, shift_amount); |
1861 |
} else {
|
1862 |
TCGv_i32 t0, t1; |
1863 |
t0 = tcg_temp_new_i32(); |
1864 |
t1 = tcg_temp_new_i32(); |
1865 |
tcg_gen_trunc_i64_i32(t0, src); |
1866 |
tcg_gen_trunc_i64_i32(t1, shift_amount); |
1867 |
tcg_gen_rotr_i32(t0, t0, t1); |
1868 |
tcg_gen_extu_i32_i64(dst, t0); |
1869 |
tcg_temp_free_i32(t0); |
1870 |
tcg_temp_free_i32(t1); |
1871 |
} |
1872 |
break;
|
1873 |
default:
|
1874 |
assert(FALSE); /* all shift types should be handled */
|
1875 |
break;
|
1876 |
} |
1877 |
|
1878 |
if (!sf) { /* zero extend final result */ |
1879 |
tcg_gen_ext32u_i64(dst, dst); |
1880 |
} |
1881 |
} |
1882 |
|
1883 |
/* Shift a TCGv src by immediate, put result in dst.
|
1884 |
* The shift amount must be in range (this should always be true as the
|
1885 |
* relevant instructions will UNDEF on bad shift immediates).
|
1886 |
*/
|
1887 |
static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf, |
1888 |
enum a64_shift_type shift_type, unsigned int shift_i) |
1889 |
{ |
1890 |
assert(shift_i < (sf ? 64 : 32)); |
1891 |
|
1892 |
if (shift_i == 0) { |
1893 |
tcg_gen_mov_i64(dst, src); |
1894 |
} else {
|
1895 |
TCGv_i64 shift_const; |
1896 |
|
1897 |
shift_const = tcg_const_i64(shift_i); |
1898 |
shift_reg(dst, src, sf, shift_type, shift_const); |
1899 |
tcg_temp_free_i64(shift_const); |
1900 |
} |
1901 |
} |
1902 |
|
1903 |
/* C3.5.10 Logical (shifted register)
|
1904 |
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
|
1905 |
* +----+-----+-----------+-------+---+------+--------+------+------+
|
1906 |
* | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
|
1907 |
* +----+-----+-----------+-------+---+------+--------+------+------+
|
1908 |
*/
|
1909 |
static void disas_logic_reg(DisasContext *s, uint32_t insn) |
1910 |
{ |
1911 |
TCGv_i64 tcg_rd, tcg_rn, tcg_rm; |
1912 |
unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd; |
1913 |
|
1914 |
sf = extract32(insn, 31, 1); |
1915 |
opc = extract32(insn, 29, 2); |
1916 |
shift_type = extract32(insn, 22, 2); |
1917 |
invert = extract32(insn, 21, 1); |
1918 |
rm = extract32(insn, 16, 5); |
1919 |
shift_amount = extract32(insn, 10, 6); |
1920 |
rn = extract32(insn, 5, 5); |
1921 |
rd = extract32(insn, 0, 5); |
1922 |
|
1923 |
if (!sf && (shift_amount & (1 << 5))) { |
1924 |
unallocated_encoding(s); |
1925 |
return;
|
1926 |
} |
1927 |
|
1928 |
tcg_rd = cpu_reg(s, rd); |
1929 |
|
1930 |
if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) { |
1931 |
/* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
|
1932 |
* register-register MOV and MVN, so it is worth special casing.
|
1933 |
*/
|
1934 |
tcg_rm = cpu_reg(s, rm); |
1935 |
if (invert) {
|
1936 |
tcg_gen_not_i64(tcg_rd, tcg_rm); |
1937 |
if (!sf) {
|
1938 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
1939 |
} |
1940 |
} else {
|
1941 |
if (sf) {
|
1942 |
tcg_gen_mov_i64(tcg_rd, tcg_rm); |
1943 |
} else {
|
1944 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rm); |
1945 |
} |
1946 |
} |
1947 |
return;
|
1948 |
} |
1949 |
|
1950 |
tcg_rm = read_cpu_reg(s, rm, sf); |
1951 |
|
1952 |
if (shift_amount) {
|
1953 |
shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount); |
1954 |
} |
1955 |
|
1956 |
tcg_rn = cpu_reg(s, rn); |
1957 |
|
1958 |
switch (opc | (invert << 2)) { |
1959 |
case 0: /* AND */ |
1960 |
case 3: /* ANDS */ |
1961 |
tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm); |
1962 |
break;
|
1963 |
case 1: /* ORR */ |
1964 |
tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm); |
1965 |
break;
|
1966 |
case 2: /* EOR */ |
1967 |
tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm); |
1968 |
break;
|
1969 |
case 4: /* BIC */ |
1970 |
case 7: /* BICS */ |
1971 |
tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm); |
1972 |
break;
|
1973 |
case 5: /* ORN */ |
1974 |
tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm); |
1975 |
break;
|
1976 |
case 6: /* EON */ |
1977 |
tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm); |
1978 |
break;
|
1979 |
default:
|
1980 |
assert(FALSE); |
1981 |
break;
|
1982 |
} |
1983 |
|
1984 |
if (!sf) {
|
1985 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
1986 |
} |
1987 |
|
1988 |
if (opc == 3) { |
1989 |
gen_logic_CC(sf, tcg_rd); |
1990 |
} |
1991 |
} |
1992 |
|
1993 |
/*
|
1994 |
* C3.5.1 Add/subtract (extended register)
|
1995 |
*
|
1996 |
* 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
|
1997 |
* +--+--+--+-----------+-----+--+-------+------+------+----+----+
|
1998 |
* |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
|
1999 |
* +--+--+--+-----------+-----+--+-------+------+------+----+----+
|
2000 |
*
|
2001 |
* sf: 0 -> 32bit, 1 -> 64bit
|
2002 |
* op: 0 -> add , 1 -> sub
|
2003 |
* S: 1 -> set flags
|
2004 |
* opt: 00
|
2005 |
* option: extension type (see DecodeRegExtend)
|
2006 |
* imm3: optional shift to Rm
|
2007 |
*
|
2008 |
* Rd = Rn + LSL(extend(Rm), amount)
|
2009 |
*/
|
2010 |
static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn) |
2011 |
{ |
2012 |
int rd = extract32(insn, 0, 5); |
2013 |
int rn = extract32(insn, 5, 5); |
2014 |
int imm3 = extract32(insn, 10, 3); |
2015 |
int option = extract32(insn, 13, 3); |
2016 |
int rm = extract32(insn, 16, 5); |
2017 |
bool setflags = extract32(insn, 29, 1); |
2018 |
bool sub_op = extract32(insn, 30, 1); |
2019 |
bool sf = extract32(insn, 31, 1); |
2020 |
|
2021 |
TCGv_i64 tcg_rm, tcg_rn; /* temps */
|
2022 |
TCGv_i64 tcg_rd; |
2023 |
TCGv_i64 tcg_result; |
2024 |
|
2025 |
if (imm3 > 4) { |
2026 |
unallocated_encoding(s); |
2027 |
return;
|
2028 |
} |
2029 |
|
2030 |
/* non-flag setting ops may use SP */
|
2031 |
if (!setflags) {
|
2032 |
tcg_rn = read_cpu_reg_sp(s, rn, sf); |
2033 |
tcg_rd = cpu_reg_sp(s, rd); |
2034 |
} else {
|
2035 |
tcg_rn = read_cpu_reg(s, rn, sf); |
2036 |
tcg_rd = cpu_reg(s, rd); |
2037 |
} |
2038 |
|
2039 |
tcg_rm = read_cpu_reg(s, rm, sf); |
2040 |
ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3); |
2041 |
|
2042 |
tcg_result = tcg_temp_new_i64(); |
2043 |
|
2044 |
if (!setflags) {
|
2045 |
if (sub_op) {
|
2046 |
tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); |
2047 |
} else {
|
2048 |
tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); |
2049 |
} |
2050 |
} else {
|
2051 |
if (sub_op) {
|
2052 |
gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); |
2053 |
} else {
|
2054 |
gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); |
2055 |
} |
2056 |
} |
2057 |
|
2058 |
if (sf) {
|
2059 |
tcg_gen_mov_i64(tcg_rd, tcg_result); |
2060 |
} else {
|
2061 |
tcg_gen_ext32u_i64(tcg_rd, tcg_result); |
2062 |
} |
2063 |
|
2064 |
tcg_temp_free_i64(tcg_result); |
2065 |
} |
2066 |
|
2067 |
/*
|
2068 |
* C3.5.2 Add/subtract (shifted register)
|
2069 |
*
|
2070 |
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
|
2071 |
* +--+--+--+-----------+-----+--+-------+---------+------+------+
|
2072 |
* |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
|
2073 |
* +--+--+--+-----------+-----+--+-------+---------+------+------+
|
2074 |
*
|
2075 |
* sf: 0 -> 32bit, 1 -> 64bit
|
2076 |
* op: 0 -> add , 1 -> sub
|
2077 |
* S: 1 -> set flags
|
2078 |
* shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
|
2079 |
* imm6: Shift amount to apply to Rm before the add/sub
|
2080 |
*/
|
2081 |
static void disas_add_sub_reg(DisasContext *s, uint32_t insn) |
2082 |
{ |
2083 |
int rd = extract32(insn, 0, 5); |
2084 |
int rn = extract32(insn, 5, 5); |
2085 |
int imm6 = extract32(insn, 10, 6); |
2086 |
int rm = extract32(insn, 16, 5); |
2087 |
int shift_type = extract32(insn, 22, 2); |
2088 |
bool setflags = extract32(insn, 29, 1); |
2089 |
bool sub_op = extract32(insn, 30, 1); |
2090 |
bool sf = extract32(insn, 31, 1); |
2091 |
|
2092 |
TCGv_i64 tcg_rd = cpu_reg(s, rd); |
2093 |
TCGv_i64 tcg_rn, tcg_rm; |
2094 |
TCGv_i64 tcg_result; |
2095 |
|
2096 |
if ((shift_type == 3) || (!sf && (imm6 > 31))) { |
2097 |
unallocated_encoding(s); |
2098 |
return;
|
2099 |
} |
2100 |
|
2101 |
tcg_rn = read_cpu_reg(s, rn, sf); |
2102 |
tcg_rm = read_cpu_reg(s, rm, sf); |
2103 |
|
2104 |
shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6); |
2105 |
|
2106 |
tcg_result = tcg_temp_new_i64(); |
2107 |
|
2108 |
if (!setflags) {
|
2109 |
if (sub_op) {
|
2110 |
tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); |
2111 |
} else {
|
2112 |
tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); |
2113 |
} |
2114 |
} else {
|
2115 |
if (sub_op) {
|
2116 |
gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); |
2117 |
} else {
|
2118 |
gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); |
2119 |
} |
2120 |
} |
2121 |
|
2122 |
if (sf) {
|
2123 |
tcg_gen_mov_i64(tcg_rd, tcg_result); |
2124 |
} else {
|
2125 |
tcg_gen_ext32u_i64(tcg_rd, tcg_result); |
2126 |
} |
2127 |
|
2128 |
tcg_temp_free_i64(tcg_result); |
2129 |
} |
2130 |
|
2131 |
/* C3.5.9 Data-processing (3 source)
|
2132 |
|
2133 |
31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
|
2134 |
+--+------+-----------+------+------+----+------+------+------+
|
2135 |
|sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
|
2136 |
+--+------+-----------+------+------+----+------+------+------+
|
2137 |
|
2138 |
*/
|
2139 |
static void disas_data_proc_3src(DisasContext *s, uint32_t insn) |
2140 |
{ |
2141 |
int rd = extract32(insn, 0, 5); |
2142 |
int rn = extract32(insn, 5, 5); |
2143 |
int ra = extract32(insn, 10, 5); |
2144 |
int rm = extract32(insn, 16, 5); |
2145 |
int op_id = (extract32(insn, 29, 3) << 4) | |
2146 |
(extract32(insn, 21, 3) << 1) | |
2147 |
extract32(insn, 15, 1); |
2148 |
bool sf = extract32(insn, 31, 1); |
2149 |
bool is_sub = extract32(op_id, 0, 1); |
2150 |
bool is_high = extract32(op_id, 2, 1); |
2151 |
bool is_signed = false; |
2152 |
TCGv_i64 tcg_op1; |
2153 |
TCGv_i64 tcg_op2; |
2154 |
TCGv_i64 tcg_tmp; |
2155 |
|
2156 |
/* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
|
2157 |
switch (op_id) {
|
2158 |
case 0x42: /* SMADDL */ |
2159 |
case 0x43: /* SMSUBL */ |
2160 |
case 0x44: /* SMULH */ |
2161 |
is_signed = true;
|
2162 |
break;
|
2163 |
case 0x0: /* MADD (32bit) */ |
2164 |
case 0x1: /* MSUB (32bit) */ |
2165 |
case 0x40: /* MADD (64bit) */ |
2166 |
case 0x41: /* MSUB (64bit) */ |
2167 |
case 0x4a: /* UMADDL */ |
2168 |
case 0x4b: /* UMSUBL */ |
2169 |
case 0x4c: /* UMULH */ |
2170 |
break;
|
2171 |
default:
|
2172 |
unallocated_encoding(s); |
2173 |
return;
|
2174 |
} |
2175 |
|
2176 |
if (is_high) {
|
2177 |
TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */
|
2178 |
TCGv_i64 tcg_rd = cpu_reg(s, rd); |
2179 |
TCGv_i64 tcg_rn = cpu_reg(s, rn); |
2180 |
TCGv_i64 tcg_rm = cpu_reg(s, rm); |
2181 |
|
2182 |
if (is_signed) {
|
2183 |
tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); |
2184 |
} else {
|
2185 |
tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); |
2186 |
} |
2187 |
|
2188 |
tcg_temp_free_i64(low_bits); |
2189 |
return;
|
2190 |
} |
2191 |
|
2192 |
tcg_op1 = tcg_temp_new_i64(); |
2193 |
tcg_op2 = tcg_temp_new_i64(); |
2194 |
tcg_tmp = tcg_temp_new_i64(); |
2195 |
|
2196 |
if (op_id < 0x42) { |
2197 |
tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn)); |
2198 |
tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm)); |
2199 |
} else {
|
2200 |
if (is_signed) {
|
2201 |
tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn)); |
2202 |
tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm)); |
2203 |
} else {
|
2204 |
tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn)); |
2205 |
tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm)); |
2206 |
} |
2207 |
} |
2208 |
|
2209 |
if (ra == 31 && !is_sub) { |
2210 |
/* Special-case MADD with rA == XZR; it is the standard MUL alias */
|
2211 |
tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2); |
2212 |
} else {
|
2213 |
tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2); |
2214 |
if (is_sub) {
|
2215 |
tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); |
2216 |
} else {
|
2217 |
tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); |
2218 |
} |
2219 |
} |
2220 |
|
2221 |
if (!sf) {
|
2222 |
tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd)); |
2223 |
} |
2224 |
|
2225 |
tcg_temp_free_i64(tcg_op1); |
2226 |
tcg_temp_free_i64(tcg_op2); |
2227 |
tcg_temp_free_i64(tcg_tmp); |
2228 |
} |
2229 |
|
2230 |
/* Add/subtract (with carry) */
|
2231 |
static void disas_adc_sbc(DisasContext *s, uint32_t insn) |
2232 |
{ |
2233 |
unsupported_encoding(s, insn); |
2234 |
} |
2235 |
|
2236 |
/* Conditional compare (immediate) */
|
2237 |
static void disas_cc_imm(DisasContext *s, uint32_t insn) |
2238 |
{ |
2239 |
unsupported_encoding(s, insn); |
2240 |
} |
2241 |
|
2242 |
/* Conditional compare (register) */
|
2243 |
static void disas_cc_reg(DisasContext *s, uint32_t insn) |
2244 |
{ |
2245 |
unsupported_encoding(s, insn); |
2246 |
} |
2247 |
|
2248 |
/* C3.5.6 Conditional select
|
2249 |
* 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
|
2250 |
* +----+----+---+-----------------+------+------+-----+------+------+
|
2251 |
* | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
|
2252 |
* +----+----+---+-----------------+------+------+-----+------+------+
|
2253 |
*/
|
2254 |
static void disas_cond_select(DisasContext *s, uint32_t insn) |
2255 |
{ |
2256 |
unsigned int sf, else_inv, rm, cond, else_inc, rn, rd; |
2257 |
TCGv_i64 tcg_rd, tcg_src; |
2258 |
|
2259 |
if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) { |
2260 |
/* S == 1 or op2<1> == 1 */
|
2261 |
unallocated_encoding(s); |
2262 |
return;
|
2263 |
} |
2264 |
sf = extract32(insn, 31, 1); |
2265 |
else_inv = extract32(insn, 30, 1); |
2266 |
rm = extract32(insn, 16, 5); |
2267 |
cond = extract32(insn, 12, 4); |
2268 |
else_inc = extract32(insn, 10, 1); |
2269 |
rn = extract32(insn, 5, 5); |
2270 |
rd = extract32(insn, 0, 5); |
2271 |
|
2272 |
if (rd == 31) { |
2273 |
/* silly no-op write; until we use movcond we must special-case
|
2274 |
* this to avoid a dead temporary across basic blocks.
|
2275 |
*/
|
2276 |
return;
|
2277 |
} |
2278 |
|
2279 |
tcg_rd = cpu_reg(s, rd); |
2280 |
|
2281 |
if (cond >= 0x0e) { /* condition "always" */ |
2282 |
tcg_src = read_cpu_reg(s, rn, sf); |
2283 |
tcg_gen_mov_i64(tcg_rd, tcg_src); |
2284 |
} else {
|
2285 |
/* OPTME: we could use movcond here, at the cost of duplicating
|
2286 |
* a lot of the arm_gen_test_cc() logic.
|
2287 |
*/
|
2288 |
int label_match = gen_new_label();
|
2289 |
int label_continue = gen_new_label();
|
2290 |
|
2291 |
arm_gen_test_cc(cond, label_match); |
2292 |
/* nomatch: */
|
2293 |
tcg_src = cpu_reg(s, rm); |
2294 |
|
2295 |
if (else_inv && else_inc) {
|
2296 |
tcg_gen_neg_i64(tcg_rd, tcg_src); |
2297 |
} else if (else_inv) { |
2298 |
tcg_gen_not_i64(tcg_rd, tcg_src); |
2299 |
} else if (else_inc) { |
2300 |
tcg_gen_addi_i64(tcg_rd, tcg_src, 1);
|
2301 |
} else {
|
2302 |
tcg_gen_mov_i64(tcg_rd, tcg_src); |
2303 |
} |
2304 |
if (!sf) {
|
2305 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
2306 |
} |
2307 |
tcg_gen_br(label_continue); |
2308 |
/* match: */
|
2309 |
gen_set_label(label_match); |
2310 |
tcg_src = read_cpu_reg(s, rn, sf); |
2311 |
tcg_gen_mov_i64(tcg_rd, tcg_src); |
2312 |
/* continue: */
|
2313 |
gen_set_label(label_continue); |
2314 |
} |
2315 |
} |
2316 |
|
2317 |
static void handle_clz(DisasContext *s, unsigned int sf, |
2318 |
unsigned int rn, unsigned int rd) |
2319 |
{ |
2320 |
TCGv_i64 tcg_rd, tcg_rn; |
2321 |
tcg_rd = cpu_reg(s, rd); |
2322 |
tcg_rn = cpu_reg(s, rn); |
2323 |
|
2324 |
if (sf) {
|
2325 |
gen_helper_clz64(tcg_rd, tcg_rn); |
2326 |
} else {
|
2327 |
TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); |
2328 |
tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); |
2329 |
gen_helper_clz(tcg_tmp32, tcg_tmp32); |
2330 |
tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
2331 |
tcg_temp_free_i32(tcg_tmp32); |
2332 |
} |
2333 |
} |
2334 |
|
2335 |
static void handle_cls(DisasContext *s, unsigned int sf, |
2336 |
unsigned int rn, unsigned int rd) |
2337 |
{ |
2338 |
TCGv_i64 tcg_rd, tcg_rn; |
2339 |
tcg_rd = cpu_reg(s, rd); |
2340 |
tcg_rn = cpu_reg(s, rn); |
2341 |
|
2342 |
if (sf) {
|
2343 |
gen_helper_cls64(tcg_rd, tcg_rn); |
2344 |
} else {
|
2345 |
TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); |
2346 |
tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); |
2347 |
gen_helper_cls32(tcg_tmp32, tcg_tmp32); |
2348 |
tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
2349 |
tcg_temp_free_i32(tcg_tmp32); |
2350 |
} |
2351 |
} |
2352 |
|
2353 |
static void handle_rbit(DisasContext *s, unsigned int sf, |
2354 |
unsigned int rn, unsigned int rd) |
2355 |
{ |
2356 |
TCGv_i64 tcg_rd, tcg_rn; |
2357 |
tcg_rd = cpu_reg(s, rd); |
2358 |
tcg_rn = cpu_reg(s, rn); |
2359 |
|
2360 |
if (sf) {
|
2361 |
gen_helper_rbit64(tcg_rd, tcg_rn); |
2362 |
} else {
|
2363 |
TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); |
2364 |
tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); |
2365 |
gen_helper_rbit(tcg_tmp32, tcg_tmp32); |
2366 |
tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); |
2367 |
tcg_temp_free_i32(tcg_tmp32); |
2368 |
} |
2369 |
} |
2370 |
|
2371 |
/* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
|
2372 |
static void handle_rev64(DisasContext *s, unsigned int sf, |
2373 |
unsigned int rn, unsigned int rd) |
2374 |
{ |
2375 |
if (!sf) {
|
2376 |
unallocated_encoding(s); |
2377 |
return;
|
2378 |
} |
2379 |
tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn)); |
2380 |
} |
2381 |
|
2382 |
/* C5.6.149 REV with sf==0, opcode==2
|
2383 |
* C5.6.151 REV32 (sf==1, opcode==2)
|
2384 |
*/
|
2385 |
static void handle_rev32(DisasContext *s, unsigned int sf, |
2386 |
unsigned int rn, unsigned int rd) |
2387 |
{ |
2388 |
TCGv_i64 tcg_rd = cpu_reg(s, rd); |
2389 |
|
2390 |
if (sf) {
|
2391 |
TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
2392 |
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); |
2393 |
|
2394 |
/* bswap32_i64 requires zero high word */
|
2395 |
tcg_gen_ext32u_i64(tcg_tmp, tcg_rn); |
2396 |
tcg_gen_bswap32_i64(tcg_rd, tcg_tmp); |
2397 |
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
|
2398 |
tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); |
2399 |
tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp); |
2400 |
|
2401 |
tcg_temp_free_i64(tcg_tmp); |
2402 |
} else {
|
2403 |
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn)); |
2404 |
tcg_gen_bswap32_i64(tcg_rd, tcg_rd); |
2405 |
} |
2406 |
} |
2407 |
|
2408 |
/* C5.6.150 REV16 (opcode==1) */
|
2409 |
static void handle_rev16(DisasContext *s, unsigned int sf, |
2410 |
unsigned int rn, unsigned int rd) |
2411 |
{ |
2412 |
TCGv_i64 tcg_rd = cpu_reg(s, rd); |
2413 |
TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
2414 |
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); |
2415 |
|
2416 |
tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff);
|
2417 |
tcg_gen_bswap16_i64(tcg_rd, tcg_tmp); |
2418 |
|
2419 |
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16);
|
2420 |
tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
|
2421 |
tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); |
2422 |
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16); |
2423 |
|
2424 |
if (sf) {
|
2425 |
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
|
2426 |
tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
|
2427 |
tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); |
2428 |
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16); |
2429 |
|
2430 |
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 48);
|
2431 |
tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); |
2432 |
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 48, 16); |
2433 |
} |
2434 |
|
2435 |
tcg_temp_free_i64(tcg_tmp); |
2436 |
} |
2437 |
|
2438 |
/* C3.5.7 Data-processing (1 source)
|
2439 |
* 31 30 29 28 21 20 16 15 10 9 5 4 0
|
2440 |
* +----+---+---+-----------------+---------+--------+------+------+
|
2441 |
* | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
|
2442 |
* +----+---+---+-----------------+---------+--------+------+------+
|
2443 |
*/
|
2444 |
static void disas_data_proc_1src(DisasContext *s, uint32_t insn) |
2445 |
{ |
2446 |
unsigned int sf, opcode, rn, rd; |
2447 |
|
2448 |
if (extract32(insn, 29, 1) || extract32(insn, 16, 5)) { |
2449 |
unallocated_encoding(s); |
2450 |
return;
|
2451 |
} |
2452 |
|
2453 |
sf = extract32(insn, 31, 1); |
2454 |
opcode = extract32(insn, 10, 6); |
2455 |
rn = extract32(insn, 5, 5); |
2456 |
rd = extract32(insn, 0, 5); |
2457 |
|
2458 |
switch (opcode) {
|
2459 |
case 0: /* RBIT */ |
2460 |
handle_rbit(s, sf, rn, rd); |
2461 |
break;
|
2462 |
case 1: /* REV16 */ |
2463 |
handle_rev16(s, sf, rn, rd); |
2464 |
break;
|
2465 |
case 2: /* REV32 */ |
2466 |
handle_rev32(s, sf, rn, rd); |
2467 |
break;
|
2468 |
case 3: /* REV64 */ |
2469 |
handle_rev64(s, sf, rn, rd); |
2470 |
break;
|
2471 |
case 4: /* CLZ */ |
2472 |
handle_clz(s, sf, rn, rd); |
2473 |
break;
|
2474 |
case 5: /* CLS */ |
2475 |
handle_cls(s, sf, rn, rd); |
2476 |
break;
|
2477 |
} |
2478 |
} |
2479 |
|
2480 |
static void handle_div(DisasContext *s, bool is_signed, unsigned int sf, |
2481 |
unsigned int rm, unsigned int rn, unsigned int rd) |
2482 |
{ |
2483 |
TCGv_i64 tcg_n, tcg_m, tcg_rd; |
2484 |
tcg_rd = cpu_reg(s, rd); |
2485 |
|
2486 |
if (!sf && is_signed) {
|
2487 |
tcg_n = new_tmp_a64(s); |
2488 |
tcg_m = new_tmp_a64(s); |
2489 |
tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn)); |
2490 |
tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm)); |
2491 |
} else {
|
2492 |
tcg_n = read_cpu_reg(s, rn, sf); |
2493 |
tcg_m = read_cpu_reg(s, rm, sf); |
2494 |
} |
2495 |
|
2496 |
if (is_signed) {
|
2497 |
gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m); |
2498 |
} else {
|
2499 |
gen_helper_udiv64(tcg_rd, tcg_n, tcg_m); |
2500 |
} |
2501 |
|
2502 |
if (!sf) { /* zero extend final result */ |
2503 |
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); |
2504 |
} |
2505 |
} |
2506 |
|
2507 |
/* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
|
2508 |
static void handle_shift_reg(DisasContext *s, |
2509 |
enum a64_shift_type shift_type, unsigned int sf, |
2510 |
unsigned int rm, unsigned int rn, unsigned int rd) |
2511 |
{ |
2512 |
TCGv_i64 tcg_shift = tcg_temp_new_i64(); |
2513 |
TCGv_i64 tcg_rd = cpu_reg(s, rd); |
2514 |
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); |
2515 |
|
2516 |
tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31); |
2517 |
shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift); |
2518 |
tcg_temp_free_i64(tcg_shift); |
2519 |
} |
2520 |
|
2521 |
/* C3.5.8 Data-processing (2 source)
|
2522 |
* 31 30 29 28 21 20 16 15 10 9 5 4 0
|
2523 |
* +----+---+---+-----------------+------+--------+------+------+
|
2524 |
* | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
|
2525 |
* +----+---+---+-----------------+------+--------+------+------+
|
2526 |
*/
|
2527 |
static void disas_data_proc_2src(DisasContext *s, uint32_t insn) |
2528 |
{ |
2529 |
unsigned int sf, rm, opcode, rn, rd; |
2530 |
sf = extract32(insn, 31, 1); |
2531 |
rm = extract32(insn, 16, 5); |
2532 |
opcode = extract32(insn, 10, 6); |
2533 |
rn = extract32(insn, 5, 5); |
2534 |
rd = extract32(insn, 0, 5); |
2535 |
|
2536 |
if (extract32(insn, 29, 1)) { |
2537 |
unallocated_encoding(s); |
2538 |
return;
|
2539 |
} |
2540 |
|
2541 |
switch (opcode) {
|
2542 |
case 2: /* UDIV */ |
2543 |
handle_div(s, false, sf, rm, rn, rd);
|
2544 |
break;
|
2545 |
case 3: /* SDIV */ |
2546 |
handle_div(s, true, sf, rm, rn, rd);
|
2547 |
break;
|
2548 |
case 8: /* LSLV */ |
2549 |
handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); |
2550 |
break;
|
2551 |
case 9: /* LSRV */ |
2552 |
handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd); |
2553 |
break;
|
2554 |
case 10: /* ASRV */ |
2555 |
handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd); |
2556 |
break;
|
2557 |
case 11: /* RORV */ |
2558 |
handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd); |
2559 |
break;
|
2560 |
case 16: |
2561 |
case 17: |
2562 |
case 18: |
2563 |
case 19: |
2564 |
case 20: |
2565 |
case 21: |
2566 |
case 22: |
2567 |
case 23: /* CRC32 */ |
2568 |
unsupported_encoding(s, insn); |
2569 |
break;
|
2570 |
default:
|
2571 |
unallocated_encoding(s); |
2572 |
break;
|
2573 |
} |
2574 |
} |
2575 |
|
2576 |
/* C3.5 Data processing - register */
|
2577 |
static void disas_data_proc_reg(DisasContext *s, uint32_t insn) |
2578 |
{ |
2579 |
switch (extract32(insn, 24, 5)) { |
2580 |
case 0x0a: /* Logical (shifted register) */ |
2581 |
disas_logic_reg(s, insn); |
2582 |
break;
|
2583 |
case 0x0b: /* Add/subtract */ |
2584 |
if (insn & (1 << 21)) { /* (extended register) */ |
2585 |
disas_add_sub_ext_reg(s, insn); |
2586 |
} else {
|
2587 |
disas_add_sub_reg(s, insn); |
2588 |
} |
2589 |
break;
|
2590 |
case 0x1b: /* Data-processing (3 source) */ |
2591 |
disas_data_proc_3src(s, insn); |
2592 |
break;
|
2593 |
case 0x1a: |
2594 |
switch (extract32(insn, 21, 3)) { |
2595 |
case 0x0: /* Add/subtract (with carry) */ |
2596 |
disas_adc_sbc(s, insn); |
2597 |
break;
|
2598 |
case 0x2: /* Conditional compare */ |
2599 |
if (insn & (1 << 11)) { /* (immediate) */ |
2600 |
disas_cc_imm(s, insn); |
2601 |
} else { /* (register) */ |
2602 |
disas_cc_reg(s, insn); |
2603 |
} |
2604 |
break;
|
2605 |
case 0x4: /* Conditional select */ |
2606 |
disas_cond_select(s, insn); |
2607 |
break;
|
2608 |
case 0x6: /* Data-processing */ |
2609 |
if (insn & (1 << 30)) { /* (1 source) */ |
2610 |
disas_data_proc_1src(s, insn); |
2611 |
} else { /* (2 source) */ |
2612 |
disas_data_proc_2src(s, insn); |
2613 |
} |
2614 |
break;
|
2615 |
default:
|
2616 |
unallocated_encoding(s); |
2617 |
break;
|
2618 |
} |
2619 |
break;
|
2620 |
default:
|
2621 |
unallocated_encoding(s); |
2622 |
break;
|
2623 |
} |
2624 |
} |
2625 |
|
2626 |
/* C3.6 Data processing - SIMD and floating point */
|
2627 |
static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) |
2628 |
{ |
2629 |
unsupported_encoding(s, insn); |
2630 |
} |
2631 |
|
2632 |
/* C3.1 A64 instruction index by encoding */
|
2633 |
static void disas_a64_insn(CPUARMState *env, DisasContext *s) |
2634 |
{ |
2635 |
uint32_t insn; |
2636 |
|
2637 |
insn = arm_ldl_code(env, s->pc, s->bswap_code); |
2638 |
s->insn = insn; |
2639 |
s->pc += 4;
|
2640 |
|
2641 |
switch (extract32(insn, 25, 4)) { |
2642 |
case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */ |
2643 |
unallocated_encoding(s); |
2644 |
break;
|
2645 |
case 0x8: case 0x9: /* Data processing - immediate */ |
2646 |
disas_data_proc_imm(s, insn); |
2647 |
break;
|
2648 |
case 0xa: case 0xb: /* Branch, exception generation and system insns */ |
2649 |
disas_b_exc_sys(s, insn); |
2650 |
break;
|
2651 |
case 0x4: |
2652 |
case 0x6: |
2653 |
case 0xc: |
2654 |
case 0xe: /* Loads and stores */ |
2655 |
disas_ldst(s, insn); |
2656 |
break;
|
2657 |
case 0x5: |
2658 |
case 0xd: /* Data processing - register */ |
2659 |
disas_data_proc_reg(s, insn); |
2660 |
break;
|
2661 |
case 0x7: |
2662 |
case 0xf: /* Data processing - SIMD and floating point */ |
2663 |
disas_data_proc_simd_fp(s, insn); |
2664 |
break;
|
2665 |
default:
|
2666 |
assert(FALSE); /* all 15 cases should be handled above */
|
2667 |
break;
|
2668 |
} |
2669 |
|
2670 |
/* if we allocated any temporaries, free them here */
|
2671 |
free_tmp_a64(s); |
2672 |
} |
2673 |
|
2674 |
void gen_intermediate_code_internal_a64(ARMCPU *cpu,
|
2675 |
TranslationBlock *tb, |
2676 |
bool search_pc)
|
2677 |
{ |
2678 |
CPUState *cs = CPU(cpu); |
2679 |
CPUARMState *env = &cpu->env; |
2680 |
DisasContext dc1, *dc = &dc1; |
2681 |
CPUBreakpoint *bp; |
2682 |
uint16_t *gen_opc_end; |
2683 |
int j, lj;
|
2684 |
target_ulong pc_start; |
2685 |
target_ulong next_page_start; |
2686 |
int num_insns;
|
2687 |
int max_insns;
|
2688 |
|
2689 |
pc_start = tb->pc; |
2690 |
|
2691 |
dc->tb = tb; |
2692 |
|
2693 |
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
2694 |
|
2695 |
dc->is_jmp = DISAS_NEXT; |
2696 |
dc->pc = pc_start; |
2697 |
dc->singlestep_enabled = cs->singlestep_enabled; |
2698 |
dc->condjmp = 0;
|
2699 |
|
2700 |
dc->aarch64 = 1;
|
2701 |
dc->thumb = 0;
|
2702 |
dc->bswap_code = 0;
|
2703 |
dc->condexec_mask = 0;
|
2704 |
dc->condexec_cond = 0;
|
2705 |
#if !defined(CONFIG_USER_ONLY)
|
2706 |
dc->user = 0;
|
2707 |
#endif
|
2708 |
dc->vfp_enabled = 0;
|
2709 |
dc->vec_len = 0;
|
2710 |
dc->vec_stride = 0;
|
2711 |
|
2712 |
init_tmp_a64_array(dc); |
2713 |
|
2714 |
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
2715 |
lj = -1;
|
2716 |
num_insns = 0;
|
2717 |
max_insns = tb->cflags & CF_COUNT_MASK; |
2718 |
if (max_insns == 0) { |
2719 |
max_insns = CF_COUNT_MASK; |
2720 |
} |
2721 |
|
2722 |
gen_tb_start(); |
2723 |
|
2724 |
tcg_clear_temp_count(); |
2725 |
|
2726 |
do {
|
2727 |
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
2728 |
QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
2729 |
if (bp->pc == dc->pc) {
|
2730 |
gen_exception_insn(dc, 0, EXCP_DEBUG);
|
2731 |
/* Advance PC so that clearing the breakpoint will
|
2732 |
invalidate this TB. */
|
2733 |
dc->pc += 2;
|
2734 |
goto done_generating;
|
2735 |
} |
2736 |
} |
2737 |
} |
2738 |
|
2739 |
if (search_pc) {
|
2740 |
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
2741 |
if (lj < j) {
|
2742 |
lj++; |
2743 |
while (lj < j) {
|
2744 |
tcg_ctx.gen_opc_instr_start[lj++] = 0;
|
2745 |
} |
2746 |
} |
2747 |
tcg_ctx.gen_opc_pc[lj] = dc->pc; |
2748 |
tcg_ctx.gen_opc_instr_start[lj] = 1;
|
2749 |
tcg_ctx.gen_opc_icount[lj] = num_insns; |
2750 |
} |
2751 |
|
2752 |
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { |
2753 |
gen_io_start(); |
2754 |
} |
2755 |
|
2756 |
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
|
2757 |
tcg_gen_debug_insn_start(dc->pc); |
2758 |
} |
2759 |
|
2760 |
disas_a64_insn(env, dc); |
2761 |
|
2762 |
if (tcg_check_temp_count()) {
|
2763 |
fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", |
2764 |
dc->pc); |
2765 |
} |
2766 |
|
2767 |
/* Translation stops when a conditional branch is encountered.
|
2768 |
* Otherwise the subsequent code could get translated several times.
|
2769 |
* Also stop translation when a page boundary is reached. This
|
2770 |
* ensures prefetch aborts occur at the right place.
|
2771 |
*/
|
2772 |
num_insns++; |
2773 |
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
|
2774 |
!cs->singlestep_enabled && |
2775 |
!singlestep && |
2776 |
dc->pc < next_page_start && |
2777 |
num_insns < max_insns); |
2778 |
|
2779 |
if (tb->cflags & CF_LAST_IO) {
|
2780 |
gen_io_end(); |
2781 |
} |
2782 |
|
2783 |
if (unlikely(cs->singlestep_enabled) && dc->is_jmp != DISAS_EXC) {
|
2784 |
/* Note that this means single stepping WFI doesn't halt the CPU.
|
2785 |
* For conditional branch insns this is harmless unreachable code as
|
2786 |
* gen_goto_tb() has already handled emitting the debug exception
|
2787 |
* (and thus a tb-jump is not possible when singlestepping).
|
2788 |
*/
|
2789 |
assert(dc->is_jmp != DISAS_TB_JUMP); |
2790 |
if (dc->is_jmp != DISAS_JUMP) {
|
2791 |
gen_a64_set_pc_im(dc->pc); |
2792 |
} |
2793 |
gen_exception(EXCP_DEBUG); |
2794 |
} else {
|
2795 |
switch (dc->is_jmp) {
|
2796 |
case DISAS_NEXT:
|
2797 |
gen_goto_tb(dc, 1, dc->pc);
|
2798 |
break;
|
2799 |
default:
|
2800 |
case DISAS_JUMP:
|
2801 |
case DISAS_UPDATE:
|
2802 |
/* indicate that the hash table must be used to find the next TB */
|
2803 |
tcg_gen_exit_tb(0);
|
2804 |
break;
|
2805 |
case DISAS_TB_JUMP:
|
2806 |
case DISAS_EXC:
|
2807 |
case DISAS_SWI:
|
2808 |
break;
|
2809 |
case DISAS_WFI:
|
2810 |
/* This is a special case because we don't want to just halt the CPU
|
2811 |
* if trying to debug across a WFI.
|
2812 |
*/
|
2813 |
gen_helper_wfi(cpu_env); |
2814 |
break;
|
2815 |
} |
2816 |
} |
2817 |
|
2818 |
done_generating:
|
2819 |
gen_tb_end(tb, num_insns); |
2820 |
*tcg_ctx.gen_opc_ptr = INDEX_op_end; |
2821 |
|
2822 |
#ifdef DEBUG_DISAS
|
2823 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
2824 |
qemu_log("----------------\n");
|
2825 |
qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
2826 |
log_target_disas(env, pc_start, dc->pc - pc_start, |
2827 |
dc->thumb | (dc->bswap_code << 1));
|
2828 |
qemu_log("\n");
|
2829 |
} |
2830 |
#endif
|
2831 |
if (search_pc) {
|
2832 |
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
2833 |
lj++; |
2834 |
while (lj <= j) {
|
2835 |
tcg_ctx.gen_opc_instr_start[lj++] = 0;
|
2836 |
} |
2837 |
} else {
|
2838 |
tb->size = dc->pc - pc_start; |
2839 |
tb->icount = num_insns; |
2840 |
} |
2841 |
} |