Revision 52cc07d0 hw/slavio_misc.c
| b/hw/slavio_misc.c | ||
|---|---|---|
| 36 | 36 |
#ifdef DEBUG_MISC |
| 37 | 37 |
#define MISC_DPRINTF(fmt, args...) \ |
| 38 | 38 |
do { printf("MISC: " fmt , ##args); } while (0)
|
| 39 |
#define pic_set_irq_new(intctl, irq, level) \ |
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do { printf("MISC: set_irq(%d): %d\n", (irq), (level)); \
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pic_set_irq_new((intctl), (irq),(level));} while (0) |
|
| 39 | 42 |
#else |
| 40 | 43 |
#define MISC_DPRINTF(fmt, args...) |
| 41 | 44 |
#endif |
| ... | ... | |
| 45 | 48 |
uint8_t config; |
| 46 | 49 |
uint8_t aux1, aux2; |
| 47 | 50 |
uint8_t diag, mctrl, sysctrl; |
| 51 |
void *intctl; |
|
| 48 | 52 |
} MiscState; |
| 49 | 53 |
|
| 50 | 54 |
#define MISC_MAXADDR 1 |
| ... | ... | |
| 54 | 58 |
MiscState *s = opaque; |
| 55 | 59 |
|
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if ((s->aux2 & 0x4) && (s->config & 0x8)) {
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pic_set_irq(s->irq, 1);
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|
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pic_set_irq_new(s->intctl, s->irq, 1);
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|
| 58 | 62 |
} else {
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pic_set_irq(s->irq, 0);
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pic_set_irq_new(s->intctl, s->irq, 0);
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|
| 60 | 64 |
} |
| 61 | 65 |
} |
| 62 | 66 |
|
| ... | ... | |
| 207 | 211 |
return 0; |
| 208 | 212 |
} |
| 209 | 213 |
|
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void *slavio_misc_init(uint32_t base, int irq) |
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void *slavio_misc_init(uint32_t base, int irq, void *intctl)
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|
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{
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int slavio_misc_io_memory; |
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MiscState *s; |
| ... | ... | |
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cpu_register_physical_memory(base + 0xa000000, MISC_MAXADDR, slavio_misc_io_memory); |
| 234 | 238 |
|
| 235 | 239 |
s->irq = irq; |
| 240 |
s->intctl = intctl; |
|
| 236 | 241 |
|
| 237 | 242 |
register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load, s);
|
| 238 | 243 |
qemu_register_reset(slavio_misc_reset, s); |
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