target-ppc: Convert CPU definitions
Turn the array of model definitions into a set of self-registering QOMtypes with their own class_init. Unique identifiers are obtained fromthe combination of PVR, SVR and family identifiers; this requires allalias #defines to be removed from the list. Possibly there are some more...
target-ppc: Introduce abstract CPU family types
Instead of assigning *_<family> constants, set .parent to a family type.
Introduce a POWERPC_FAMILY() macro to keep type registration close toits implementation. This macro will need tweaking later.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-ppc: Set instruction flags on CPU family classes
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Extract 970 aliases
target-ppc: Extract POWER7 alias
target-ppc: Get model name from type name
We are about to drop the redundant name field along with ppc_def_t.
target-ppc: Extract MPC82xx_HiP{3, 4} aliases
target-ppc: Extract MPC52xx alias
target-ppc: Extract MPC5200/MPC5200B aliases
target-ppc: Extract MPC8240 alias
target-ppc: Extract 405GPe alias
target-ppc: Extract 604e alias
target-ppc: Extract MPC85xx aliases
target-ppc: Extract e500v1/e500v2 aliases
target-ppc: Extract MPC83xx aliases
target-ppc: Extract e300 alias
target-ppc: Extract e200 alias
target-ppc: Extract MPC82xx alias
target-ppc: Extract MPC8247/MPC8248/MPC8270-80 aliases
This depends on the fix for "G2leGP3" PVR.
target-ppc: Extract MPC82xx aliases to *_HiP4
target-ppc: Extract 7410 alias
target-ppc: Extract 7400 alias
target-ppc: Extract 7x5 aliases
target-ppc: Extract 750 aliases
target-ppc: Extract 740/750 aliases
target-ppc: Extract 603e alias
target-ppc: Extract 603r alias
target-ppc: Extract 601/601v aliases
target-ppc: Extract MGT823/MPC8xx as aliases
They used different PVRs but were defined to MPC8xx.
target-ppc: Extract 40x aliases
target-ppc: Extract 440 aliases
target-ppc: Turn "ppc32" and "ppc64" CPUs into aliases
target-ppc: Extract 74x7[A] aliases
target-ppc: Extract 74x5 as aliases
target-ppc: Extract 74x1 aliases
target-ppc: Extract 7450 alias
target-ppc: Extract 7448 alias
target-ppc: Update error handling in ppc_cpu_realize()
Commit fe828a4d4b7a5617cda7b24e95e327bfb71d790e added a new fatal errormessage while QOM realize'ification was in flight.
Convert it to return an Error instead of exit()ing.
target-ppc: Drop nested TARGET_PPC64 guard for POWER7
It is within a large TARGET_PPC64 section from 970 to 620,so an #endif /* TARGET_PPC64 */ is confusing. Clean this up.
target-ppc: Inline comma into POWERPC_DEF_SVR() macro
To repurpose the POWERPC_DEF_SVR() macro outside of an array,move the comma into the macro. No functional change.
target-ppc: Extract aliases from definitions list
Move definitions that were 100% identical except for the name into alist of aliases so that we don't register duplicate CPU types.Drop the accompanying comments since they don't really add value.
We need to support recursive lookup due to code names referencing a...
target-ppc: Make -cpu "ppc" an alias to "ppc32"
Drop the #if 0'ed alternative to make it "ppc64" for TARGET_PPC64.If we ever want to change it, we can more easily do so now.
target-ppc: Extract MPC5xx aliases
Their PVR differed but was defined to MPC5xx.
target-ppc: Fix CPU_POWERPC_MPC8547E
It was defined to ..._MPC8545E_v21 rather than ..._MPC8547E_v21.Due to both resolving to CPU_POWERPC_e500v2_v21 this did not show.
Fixing this nontheless helps with QOM'ifying CPU aliases.
target-ppc: Fix "G2leGP3" PVR
Unlike derived PVR constants mapped to CPU_POWERPC_G2LEgp3, the"G2leGP3" model definition itself used the CPU_POWERPC_G2LEgp1 PVR.
Fixing this will allow to alias CPU_POWERPC_G2LEgp3-using types to"G2leGP3".
gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
The gen_icount_start/end functions are now somewhat misnamed since theyare useful for generic "start/end of TB" code, used for more than justicount. Rename them to gen_tb_start/end.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
cpu: Introduce ENV_OFFSET macros
Introduce ENV_OFFSET macros which can be used in non-target-specificcode that needs to generate TCG instructions which reference CPUStatefields given the cpu_env register that TCG targets set up with apointer to the CPUArchState struct....
target-ppc: Fix SUBFE carry
While ~T0+T1+CF = T1-T0+CF-1 is true for the low 32-bits,it does not produce the correct carry-out to bit 33. Doexactly what the manual says.
Cc: Alexander Graf <agraf@suse.de>Signed-off-by: Richard Henderson <rth@twiddle.net>...
target-ppc: Use mul*2 in mulh* insns
Cc: Alexander Graf <agraf@suse.de>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-ppc: Split out SO, OV, CA fields from XER
In preparation for more efficient setting of these fields.
target-ppc: Use setcond in gen_op_cmp
Which means that callers need not copy data into local tmps.
target-ppc: Compute addition overflow without branches
target-ppc: Compute addition carry with setcond
target-ppc: Use add2 for carry generation
target-ppc: Implement neg in terms of subf
target-ppc: Compute arithmetic shift carry without branches
target-ppc: Compute mullwo without branches
cpu: Add CPUArchState pointer to CPUState
The target-specific ENV_GET_CPU() macros have allowed us to navigatefrom CPUArchState to CPUState. The reverse direction was not supported.Avoid introducing CPU_GET_ENV() macros by initializing an untypedpointer that is initialized in derived instance_init functions....
target-ppc: Move TCG initialization to PowerPCCPU initfn
Ensures that a QOM-created PowerPCCPU is usable.
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-ppc: Update PowerPCCPU to QOM realizefn
Adapt ppc_cpu_realize() signature, hook it up to DeviceClass and setrealized = true in cpu_ppc_init().
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
error: Strip trailing '\n' from error string arguments (again)
Commit 6daf194d and be62a2eb got rid of a bunch, but they keep comingback. Tracked down with this Coccinelle semantic patch:
r expression err, eno, cls, fmt; position p; @@ (...
r
cpu: do not use object_delete
CPUs are never added to the composition tree, so delete is achievedsimply by removing the last references to them.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
target-ppc: Fix target_ulong vs. hwaddr format mismatches
Since HWADDR_PRIx is always the same now, use %016 for TARGET_PPC64 and%08 for common code. This may slightly change the ppc64 debug output.
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
target-ppc: Fix build for PPC_DEBUG_DISAS
In r5949 / 76db3ba44ee8db671f804755f13b016eefd13288 (target-ppc: memoryload/store rework) variable little_endian was replaced with ctx.le_mode.Update the debug code.
PPC: Unify dcbzl code path
The bit that makes a dcbz instruction a dcbzl instruction was declared asreserved in ppc32 ISAs. However, hardware simply ignores the bit, makingcode valid if it simply invokes dcbzl instead of dcbz even on 750 and G4.
Thus, mark the bit as unreserved so that we properly emulate a simple dcbz...
target-ppc: Fix unused variable warning for FLUSH_ALL_TLBS
cpu: Add model resolution support to CPUClass
Introduce CPUClass::class_by_name and add a default implementation.Hook up the alpha and ppc implementations.
Introduce a wrapper function cpu_class_by_name().
kvm: Create kvm_arch_vcpu_id() function
This will allow each architecture to define how the VCPU ID is set onthe KVM_CREATE_VCPU ioctl call.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Acked-by: Gleb Natapov <gleb@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-ppc: Give a meaningful error if too many threads are specified
Currently the target-ppc tcg code only supports a single thread. You canspecify more, but they're treated identically to multiple cores. On KVMwe obviously can't support more threads than the hardware; if more are...
PPC: Provide zero SVR for -cpu e500mc and e5500
Even though our -cpu types for e500mc and e5500 are no real CPUs thatactually have version registers, a guest might still want to accesssaid version register and that has to succeed for a guest to be happy....
PPC: KVM: Add support for EPR with KVM
This patch links KVM EPR support to the existing TCG support we have now.
Signed-off-by: Alexander Graf <agraf@suse.de>
cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using anegative offset. Therefore the field is placed last in CPUState.
Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.
Move common parts of mips cpu_state_reset() to mips_cpu_reset()....
PPC: KVM: set has-idle in guest device tree
On e500mc, the platform doesn't provide a way for the CPU to go idle.
To still not uselessly burn CPU time, expose an idle hypercall to the guestif kvm supports it.
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>...
PPC: Bring EPR support closer to reality
We already used to support the external proxy facility of FSL MPICs,but only implemented it halfway correctly.
This patch adds support for
target-ppc: Slim conversion of model definitions to QOM subclasses
Since the model list is highly macrofied, keep ppc_def_t for now andsave a pointer to it in PowerPCCPUClass. This results in a flat list ofsubclasses including aliases, to be refined later....
target-ppc: Error out for -cpu host on unknown PVR
Previously we silently exited, with subclasses we got an opcode warning.Instead, explicitly tell the user what's wrong.
An indication for this is -cpu ? showing "host" with an all-zero PVR.
ppc/booke: fix crit/mcheck/debug exceptions
Book E does not play games with certain bits of xSRR1 being MSR savebits and others being error status. xSRR1 is the old MSR, period.This was causing things like MSR[CE] to be lost, even in the savedversion, as soon as you take an exception....
Merge branch 'master' of git://git.qemu.org/qemu into qom-cpu
Adapt header include paths.
cpu: Move kvm_state field into CPUState
Adapt some functions to take CPUState / {PowerPC,S390}CPU argument.
kvm: Pass CPUState to kvm_arch_*
Move kvm_vcpu_dirty field into CPUState to simplify things and changeits type to bool while at it.
kvm: Pass CPUState to kvm_vcpu_ioctl()
Adapt helper functions to pass X86CPU / PowerPCCPU / S390CPU.
fpu: move public header file to include/fpu
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
softmmu: move include files to include/sysemu/
misc: move include files to include/qemu/
qom: move include files to include/qom/
exec: move include files to include/exec/
build: kill libdis, move disassemblers to disas/
exec: refactor cpu_restore_state
Refactor common code around calls to cpu_restore_state().
tb_find_pc() has now no external users, make it static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-ppc: Don't use hwaddr to represent hardware state
The hwaddr type is somewhat vaguely defined as being able to contain busaddresses on the widest possible bus in the system. For that reason it'sdiscouraged for representing specific pieces of persistent hardware state,...
TCG: Use gen_opc_instr_start from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_pc from context instead of global variable.
TCG: Use gen_opc_icount from context instead of global variable.
PPC: Fix missing TRACE exception
This patch fixes bug 1031698 :https://bugs.launchpad.net/qemu/+bug/1031698
If we look at the (truncated) translation of the conditional branchinstruction in the test submitted in the bug post, the call to theexception helper is missing in the "bne-false" chunk of translated...
TCG: Use gen_opc_buf from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_ptr from context instead of global variable.
disas: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Richard Henderson <rth@twiddle.net>Acked-by: Aurelien Jarno <aurelien@aurel32.net>Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
Merge branch 'trivial-patches' of git://github.com/stefanha/qemu
ppc: add missing static
Add missing 'static' qualifiers.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Alexander Graf <agraf@suse.de>Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
target-ppc: make some functions static
Merge remote-tracking branch 'afaerber/qom-cpu' into staging