Revision 536ba015
| b/target-sparc/helper.c | ||
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| 379 | 379 |
/* |
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* UltraSparc IIi I/DMMUs |
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*/ |
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static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) |
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{
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return (x & mask) == (y & mask); |
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} |
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// Returns true if TTE tag is valid and matches virtual address value in context |
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// requires virtual address mask value calculated from TTE entry size |
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static inline int ultrasparc_tag_match(uint64_t tlb_tag, uint64_t tlb_tte, |
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uint64_t address, uint64_t context, |
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target_phys_addr_t *physical) |
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{
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uint64_t mask; |
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switch ((tlb_tte >> 61) & 3) {
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default: |
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case 0x0: // 8k |
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mask = 0xffffffffffffe000ULL; |
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break; |
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case 0x1: // 64k |
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mask = 0xffffffffffff0000ULL; |
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break; |
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case 0x2: // 512k |
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mask = 0xfffffffffff80000ULL; |
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break; |
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case 0x3: // 4M |
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mask = 0xffffffffffc00000ULL; |
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break; |
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} |
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// valid, context match, virtual address match? |
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if ((tlb_tte & 0x8000000000000000ULL) && |
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compare_masked(context, tlb_tag, 0x1fff) && |
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compare_masked(address, tlb_tag, mask)) |
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{
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// decode physical address |
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*physical = ((tlb_tte & mask) | (address & ~mask)) & 0x1ffffffe000ULL; |
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return 1; |
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} |
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return 0; |
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} |
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static int get_physical_address_data(CPUState *env, |
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target_phys_addr_t *physical, int *prot, |
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target_ulong address, int rw, int is_user) |
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{
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target_ulong mask; |
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unsigned int i; |
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uint64_t context; |
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if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
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*physical = ultrasparc_truncate_physical(address); |
| ... | ... | |
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return 0; |
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} |
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context = env->dmmuregs[1] & 0x1fff; |
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for (i = 0; i < 64; i++) {
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switch ((env->dtlb_tte[i] >> 61) & 3) {
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default: |
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case 0x0: // 8k |
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mask = 0xffffffffffffe000ULL; |
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break; |
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case 0x1: // 64k |
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mask = 0xffffffffffff0000ULL; |
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break; |
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case 0x2: // 512k |
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mask = 0xfffffffffff80000ULL; |
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break; |
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case 0x3: // 4M |
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mask = 0xffffffffffc00000ULL; |
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break; |
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} |
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// ctx match, vaddr match, valid? |
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if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
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(address & mask) == (env->dtlb_tag[i] & mask) &&
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(env->dtlb_tte[i] & 0x8000000000000000ULL)) {
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if (ultrasparc_tag_match(env->dtlb_tag[i], env->dtlb_tte[i],
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address, context, physical)
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) {
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// access ok? |
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if (((env->dtlb_tte[i] & 0x4) && is_user) || |
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(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
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| ... | ... | |
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#endif |
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return 1; |
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} |
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*physical = ((env->dtlb_tte[i] & mask) | (address & ~mask)) & |
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0x1ffffffe000ULL; |
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*prot = PAGE_READ; |
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if (env->dtlb_tte[i] & 0x2) |
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*prot |= PAGE_WRITE; |
| ... | ... | |
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#ifdef DEBUG_MMU |
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printf("DMISS at 0x%" PRIx64 "\n", address);
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#endif |
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env->dmmuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);
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env->dmmuregs[6] = (address & ~0x1fffULL) | context;
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env->exception_index = TT_DMISS; |
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return 1; |
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} |
| ... | ... | |
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target_phys_addr_t *physical, int *prot, |
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target_ulong address, int is_user) |
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{
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target_ulong mask; |
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unsigned int i; |
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uint64_t context; |
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if ((env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0) {
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/* IMMU disabled */ |
| ... | ... | |
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return 0; |
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} |
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context = env->dmmuregs[1] & 0x1fff; |
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for (i = 0; i < 64; i++) {
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switch ((env->itlb_tte[i] >> 61) & 3) {
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default: |
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case 0x0: // 8k |
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mask = 0xffffffffffffe000ULL; |
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break; |
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case 0x1: // 64k |
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mask = 0xffffffffffff0000ULL; |
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break; |
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case 0x2: // 512k |
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mask = 0xfffffffffff80000ULL; |
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break; |
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case 0x3: // 4M |
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mask = 0xffffffffffc00000ULL; |
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break; |
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} |
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// ctx match, vaddr match, valid? |
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if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
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(address & mask) == (env->itlb_tag[i] & mask) &&
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(env->itlb_tte[i] & 0x8000000000000000ULL)) {
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if (ultrasparc_tag_match(env->itlb_tag[i], env->itlb_tte[i],
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address, context, physical)
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) {
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// access ok? |
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if ((env->itlb_tte[i] & 0x4) && is_user) {
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if (env->immuregs[3]) /* Fault status register */ |
| ... | ... | |
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#endif |
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return 1; |
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} |
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*physical = ((env->itlb_tte[i] & mask) | (address & ~mask)) & |
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0x1ffffffe000ULL; |
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*prot = PAGE_EXEC; |
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return 0; |
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} |
| ... | ... | |
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printf("TMISS at 0x%" PRIx64 "\n", address);
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#endif |
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/* Context is stored in DMMU (dmmuregs[1]) also for IMMU */ |
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env->immuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);
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env->immuregs[6] = (address & ~0x1fffULL) | context;
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env->exception_index = TT_TMISS; |
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return 1; |
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} |
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